[coreboot] r3116 - in trunk/coreboot-v2/src: config mainboard/gigabyte/m57sli superio/ite/it8716f
svn at coreboot.org
svn at coreboot.org
Mon Feb 25 20:36:20 CET 2008
Author: ward
Date: 2008-02-25 20:36:20 +0100 (Mon, 25 Feb 2008)
New Revision: 3116
Added:
trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c
Modified:
trunk/coreboot-v2/src/config/Options.lb
trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb
trunk/coreboot-v2/src/superio/ite/it8716f/superio.c
Log:
This patch adds automatic fan control for the CPU fan on the m57sli
board.
This is done via the ec_init routine in a source file in the
mainboard/gigabyte/m57sli directory. A Config variable 'HAVE_FANCTL' has been
added to notify superio.c to get the ec_init externally.
I (Ward) have tested this on the PLCC and the SOIC/SPI version of this board.
It works.
Signed-off-by: Ronald Hoogenboom <hoogenboom30 at zonnet.nl>
Acked-by: Ward Vandewege <ward at gnu.org>
Modified: trunk/coreboot-v2/src/config/Options.lb
===================================================================
--- trunk/coreboot-v2/src/config/Options.lb 2008-02-25 10:15:10 UTC (rev 3115)
+++ trunk/coreboot-v2/src/config/Options.lb 2008-02-25 19:36:20 UTC (rev 3116)
@@ -861,6 +861,11 @@
# Misc device options
###############################################
+define HAVE_FANCTL
+ default 0
+ export used
+ comment "Include board specific FAN control initialization"
+end
define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
default 0
export used
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2008-02-25 10:15:10 UTC (rev 3115)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2008-02-25 19:36:20 UTC (rev 3116)
@@ -206,6 +206,10 @@
end
end
+if HAVE_FANCTL
+ object fanctl.o
+end
+
##
## Setup RAM
##
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2008-02-25 10:15:10 UTC (rev 3115)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2008-02-25 19:36:20 UTC (rev 3116)
@@ -115,6 +115,7 @@
uses CONFIG_USE_PRINTK_IN_CAR
+uses HAVE_FANCTL
###
### Build options
###
@@ -140,6 +141,11 @@
default CONFIG_LB_MEM_TOPK=2048
##
+## Set-up automatic fan control
+##
+default HAVE_FANCTL=1
+
+##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
Added: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c (rev 0)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c 2008-02-25 19:36:20 UTC (rev 3116)
@@ -0,0 +1,57 @@
+#include <arch/io.h>
+
+static void write_index(uint16_t port_base, uint8_t reg, uint8_t value)
+{
+ outb(reg, port_base);
+ outb(value, port_base + 1);
+}
+
+static const struct {
+ uint8_t index, value;
+} sequence[]= {
+ /* Set FAN_CTL control register (0x14) polarity to high, and
+ activate fans 1, 2 and 3. */
+ { 0x14, 0x87},
+ /* set the correct sensor types 1,2 thermistor; 3 diode */
+ { 0x51, 0x1c},
+ /* set the 'zero' voltage for diode type sensor */
+ { 0x5c, 0x80},
+// { 0x56, 0xe5},
+// { 0x57, 0xe5},
+ { 0x59, 0xe5},
+ { 0x5c, 0x00},
+ /* fan1 (controlled by temp3) control parameters */
+ /* fan off limit */
+ { 0x60, 0xff},
+ /* fan start limit */
+ { 0x61, 0x14},
+ /* ???? */
+// { 0x62, 0x00},
+ /* start PWM */
+ { 0x63, 0x27},
+ /* smooth and slope PWM */
+ { 0x64, 0x90},
+ /* direct-down and interval */
+ { 0x65, 0x03},
+ /* fan1 auto controlled by temp3 */
+ { 0x15, 0x82},
+ /* fan2 soft controlled, max speed */
+ { 0x16, 0x7f},
+ /* fan3 soft controlled, 75% speed */
+ { 0x17, 0x60},
+ /* all fans enable, fan1 ctl smart */
+ { 0x13, 0x71}
+};
+
+#define ARRAYSIZE(x) sizeof x/sizeof *x
+
+/*
+ * Called from superio.c
+ */
+void init_ec(uint16_t base)
+{
+ int i;
+ for (i=0; i<ARRAYSIZE(sequence); i++) {
+ write_index(base, sequence[i].index, sequence[i].value);
+ }
+}
Modified: trunk/coreboot-v2/src/superio/ite/it8716f/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8716f/superio.c 2008-02-25 10:15:10 UTC (rev 3115)
+++ trunk/coreboot-v2/src/superio/ite/it8716f/superio.c 2008-02-25 19:36:20 UTC (rev 3116)
@@ -62,6 +62,9 @@
return inb(port_base + 1);
}
+#ifdef HAVE_FANCTL
+extern void init_ec(uint16_t base);
+#else
static void init_ec(uint16_t base)
{
uint8_t value;
@@ -77,6 +80,7 @@
printk_debug("FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n",
base + 0x14, value | 0x87);
}
+#endif
static void it8716f_init(device_t dev)
{
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