[coreboot] v2[PATCH]RCA RM4100 i82830 support
peter at stuge.se
Tue Feb 26 02:27:37 CET 2008
On Mon, Feb 25, 2008 at 04:31:15PM -0500, joe at smittys.pointclark.net wrote:
> Dis-reguard the last patch, this is the real one. A e100 kernel driver
> developer helped me figure out that the ethernet was an irq routing
> issue, fixed! It is working great now:-)))
Do you have any idea about the TV out?
Also see the comments below:
> +++ src/northbridge/intel/i82830/raminit.c (revision 0)
> +static void set_dram_timing(const struct mem_controller *ctrl)
> + /* Set the value for DRAM Timing Register */
> + /* TODO: Configure the value according to SPD values. */
> + pci_write_config32(ctrl->d0, DRT, 0x00000010);
> +static void set_dram_buffer_strength(const struct mem_controller *ctrl)
> + /* TODO: This needs to be set according to the DRAM tech
> + * (x8, x16, or x32). Argh, Intel provides no docs on this!
> + * Currently, it needs to be pulled from the output of
> + * lspci -xxx Rx92
> + */
> + /* Set the value for System Memory Buffer Strength Control Registers */
> + pci_write_config32(ctrl->d0, BUFF_SC, 0xFC9B491B);
How about these two TODOs? In the second case I think the comment
refers to running the command under the factory BIOS - in that case
it would be good to clarify that.
> +static void sdram_enable(int controllers, const struct mem_controller *ctrl)
> + /* 4. Mode register set. Wait two memory cycles. */
> + /* TODO: Set offset according to DRT values */
> + PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
> + do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0);
Can this be done?
> +++ targets/rca/rm4100/Config.lb (revision 0)
> +romimage "fallback"
> + option USE_FALLBACK_IMAGE = 1
> + option FALLBACK_SIZE = ROM_SIZE
> + option COREBOOT_EXTRA_VERSION = "_RM4100"
> +# payload /etc/hosts
This last line makes no sense so I would remove it before the commit.
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