[LinuxBIOS] r543 - in LinuxBIOSv3: arch/x86/geodelx include/arch/x86

[svn at openbios.org]

Author: hailfinger
Date: 2008-01-04 13:53:09 +0100 (Fri, 04 Jan 2008)
New Revision: 543

Modified:
   LinuxBIOSv3/arch/x86/geodelx/stage0.S
   LinuxBIOSv3/include/arch/x86/amd_geodelx.h
Log:
Move AMD Geode LX defines for CAR from a .S to a .h so they are
available to C.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: LinuxBIOSv3/arch/x86/geodelx/stage0.S
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/stage0.S	2007-12-11 01:24:52 UTC (rev 542)
+++ LinuxBIOSv3/arch/x86/geodelx/stage0.S	2008-01-04 12:53:09 UTC (rev 543)
@@ -28,24 +28,6 @@
 #include "../macros.h"
 #include <amd_geodelx.h>
 
-/* This is where the DCache will be mapped and be used as stack. It would be
- * cool if it was the same base as LinuxBIOS normal stack.
- */
-#define LX_STACK_BASE		DCACHE_RAM_BASE
-#define LX_STACK_END		LX_STACK_BASE + (DCACHE_RAM_SIZE - 4)
-
-#define LX_NUM_CACHELINES	0x080	/* There are 128 lines per way. */
-#define LX_CACHELINE_SIZE	0x020	/* There are 32 bytes per line. */
-#define LX_CACHEWAY_SIZE	(LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
-#define CR0_CD			0x40000000 /* Bit 30 = Cache Disable */
-#define CR0_NW			0x20000000 /* Bit 29 = Not Write Through */
-
-#define ROM_CODE_SEG		0x08
-#define ROM_DATA_SEG		0x10
-
-#define CACHE_RAM_CODE_SEG	0x18
-#define CACHE_RAM_DATA_SEG	0x20
-
 	.code16
 	.globl _stage0
 _stage0:

Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h
===================================================================
--- LinuxBIOSv3/include/arch/x86/amd_geodelx.h	2007-12-11 01:24:52 UTC (rev 542)
+++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h	2008-01-04 12:53:09 UTC (rev 543)
@@ -567,7 +567,24 @@
 /* ------------------------  */
 #define DCACHE_RAM_SIZE 0x08000
 #define DCACHE_RAM_BASE 0xc8000
+/* This is where the DCache will be mapped and be used as stack. It would be
+ * cool if it was the same base as LinuxBIOS normal stack.
+ */
+#define LX_STACK_BASE		DCACHE_RAM_BASE
+#define LX_STACK_END		LX_STACK_BASE + (DCACHE_RAM_SIZE - 4)
 
+#define LX_NUM_CACHELINES	0x080	/* There are 128 lines per way. */
+#define LX_CACHELINE_SIZE	0x020	/* There are 32 bytes per line. */
+#define LX_CACHEWAY_SIZE	(LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
+#define CR0_CD			0x40000000 /* Bit 30 = Cache Disable */
+#define CR0_NW			0x20000000 /* Bit 29 = Not Write Through */
+
+#define ROM_CODE_SEG		0x08
+#define ROM_DATA_SEG		0x10
+
+#define CACHE_RAM_CODE_SEG	0x18
+#define CACHE_RAM_DATA_SEG	0x20
+
 /* POST CODES */
 /* standard AMD post definitions -- might as well use them. */