[coreboot] AMD Family 0Fh CAR and L1 cache tags

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Tue Jan 15 15:19:29 CET 2008


The BKDG rev. 3.08 for AMD Family 0Fh states that it is possible to use
a CAR area with a size of 64K in section 13.16 "Cache Initialization For
General Storage During Boot". It also says that during DRAM training CAR
size must be reduced. For DDR training, 256 cache lines with L1 cache
tag indexes 00h-FFh are reserved and must not be used as CAR. The text
then refers to the AMD64 Arch Programmers Manual Vol. 2 for more details
on L1 function. However, I couldn't find any explanation why L1 cache
tag indexes 00h-FFh correspond to address space C0000h-C3FFFh when fixed
size MTRRs are active.

Explanations would be very welcome.


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