[coreboot] AMD Family 0Fh CAR and L1 cache tags

Marc Jones marc.jones at amd.com
Tue Jan 15 18:54:27 CET 2008

Carl-Daniel Hailfinger wrote:
> Hi!
> The BKDG rev. 3.08 for AMD Family 0Fh states that it is possible to use
> a CAR area with a size of 64K in section 13.16 "Cache Initialization For
> General Storage During Boot". It also says that during DRAM training CAR
> size must be reduced. For DDR training, 256 cache lines with L1 cache
> tag indexes 00h-FFh are reserved and must not be used as CAR. The text
> then refers to the AMD64 Arch Programmers Manual Vol. 2 for more details
> on L1 function. However, I couldn't find any explanation why L1 cache
> tag indexes 00h-FFh correspond to address space C0000h-C3FFFh when fixed
> size MTRRs are active.

I may be misunderstanding your question but I don't think that tag 
indexes 00h-ffh have to correspond to C0000h-C3FFFh. I'm also not 
positive that they must be tag indexes 00h-ffh. I think that they could 
be on the end as long as the tags are contiguous. This comment refers 
DDR training needing the space to hold test patterns for dqs eye finding 
during memory training. See northbridge\amd\amdk8\raminit_f_dqs.c 
TrainDQSRdWrPos(). For coreboot, it looks like the test patterns are 
just pushed onto the stack. For AMD BIOS code, this is not the case and 
they are put into the cache at a set location. (I think that this is 
easier for the AGESA asm code to handle that way).


Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com

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