[coreboot] AMD Family 0Fh CAR and L1 cache tags

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Wed Jan 16 23:03:45 CET 2008

On 16.01.2008 21:58, Marc Jones wrote:
> Carl-Daniel Hailfinger wrote:
>> As I understand the logic of the snippet above, we look for a DQSWrDelay
>> which does not give any errors with TrainReadDQS. Then we don't care
>> about errors for other values of DQSWrDelay and use the current value of
>> DQSWrDelay to run TrainWriteDQS.
>> If TrainReadDQS failed for all values of DQSWrDelay, we return the
>> bitwise OR of all error conditions we had for all values of DQSWrDelay.
>> Does that really make sense?
> Any bit set means fail. Caller checks !=0. I think it is fine. I guess
> it could be translated to a pass/fail. If there are no passing case
> the reason doesn't really matter. The real errors are reported in
> TrainDQSPos(). Does that answer your question?

Yes, that indeed does explain the code. Thanks!


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