[coreboot] [PATCH] (resend) fix the flashrom problem on m57sli boards with SPI flash
echelon at free.fr
Thu Jan 17 15:33:19 CET 2008
Quoting Peter Stuge <peter at stuge.se>:
> On Thu, Jan 17, 2008 at 01:40:07PM +0100, Florentin Demetrescu wrote:
> > + /* FIXME : really dirty! It seems that the IO addr range for the SPI IF.
> > + HAS to be set into the 0xb0 or 0xb4 reg which conflicts strongly with
> > + mcp55_lpc_enable_childrens_resources() */
> > + pci_write_config32(dev, conf->spi_sio_pcireg, conf->spi_sio_iorange);
> Can you expand on this comment? What would be the clean way and what
> is the conflict in the mcp55 code?
In the procedure "mcp55_lpc_enable_childrens_resources()" at line 335 in
mcp55_lpc.c one founds this loop :
pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
Given that "var_num" can be btw 0 and 3, when i=2 one gets 0xa8 + i*4 = 0xb0,
so this procedure thrashes the value set by the patched procedure "lpc_init()"
The clean way to fix this? Unfortunately I see no one, unless we have access to
some NDAed documentation, as I have no idea why the 0x0800->0x085f IO range must
be set into the 0xb0 or 0xb4 pci registers.. Maybe Yinghai could give some
And a last remark : in some previous posts concerning this topic, people speak
about gpio configuration.. IMHO, this isn't related in any way with the gpio
configuration issue (nor in SB, not even in SIO), but only to the IO address
decoding (and "routing") inside the southbridge.
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