[coreboot] SST25VF016B (2MB) flash on m57sli (IT8716F).
rminnich at gmail.com
Fri Jan 18 18:39:52 CET 2008
On Jan 18, 2008 6:49 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> I have a mad scheme which would work for v3 without downsides (except
> for the fact that the boot block and initram have to be in the upper 512
> kB, but that's the case anyway even without my scheme).
> Basically, we create a flat LAR-in-LAR structure. Before you start to
> barf, listen:
> Instead of storing real flash size at the top of ROM, we store a virtual
> size which corresponds to the start of the first LAR member in the top
> 512 kB block. This virtual size is what all LAR parsing uses until CAR
> has been disabled. Then we shadow the entire ROM somewhere in RAM and
> further accesses to the ROM will be directed there, including all LAR
That's fine, it's very simliar to what I had to do for the brain-dead
chip that had a 64K hole in FLASH at (0-64K) -- had to shadow it at
0x2000000. We're going to see this problem again and again, we might
as well figure it out now.
> Can you test the modified variant I posted as a reply to Ronald? It
> should work as well and fit a little better into flashrom structure.
The top 512 flash fine, the lower 1.5M did not flash, but did erase,
maybe. hard to say if
coreboot appears to not have booted, sadly.
More information about the coreboot