[coreboot] progress on lx
c-d.hailfinger.devel.2006 at gmx.net
Sat Jan 19 18:48:03 CET 2008
On 19.01.2008 18:07, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
>> On 19.01.2008 07:39, ron minnich wrote:
>>> Marc, should we modify the LX build to somehow wget the VSA and copy
>>> it in to LAR? Or should we have a top-level "blob" directory in v3
>>> that includes the vsa file, and then build it in to LAR?
>> Please don't store any blobs in the v3 tree directly.
>> That's where buildrom comes into play. Buildrom can always wget/curl
>> these blobs from http://coreboot.org. Then it stores them in the LAR
>> below the "blob/" directory.
>> If you are absolutely desparate to include the VSA in a non-buildrom
>> build of v3, you still can download the VSA manually.
> There's a repository on coreboot.org for binary blobs that can be used
> with coreboot. It's at
> I suggest that one should be used for storing VSA too. We can also
> rename it, if you dont like the name.
Agreed. It looks like a nice way to store the VSA. However, it would be
nice if the VSA was also available via wget.
> We can also pull it into the main coreboot v3 tree with svn:external
> if that's what people want.
Please don't. That way, everyone checking out v3 will have to wait for
the download of all option ROMs and all VSA variants because they were
referenced with svn:external.
>>> I am thinking it is now time to solve the VSA problem, and LAR is
>>> the key piece.
>> Yes, but we need a way to specify the entry point of the VSA blob for
>> that to work reliably.
> I think that problem has been solved already in v2. We should do it
> the same way in v3, with the difference that the file is stored in a lar.
>>> Also, it looks like we need to actually run the lar code in stage 2
>>> phase 2, i.e. the setup for pci scan stage. I had not anticipated this
>>> at all. Any ideas here?
>> Why should that be a problem?
> We can also put a stage between stage1 and stage2 for VSA. I guess the
> concern is that VSA needs RAM set up, and it is needed by the PCI scan
> code to work correctly?
What exactly does stop us from using stage 2 phase 1 for that purpose?
More information about the coreboot