[coreboot] SST25VF016B (2MB) flash on m57sli (IT8716F).
c-d.hailfinger.devel.2006 at gmx.net
Tue Jan 22 00:57:55 CET 2008
On 21.01.2008 00:47, Ronald Hoogenboom wrote:
> On Mon, 2008-01-21 at 00:24 +0100, Ronald Hoogenboom wrote:
>> (LPC is the only datapath to the SB and CPU, so it has to!). We could
>> optimize by omitting the wait for SPI ready when there is no data to be
>> read, eg. readcnt==0. I'll have a look at what can be gained by that.
> Omitting it saves 10 seconds with the unconditional 10us delay, reducing
> to 40~45 secs. So I think it is worth putting it in. With the
> conditional delay, it is not so easily measurable, because of the
> natural variance much larger than 10 us...
> Patch follows...
> Signed-off-by: Ronald Hoogenboom <hoogenboom30 at zonnet.nl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Committed in r3068.
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