[coreboot] r564 - in coreboot-v3: . arch/x86 arch/x86/geodelx device doc/design include include/arch/x86 include/arch/x86/arch include/device lib mainboard mainboard/adl mainboard/adl/msm800sev mainboard/amd mainboard/amd/norwich mainboard/artecgroup mainboard/artecgroup/dbe61 mainboard/emulation mainboard/emulation/qemu-x86 mainboard/pcengines mainboard/pcengines/alix1c northbridge/amd/geodelx northbridge/intel/i440bxemulation southbridge/amd/cs5536 southbridge/intel/i82371eb superio/fintek/f71805f superio/winbond/w83627hf util util/doxygen util/dtc util/kconfig util/lar util/lzma util/nrv2b util/options util/x86emu util/x86emu/include/x86emu util/x86emu/pcbios util/x86emu/x86emu util/xcompile
svn at coreboot.org
svn at coreboot.org
Sun Jan 27 19:54:58 CET 2008
Author: stepan
Date: 2008-01-27 19:54:57 +0100 (Sun, 27 Jan 2008)
New Revision: 564
Modified:
coreboot-v3/HACKING
coreboot-v3/Kconfig
coreboot-v3/Makefile
coreboot-v3/README
coreboot-v3/Rules.make
coreboot-v3/arch/x86/Kconfig
coreboot-v3/arch/x86/Makefile
coreboot-v3/arch/x86/archtables.c
coreboot-v3/arch/x86/geodelx/cpu.c
coreboot-v3/arch/x86/geodelx/geodelx.c
coreboot-v3/arch/x86/geodelx/stage0.S
coreboot-v3/arch/x86/geodelx/stage1.c
coreboot-v3/arch/x86/i8259.c
coreboot-v3/arch/x86/ldscript.ld
coreboot-v3/arch/x86/linuxbios_table.c
coreboot-v3/arch/x86/macros.h
coreboot-v3/arch/x86/mc146818rtc.c
coreboot-v3/arch/x86/post_code.c
coreboot-v3/arch/x86/serial.c
coreboot-v3/arch/x86/speaker.c
coreboot-v3/arch/x86/stage0_i586.S
coreboot-v3/arch/x86/stage1.c
coreboot-v3/arch/x86/udelay_io.c
coreboot-v3/device/Kconfig
coreboot-v3/device/Makefile
coreboot-v3/device/agp_device.c
coreboot-v3/device/cardbus_device.c
coreboot-v3/device/device.c
coreboot-v3/device/device_util.c
coreboot-v3/device/hypertransport.c
coreboot-v3/device/pci_device.c
coreboot-v3/device/pci_ops.c
coreboot-v3/device/pci_rom.c
coreboot-v3/device/pcie_device.c
coreboot-v3/device/pcix_device.c
coreboot-v3/device/pnp_device.c
coreboot-v3/device/pnp_raw.c
coreboot-v3/device/root_device.c
coreboot-v3/device/smbus_ops.c
coreboot-v3/doc/design/flashlayout.fig
coreboot-v3/doc/design/newboot.lyx
coreboot-v3/include/arch/x86/amd_geodelx.h
coreboot-v3/include/arch/x86/arch/spinlock.h
coreboot-v3/include/arch/x86/cpu.h
coreboot-v3/include/arch/x86/div64.h
coreboot-v3/include/arch/x86/legacy.h
coreboot-v3/include/arch/x86/msr.h
coreboot-v3/include/arch/x86/swab.h
coreboot-v3/include/device/device.h
coreboot-v3/include/device/pci.h
coreboot-v3/include/device/pci_ids.h
coreboot-v3/include/elf.h
coreboot-v3/include/ip_checksum.h
coreboot-v3/include/isa-dma.h
coreboot-v3/include/keyboard.h
coreboot-v3/include/lar.h
coreboot-v3/include/lib.h
coreboot-v3/include/mc146818rtc.h
coreboot-v3/include/post_code.h
coreboot-v3/include/shared.h
coreboot-v3/include/spd.h
coreboot-v3/include/spinlock.h
coreboot-v3/include/string.h
coreboot-v3/include/tables.h
coreboot-v3/lib/Kconfig
coreboot-v3/lib/Makefile
coreboot-v3/lib/clog2.c
coreboot-v3/lib/compute_ip_checksum.c
coreboot-v3/lib/console.c
coreboot-v3/lib/delay.c
coreboot-v3/lib/elfboot.c
coreboot-v3/lib/lar.c
coreboot-v3/lib/lzma.c
coreboot-v3/lib/mem.c
coreboot-v3/lib/ram.c
coreboot-v3/lib/stage2.c
coreboot-v3/lib/string.c
coreboot-v3/lib/tables.c
coreboot-v3/lib/vsprintf.c
coreboot-v3/lib/vtxprintf.c
coreboot-v3/mainboard/Kconfig
coreboot-v3/mainboard/adl/Kconfig
coreboot-v3/mainboard/adl/msm800sev/Kconfig
coreboot-v3/mainboard/adl/msm800sev/Makefile
coreboot-v3/mainboard/adl/msm800sev/dts
coreboot-v3/mainboard/adl/msm800sev/initram.c
coreboot-v3/mainboard/adl/msm800sev/stage1.c
coreboot-v3/mainboard/amd/Kconfig
coreboot-v3/mainboard/amd/norwich/Kconfig
coreboot-v3/mainboard/amd/norwich/Makefile
coreboot-v3/mainboard/amd/norwich/dts
coreboot-v3/mainboard/amd/norwich/initram.c
coreboot-v3/mainboard/amd/norwich/stage1.c
coreboot-v3/mainboard/artecgroup/Kconfig
coreboot-v3/mainboard/artecgroup/dbe61/Kconfig
coreboot-v3/mainboard/artecgroup/dbe61/Makefile
coreboot-v3/mainboard/artecgroup/dbe61/dts
coreboot-v3/mainboard/artecgroup/dbe61/initram.c
coreboot-v3/mainboard/artecgroup/dbe61/stage1.c
coreboot-v3/mainboard/emulation/Kconfig
coreboot-v3/mainboard/emulation/qemu-x86/Kconfig
coreboot-v3/mainboard/emulation/qemu-x86/Makefile
coreboot-v3/mainboard/emulation/qemu-x86/dts
coreboot-v3/mainboard/emulation/qemu-x86/initram.c
coreboot-v3/mainboard/emulation/qemu-x86/initram_printktest.c
coreboot-v3/mainboard/emulation/qemu-x86/stage1.c
coreboot-v3/mainboard/emulation/qemu-x86/vga.c
coreboot-v3/mainboard/pcengines/Kconfig
coreboot-v3/mainboard/pcengines/alix1c/Kconfig
coreboot-v3/mainboard/pcengines/alix1c/Makefile
coreboot-v3/mainboard/pcengines/alix1c/dts
coreboot-v3/mainboard/pcengines/alix1c/initram.c
coreboot-v3/mainboard/pcengines/alix1c/stage1.c
coreboot-v3/northbridge/amd/geodelx/Makefile
coreboot-v3/northbridge/amd/geodelx/dts
coreboot-v3/northbridge/amd/geodelx/geodelx.c
coreboot-v3/northbridge/amd/geodelx/geodelxinit.c
coreboot-v3/northbridge/amd/geodelx/raminit.c
coreboot-v3/northbridge/amd/geodelx/raminit.h
coreboot-v3/northbridge/intel/i440bxemulation/Kconfig
coreboot-v3/northbridge/intel/i440bxemulation/Makefile
coreboot-v3/northbridge/intel/i440bxemulation/dts
coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c
coreboot-v3/northbridge/intel/i440bxemulation/i440bx.h
coreboot-v3/southbridge/amd/cs5536/Makefile
coreboot-v3/southbridge/amd/cs5536/cs5536.c
coreboot-v3/southbridge/amd/cs5536/cs5536.h
coreboot-v3/southbridge/amd/cs5536/dts
coreboot-v3/southbridge/amd/cs5536/smbus_initram.c
coreboot-v3/southbridge/amd/cs5536/stage1.c
coreboot-v3/southbridge/intel/i82371eb/Makefile
coreboot-v3/southbridge/intel/i82371eb/dts
coreboot-v3/southbridge/intel/i82371eb/i82371eb.c
coreboot-v3/superio/fintek/f71805f/Makefile
coreboot-v3/superio/fintek/f71805f/dts
coreboot-v3/superio/fintek/f71805f/f71805f.h
coreboot-v3/superio/fintek/f71805f/stage1.c
coreboot-v3/superio/fintek/f71805f/superio.c
coreboot-v3/superio/winbond/w83627hf/Makefile
coreboot-v3/superio/winbond/w83627hf/dts
coreboot-v3/superio/winbond/w83627hf/stage1.c
coreboot-v3/superio/winbond/w83627hf/superio.c
coreboot-v3/superio/winbond/w83627hf/w83627hf.h
coreboot-v3/util/Makefile
coreboot-v3/util/doxygen/Doxyfile.LinuxBIOS
coreboot-v3/util/dtc/dtc.c
coreboot-v3/util/dtc/dtc.h
coreboot-v3/util/dtc/endian.h
coreboot-v3/util/dtc/flattree.c
coreboot-v3/util/kconfig/confdata.c
coreboot-v3/util/kconfig/gconf.c
coreboot-v3/util/kconfig/mconf.c
coreboot-v3/util/kconfig/util.c
coreboot-v3/util/kconfig/zconf.tab.c_shipped
coreboot-v3/util/kconfig/zconf.y
coreboot-v3/util/lar/Makefile
coreboot-v3/util/lar/README
coreboot-v3/util/lar/bootblock.c
coreboot-v3/util/lar/example.c
coreboot-v3/util/lar/lar.c
coreboot-v3/util/lar/lar.h
coreboot-v3/util/lar/lib.c
coreboot-v3/util/lar/lib.h
coreboot-v3/util/lar/stream.c
coreboot-v3/util/lzma/Makefile
coreboot-v3/util/nrv2b/Makefile
coreboot-v3/util/options/Makefile
coreboot-v3/util/options/build_opt_tbl.c
coreboot-v3/util/x86emu/Makefile
coreboot-v3/util/x86emu/biosemu.c
coreboot-v3/util/x86emu/include/x86emu/x86emu.h
coreboot-v3/util/x86emu/pcbios/pcibios.c
coreboot-v3/util/x86emu/pcbios/pcibios.h
coreboot-v3/util/x86emu/vm86.c
coreboot-v3/util/x86emu/x86emu/sys.c
coreboot-v3/util/xcompile/xcompile
Log:
Now version 3: LinuxBIOS -> coreboot rename.
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Modified: coreboot-v3/HACKING
===================================================================
--- coreboot-v3/HACKING 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/HACKING 2008-01-27 18:54:57 UTC (rev 564)
@@ -5,13 +5,13 @@
Development Guidelines
----------------------
-Please read http://linuxbios.org/Development_Guidelines.
+Please read http://www.coreboot.org/Development_Guidelines.
Doxygen-generated Code/API Documentation
----------------------------------------
-The source code of LinuxBIOS is documented using Doxygen-style code comments.
+The source code of coreboot is documented using Doxygen-style code comments.
The Doxygen tool can generate HTML API documentation out of these comments.
You can generate this documentation via:
@@ -22,7 +22,7 @@
The generation of the documentation takes ca. 1-2 minutes, and may require
more than 30 MB of space on the hard drive, depending on the options
-selected in the Doxygen config file, util/doxygen/Doxyfile.LinuxBIOS.
+selected in the Doxygen config file, util/doxygen/Doxyfile.coreboot.
Required software:
@@ -57,7 +57,7 @@
Current version we use: 15508d22d00277a1f2a1022dce38f2772c810d32 (02/2006)
* util/lar/*: GPLv2
- Independant project, but written specifically for LinuxBIOS.
+ Independant project, but written specifically for coreboot.
* include/lar.h, util/lar/lar.h, util/lar/example.c:
Dual-licensed (GPLv2 + revised BSD license)
Modified: coreboot-v3/Kconfig
===================================================================
--- coreboot-v3/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2006 Ronald G. Minnich <rminnich at gmail.com>
## Copyright (C) 2006 Segher Boessenkool <segher at kernel.crashing.org>
@@ -26,7 +26,7 @@
# see http://lxr.linux.no/source/Documentation/kbuild/kconfig-language.txt.
#
-mainmenu "LinuxBIOS Configuration"
+mainmenu "coreboot configuration"
menu "General setup"
@@ -43,22 +43,22 @@
bool "Expert mode"
help
This allows you to select certain advanced configuration options.
- It is mainly intended for LinuxBIOS developers.
+ It is mainly intended for coreboot developers.
Warning: Only enable this option if you really know what you're
doing! You have been warned!
config LOCALVERSION
- string "Local version - append to LinuxBIOS release"
+ string "Local version - append to coreboot release"
help
- Append an extra string to the end of the LinuxBIOS version.
+ Append an extra string to the end of the coreboot version.
config BEEPS
- bool "Enable beeps upon certain LinuxBIOS events"
+ bool "Enable beeps upon certain coreboot events"
depends EXPERT
default n
help
- Enable this option to make LinuxBIOS beep upon certain events.
+ Enable this option to make coreboot beep upon certain events.
endmenu
@@ -101,7 +101,7 @@
depends EXPERT
default n
help
- Until now, LinuxBIOS has used ELF for the payload. There are many
+ Until now, coreboot has used ELF for the payload. There are many
problems with this, not least being the inefficiency -- the ELF has
to be decompressed to memory and then the segments have to be
copied. Plus, lar can't see the segments in the ELF -- to see all
@@ -113,17 +113,17 @@
flashed the FLASH and rebooted the machine. Boot time is really
not the time you want to find out your ELF payload is broken.
- With this option, LinuxBIOS will direct lar to break each ELF
+ With this option, coreboot will direct lar to break each ELF
segment into a LAR entry. ELF will not be used at all. Note that
- (for now) LinuxBIOS is backward compatible -- if you put an ELF
- payload in, LinuxBIOS can still parse it. We hope to remove ELF
+ (for now) coreboot is backward compatible -- if you put an ELF
+ payload in, coreboot can still parse it. We hope to remove ELF
entirely in the future.
config PAYLOAD_ELF
bool "An ELF executable payload file"
help
Select this option if you have a payload image (an ELF file)
- which LinuxBIOS should run as soon as the basic hardware
+ which coreboot should run as soon as the basic hardware
initialization is completed.
You will be able to specify the location and file name of the
@@ -132,8 +132,8 @@
config PAYLOAD_NONE
bool "No payload"
help
- Select this option if you want to create an "empty" LinuxBIOS
- ROM image for a certain mainboard, i.e. a LinuxBIOS ROM image
+ Select this option if you want to create an "empty" coreboot
+ ROM image for a certain mainboard, i.e. a coreboot ROM image
which does not yet contain a payload.
For such an image to be useful, you have to use the 'lar' tool
Modified: coreboot-v3/Makefile
===================================================================
--- coreboot-v3/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,7 +1,7 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
-## LinuxBIOS build system Lbuild
+## coreboot build system Lbuild
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
@@ -72,16 +72,16 @@
include $(src)/.config
ifneq ($(CONFIG_LOCALVERSION),"")
-LINUXBIOS_EXTRA_VERSION := -$(shell echo $(CONFIG_LOCALVERSION))
+COREBOOT_EXTRA_VERSION := -$(shell echo $(CONFIG_LOCALVERSION))
endif
-all: prepare prepare2 $(obj)/linuxbios.rom
+all: prepare prepare2 $(obj)/coreboot.rom
$(Q)printf " DONE\n"
ARCH:=$(shell echo $(CONFIG_ARCH))
MAINBOARDDIR=$(shell echo $(CONFIG_MAINBOARD_NAME))
-LINUXBIOSINCLUDE := -I$(src) -Iinclude \
+COREBOOTINCLUDE := -I$(src) -Iinclude \
-I$(src)/include \
-I$(src)/include/arch/$(ARCH)/ \
-include $(obj)/config.h \
@@ -96,8 +96,8 @@
CFLAGS += $(CFLAGS_$(ARCH))
-CPPFLAGS := $(LINUXBIOSINCLUDE)
-CFLAGS += $(LINUXBIOSINCLUDE)
+CPPFLAGS := $(COREBOOTINCLUDE)
+CFLAGS += $(COREBOOTINCLUDE)
# Note: This _must_ come after 'CC' is set for the second time in this
# Makefile (see above), otherwise the build would break if 'gcc' isn't
@@ -122,7 +122,7 @@
doxy: doxygen
doxygen:
- $(Q)$(DOXYGEN) util/doxygen/Doxyfile.LinuxBIOS
+ $(Q)$(DOXYGEN) util/doxygen/Doxyfile.coreboot
prepare:
$(Q)mkdir -p $(obj)
@@ -133,17 +133,17 @@
$(Q)printf " CP $(subst $(shell pwd)/,,$(obj)/config.h)\n"
$(Q)cp $(src)/.tmpconfig.h $(obj)/config.h
$(Q)printf " GEN $(subst $(shell pwd)/,,$(obj)/build.h)\n"
- $(Q)printf "#define LINUXBIOS_VERSION \"$(KERNELVERSION)\"\n" > $(obj)/build.h
- $(Q)printf "#define LINUXBIOS_EXTRA_VERSION \"$(LINUXBIOS_EXTRA_VERSION)\"\n" >> $(obj)/build.h
- $(Q)printf "#define LINUXBIOS_BUILD \"`LANG= date`\"\n" >> $(obj)/build.h
+ $(Q)printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" > $(obj)/build.h
+ $(Q)printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.h
+ $(Q)printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.h
$(Q)printf "\n" >> $(obj)/build.h
- $(Q)printf "#define LINUXBIOS_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.h
- $(Q)printf "#define LINUXBIOS_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.h
- $(Q)printf "#define LINUXBIOS_LINKER \"$(shell LANG= $(LD) --version | head -n1)\"\n" >> $(obj)/build.h
- $(Q)printf "#define LINUXBIOS_COMPILE_TIME \"`LANG= date +%T`\"\n" >> $(obj)/build.h
- $(Q)printf "#define LINUXBIOS_COMPILE_BY \"$(shell PATH=$$PATH:/usr/ucb whoami)\"\n" >> $(obj)/build.h
- $(Q)printf "#define LINUXBIOS_COMPILE_HOST \"$(shell hostname)\"\n" >> $(obj)/build.h
- $(Q)printf "#define LINUXBIOS_COMPILE_DOMAIN \"$(shell test `uname -s` = "Linux" && dnsdomainname || domainname)\"\n" >> $(obj)/build.h
+ $(Q)printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.h
+ $(Q)printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.h
+ $(Q)printf "#define COREBOOT_LINKER \"$(shell LANG= $(LD) --version | head -n1)\"\n" >> $(obj)/build.h
+ $(Q)printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> $(obj)/build.h
+ $(Q)printf "#define COREBOOT_COMPILE_BY \"$(shell PATH=$$PATH:/usr/ucb whoami)\"\n" >> $(obj)/build.h
+ $(Q)printf "#define COREBOOT_COMPILE_HOST \"$(shell hostname)\"\n" >> $(obj)/build.h
+ $(Q)printf "#define COREBOOT_COMPILE_DOMAIN \"$(shell test `uname -s` = "Linux" && dnsdomainname || domainname)\"\n" >> $(obj)/build.h
clean:
$(Q)printf " CLEAN $(subst $(shell pwd)/,,$(obj))\n"
Modified: coreboot-v3/README
===================================================================
--- coreboot-v3/README 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/README 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,8 +1,8 @@
-------------------------------------------------------------------------------
-LinuxBIOS README
+coreboot README
-------------------------------------------------------------------------------
-LinuxBIOS is a Free Software project aimed at replacing the proprietary
+Coreboot is a Free Software project aimed at replacing the proprietary
BIOS you can find in most of today's computers.
It performs just a little bit of hardware initialization and then executes
@@ -13,7 +13,7 @@
--------
After the basic initialization of the hardware has been performed, any
-desired "payload" can be started by LinuxBIOS. Examples include:
+desired "payload" can be started by coreboot. Examples include:
* A Linux kernel
* FILO (a simple bootloader with filesystem support)
@@ -31,12 +31,12 @@
Supported Hardware
------------------
-LinuxBIOS supports a wide range of chipsets, devices, and mainboards.
+Coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
- * http://www.linuxbios.org/Supported_Motherboards
- * http://www.linuxbios.org/Supported_Chipsets_and_Devices
+ * http://www.coreboot.org/Supported_Motherboards
+ * http://www.coreboot.org/Supported_Chipsets_and_Devices
Build Requirements
@@ -57,7 +57,7 @@
Building And Installing
-----------------------
-Note: Currently only the x86 QEMU target is supported in LinuxBIOSv3.
+Note: Currently only the x86 QEMU target is supported in coreboot-v3.
1) Build a payload:
@@ -70,29 +70,29 @@
variety of payloads. The result of this step is usually a file
called 'payload.elf' in the top-level directory.
-2) Configure LinuxBIOS:
+2) Configure coreboot:
$ make menuconfig
Select at least the desired mainboard vendor, the mainboard device, and
- the size of your ROM chip. Per default LinuxBIOS will look for a file
+ the size of your ROM chip. Per default coreboot will look for a file
called 'payload.elf' in the current directory and use that as the payload.
If that's not what you want, you can change the path/filename of the
payload to use some other payload file. Or you can choose 'No payload'
- in the configuration menu, in which case the resulting LinuxBIOS ROM image
+ in the configuration menu, in which case the resulting coreboot ROM image
will not contain any payload. You'll have to manually add a payload
- later using the 'lar' utility for the LinuxBIOS ROM image to be useful.
+ later using the 'lar' utility for the coreboot ROM image to be useful.
-3) Build the LinuxBIOS ROM image:
+3) Build the coreboot ROM image:
$ make
- The generated ROM image is the file linuxbios.rom in the build/ directory.
+ The generated ROM image is the file coreboot.rom in the build/ directory.
-4) Flash the LinuxBIOS ROM image on a BIOS chip:
+4) Flash the coreboot ROM image on a BIOS chip:
- $ flashrom -wv linuxbios.rom
+ $ flashrom -wv coreboot.rom
NOTE: This step will OVERWRITE the current BIOS located on the ROM chip!
Make sure you have adequate backup facilities before performing this
@@ -106,12 +106,12 @@
the flashrom package via 'apt-get install flashrom'.
-Testing LinuxBIOS Without Modifying Your Hardware
+Testing coreboot Without Modifying Your Hardware
-------------------------------------------------
-If you want to test LinuxBIOS without any risks before you really decide
+If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
-LinuxBIOS virtually in QEMU.
+coreboot virtually in QEMU.
The required steps are:
@@ -124,14 +124,14 @@
$ qemu -L build -hda /dev/zero -serial stdio
- This will run LinuxBIOS in QEMU and output all debugging messages (which
+ This will run coreboot in QEMU and output all debugging messages (which
are usually emitted to a serial console) on stdout. It will not do
anything useful beyond that, as you provided no virtual harddrive to
QEMU (-hda /dev/zero).
If you have a full QEMU hard drive image (say /tmp/qemu.img) with a Linux
distribution installed, you can boot that Linux kernel by using a proper
- FILO payload with LinuxBIOS and typing:
+ FILO payload with coreboot and typing:
$ qemu -L build -hda /tmp/qemu.img -serial stdio
@@ -143,26 +143,26 @@
------------------------
Further details on the project, a FAQ, many HOWTOs, news, development
-guidelines and more can be found on the LinuxBIOS website:
+guidelines and more can be found on the coreboot website:
- http://www.linuxbios.org
+ http://www.coreboot.org
-You can contact us directly on the LinuxBIOS mailing list:
+You can contact us directly on the coreboot mailing list:
- http://www.linuxbios.org/Mailinglist
+ http://www.coreboot.org/Mailinglist
Copyright and License
---------------------
-The copyright on LinuxBIOS is owned by quite a large number of individual
+The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.
-LinuxBIOS is licensed under the terms of the GNU General Public License (GPL).
+Coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts,
which were derived from other Free Software projects, other (GPL-compatible)
licenses may apply. Please check the individual source files for details.
-This makes the resulting LinuxBIOS images licensed under the GPL, version 2.
+This makes the resulting coreboot images licensed under the GPL, version 2.
Modified: coreboot-v3/Rules.make
===================================================================
--- coreboot-v3/Rules.make 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/Rules.make 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2006-2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
@@ -25,7 +25,7 @@
$(obj)/mainboard/$(MAINBOARDDIR)/statictree.o: $(obj)/mainboard/$(MAINBOARDDIR)/statictree.c $(obj)/statictree.h
$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
- $(Q)$(CC) $(INITCFLAGS) $(LINUXBIOSINCLUDE) -c -o $@ $<
+ $(Q)$(CC) $(INITCFLAGS) $(COREBOOTINCLUDE) -c -o $@ $<
$(obj)/mainboard/$(MAINBOARDDIR)/statictree.c: $(src)/mainboard/$(MAINBOARDDIR)/dts $(obj)/util/dtc/dtc
$(Q)printf " DTC $(subst $(shell pwd)/,,$(@))\n"
Modified: coreboot-v3/arch/x86/Kconfig
===================================================================
--- coreboot-v3/arch/x86/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2006-2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
@@ -59,7 +59,7 @@
boolean
help
This option is used to enable certain functions to make
- LinuxBIOS work correctly on symmetric multi processor
+ coreboot work correctly on symmetric multi processor
systems.
It is usually set in mainboard/*/Kconfig.
Modified: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3/arch/x86/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2006-2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
@@ -29,12 +29,12 @@
#
# Build the ROM Image / LAR archive
#
-# LinuxBIOS v3 is completely modular. One module, the bootblock (stage0),
+# coreboot v3 is completely modular. One module, the bootblock (stage0),
# is mandatory. All modules are packed together in a LAR archive.
# The LAR archive may contain any number of stages, payloads and option ROMs.
#
-ROM_SIZE := $(shell expr $(CONFIG_LINUXBIOS_ROMSIZE_KB) \* 1024)
+ROM_SIZE := $(shell expr $(CONFIG_COREBOOT_ROMSIZE_KB) \* 1024)
LARFILES := nocompress:normal/initram normal/stage2 nocompress:normal/option_table
ifneq ($(CONFIG_PAYLOAD_NONE),y)
@@ -57,12 +57,12 @@
COMPRESSFLAG := -C nrv2b
endif
-$(obj)/linuxbios.rom $(obj)/linuxbios.map: $(obj)/linuxbios.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/linuxbios.initram $(obj)/linuxbios.stage2 $(obj)/option_table
+$(obj)/coreboot.rom $(obj)/coreboot.map: $(obj)/coreboot.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/coreboot.initram $(obj)/coreboot.stage2 $(obj)/option_table
$(Q)rm -rf $(obj)/lar.tmp
$(Q)mkdir $(obj)/lar.tmp
$(Q)mkdir $(obj)/lar.tmp/normal
- $(Q)cp $(obj)/linuxbios.initram $(obj)/lar.tmp/normal/initram
- $(Q)cp $(obj)/linuxbios.stage2 $(obj)/lar.tmp/normal/stage2
+ $(Q)cp $(obj)/coreboot.initram $(obj)/lar.tmp/normal/initram
+ $(Q)cp $(obj)/coreboot.stage2 $(obj)/lar.tmp/normal/stage2
$(Q)cp $(obj)/option_table $(obj)/lar.tmp/normal/option_table
ifeq ($(CONFIG_PAYLOAD_NONE),y)
$(Q)printf " PAYLOAD none (as specified by user)\n"
@@ -77,31 +77,31 @@
fi
endif
$(Q)printf " LAR $(subst $(shell pwd)/,,$(@))\n"
- $(Q)rm -f $(obj)/linuxbios.rom
+ $(Q)rm -f $(obj)/coreboot.rom
$(Q)cd $(obj)/lar.tmp && ../util/lar/lar $(PARSEELF) $(COMPRESSFLAG) -c \
- ../linuxbios.rom \
+ ../coreboot.rom \
$(LARFILES) \
- -s $(ROM_SIZE) -b $(obj)/linuxbios.bootblock
+ -s $(ROM_SIZE) -b $(obj)/coreboot.bootblock
$(Q)# QEMU wants bios.bin:
$(Q)# Run "qemu -L build/ -serial stdio -hda /dev/zero".
$(Q)printf " CP $(subst $(shell pwd)/,,$(obj)/bios.bin)\n"
$(Q)cp $@ $(obj)/bios.bin
- $(Q)echo "LinuxBIOS ROM Image:" > $(obj)/linuxbios.map
- $(Q)$(obj)/util/lar/lar -l $(obj)/linuxbios.rom >> $(obj)/linuxbios.map
- $(Q)(echo; echo "Stage 0/1 Map:") >> $(obj)/linuxbios.map
- $(Q)cat $(obj)/stage0.init.map >> $(obj)/linuxbios.map
- $(Q)(echo; echo "Stage Initram Map:") >> $(obj)/linuxbios.map
- $(Q)cat $(obj)/linuxbios.initram.map >> $(obj)/linuxbios.map
- $(Q)(echo; echo "Stage 2 Map:") >> $(obj)/linuxbios.map
- $(Q)cat $(obj)/linuxbios.stage2.map >> $(obj)/linuxbios.map
+ $(Q)echo "Coreboot ROM Image:" > $(obj)/coreboot.map
+ $(Q)$(obj)/util/lar/lar -l $(obj)/coreboot.rom >> $(obj)/coreboot.map
+ $(Q)(echo; echo "Stage 0/1 Map:") >> $(obj)/coreboot.map
+ $(Q)cat $(obj)/stage0.init.map >> $(obj)/coreboot.map
+ $(Q)(echo; echo "Stage Initram Map:") >> $(obj)/coreboot.map
+ $(Q)cat $(obj)/coreboot.initram.map >> $(obj)/coreboot.map
+ $(Q)(echo; echo "Stage 2 Map:") >> $(obj)/coreboot.map
+ $(Q)cat $(obj)/coreboot.stage2.map >> $(obj)/coreboot.map
-$(obj)/linuxbios.bootblock: $(obj)/linuxbios.vpd $(obj)/stage0.init
+$(obj)/coreboot.bootblock: $(obj)/coreboot.vpd $(obj)/stage0.init
$(Q)printf " BUILD $(subst $(shell pwd)/,,$(@))\n"
$(Q)cat $^ > $@
#
-# LinuxBIOS stage0. This is the LinuxBIOS "boot block code".
+# Coreboot stage0. This is the coreboot "boot block code".
# It enables Cache-as-RAM and parses the LAR archive for an
# initram module and the various stages and payload files.
#
@@ -164,7 +164,7 @@
#
-# This is the rest of LinuxBIOS (v2: linuxbios_ram.rom).
+# This is the rest of coreboot (v2: coreboot_ram.rom).
# Is this maybe platform independent, except for the "drivers"?
# Where should it be built, maybe in device/?
#
@@ -174,7 +174,7 @@
STAGE2_LIB_OBJ = stage2.o clog2.o mem.o tables.o delay.o \
compute_ip_checksum.o string.o
-STAGE2_ARCH_X86_OBJ = archtables.o linuxbios_table.o udelay_io.o
+STAGE2_ARCH_X86_OBJ = archtables.o coreboot_table.o udelay_io.o
STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o
STAGE2_ARCH_X86_OBJ += keyboard.o i8259.o isa-dma.o
@@ -203,12 +203,12 @@
STAGE2_OBJ_NEEDED = $(filter-out $(STAGE0_OBJ), $(STAGE2_OBJ))
-$(obj)/linuxbios.stage2 $(obj)/linuxbios.stage2.map: $(obj)/stage0.init $(STAGE2_OBJ_NEEDED)
+$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.init $(STAGE2_OBJ_NEEDED)
$(Q)# leave a .o with full symbols in it for debugging.
$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x1000 --entry=stage2 \
- -o $(obj)/linuxbios.stage2 $(STAGE2_OBJ_NEEDED)
- $(Q)$(NM) $(obj)/linuxbios.stage2 | sort -u > $(obj)/linuxbios.stage2.map
+ -o $(obj)/coreboot.stage2 $(STAGE2_OBJ_NEEDED)
+ $(Q)$(NM) $(obj)/coreboot.stage2 | sort -u > $(obj)/coreboot.stage2.map
#
# Build rules.
@@ -222,7 +222,7 @@
# Building asm stub.
$(obj)/arch/x86/stage0%.o: $(src)/arch/x86/stage0%.S
$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
- $(Q)$(CC) -E $(LINUXBIOSINCLUDE) $< \
+ $(Q)$(CC) -E $(COREBOOTINCLUDE) $< \
-o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \
-DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
$(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n"
@@ -231,20 +231,20 @@
$(obj)/arch/x86/geodelx/stage0.o: $(src)/arch/x86/geodelx/stage0.S
$(Q)mkdir -p $(dir $@)
$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
- $(Q)$(CC) -E $(LINUXBIOSINCLUDE) $< \
+ $(Q)$(CC) -E $(COREBOOTINCLUDE) $< \
-o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \
-DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
$(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
-$(obj)/linuxbios.initram $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ)
+$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ)
$(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n"
- $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/linuxbios.initram_partiallylinked.o
+ $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/coreboot.initram_partiallylinked.o
$(Q)# initram links against stage0
$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \
- $(obj)/linuxbios.initram_partiallylinked.o -o $(obj)/linuxbios.initram
+ $(obj)/coreboot.initram_partiallylinked.o -o $(obj)/coreboot.initram
$(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n"
- $(Q)$(NM) $(obj)/linuxbios.initram | sort -u > $(obj)/linuxbios.initram.map
+ $(Q)$(NM) $(obj)/coreboot.initram | sort -u > $(obj)/coreboot.initram.map
endif
Modified: coreboot-v3/arch/x86/archtables.c
===================================================================
--- coreboot-v3/arch/x86/archtables.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/archtables.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,7 +1,6 @@
/*
- * table management code for Linux BIOS
+ * table management code for coreboot
*
- *
* Copyright (C) 2002 Eric Biederman, Linux NetworX
*
* This program is free software; you can redistribute it and/or modify
@@ -45,7 +44,7 @@
#if 0
// Copy GDT to new location and reload it
// 2003-07 by SONE Takeshi
-// Ported from Etherboot to LinuxBIOS 2005-08 by Steve Magnani
+// Ported from Etherboot to coreboot 2005-08 by Steve Magnani
void move_gdt(unsigned long newgdt)
{
u16 num_gdt_bytes = &gdt_end - &gdt;
@@ -85,7 +84,7 @@
/* Write ACPI tables */
/* write them in the rom area because DSDT can be large (8K on epia-m) which
- * pushes linuxbios table out of first 4K if set up in low table area
+ * pushes coreboot table out of first 4K if set up in low table area
*/
// rom_table_end = write_acpi_tables(rom_table_end);
@@ -136,8 +135,8 @@
move_gdt(low_table_end);
low_table_end += &gdt_end - &gdt;
#endif
- /* The linuxbios table must be in 0-4K or 960K-1M */
- write_linuxbios_table(
+ /* The coreboot table must be in 0-4K or 960K-1M */
+ write_coreboot_table(
low_table_start, low_table_end,
rom_table_start, rom_table_end);
Modified: coreboot-v3/arch/x86/geodelx/cpu.c
===================================================================
--- coreboot-v3/arch/x86/geodelx/cpu.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/geodelx/cpu.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2006 Indrek Kruusa <indrek.kruusa at artecdesign.ee>
* Copyright (C) 2006 Ronald G. Minnich <rminnich at gmail.com>
Modified: coreboot-v3/arch/x86/geodelx/geodelx.c
===================================================================
--- coreboot-v3/arch/x86/geodelx/geodelx.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/geodelx/geodelx.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2006 Indrek Kruusa <indrek.kruusa at artecdesign.ee>
* Copyright (C) 2006 Ronald G. Minnich <rminnich at gmail.com>
Modified: coreboot-v3/arch/x86/geodelx/stage0.S
===================================================================
--- coreboot-v3/arch/x86/geodelx/stage0.S 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/geodelx/stage0.S 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
* Copyright (C) 2005 Eswar Nallusamy, LANL
@@ -170,7 +170,7 @@
.align 4
/* Here begins CAR support. */
- /* This particular code is straight from LinuxBIOS v2. */
+ /* This particular code is straight from coreboot v2. */
/* DCacheSetup: Setup data cache for use as RAM for a stack. */
DCacheSetup:
Modified: coreboot-v3/arch/x86/geodelx/stage1.c
===================================================================
--- coreboot-v3/arch/x86/geodelx/stage1.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/geodelx/stage1.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/arch/x86/i8259.c
===================================================================
--- coreboot-v3/arch/x86/i8259.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/i8259.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* It is based on the arch/i386/boot/setup.S file from the Linux kernel.
*/
Modified: coreboot-v3/arch/x86/ldscript.ld
===================================================================
--- coreboot-v3/arch/x86/ldscript.ld 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/ldscript.ld 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ron G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/arch/x86/linuxbios_table.c
===================================================================
--- coreboot-v3/arch/x86/linuxbios_table.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/linuxbios_table.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * table management code for Linux BIOS tables
+ * table management code for coreboot tables
*
* Copyright (C) 2002 Eric Biederman, Linux NetworX
* Copyright (C) 2007 coresystems GmbH
@@ -133,9 +133,9 @@
cmos_checksum->size = (sizeof(*cmos_checksum));
- cmos_checksum->range_start = LB_CKS_RANGE_START * 8;
- cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7;
- cmos_checksum->location = LB_CKS_LOC * 8;
+ cmos_checksum->range_start = CB_CKS_RANGE_START * 8;
+ cmos_checksum->range_end = ( CB_CKS_RANGE_END * 8 ) + 7;
+ cmos_checksum->location = CB_CKS_LOC * 8;
cmos_checksum->type = CHECKSUM_PCBIOS;
@@ -148,16 +148,16 @@
u32 tag;
const u8 *string;
} strings[] = {
- { LB_TAG_VERSION, (const u8 *)LINUXBIOS_VERSION },
- { LB_TAG_EXTRA_VERSION, (const u8 *)LINUXBIOS_EXTRA_VERSION },
- { LB_TAG_BUILD, (const u8 *)LINUXBIOS_BUILD },
- { LB_TAG_COMPILE_TIME, (const u8 *)LINUXBIOS_COMPILE_TIME }, // duplicate?
- { LB_TAG_COMPILE_BY, (const u8 *)LINUXBIOS_COMPILE_BY },
- { LB_TAG_COMPILE_HOST, (const u8 *)LINUXBIOS_COMPILE_HOST },
- { LB_TAG_COMPILE_DOMAIN, (const u8 *)LINUXBIOS_COMPILE_DOMAIN },
- { LB_TAG_COMPILER, (const u8 *)LINUXBIOS_COMPILER },
- { LB_TAG_LINKER, (const u8 *)LINUXBIOS_LINKER },
- { LB_TAG_ASSEMBLER, (const u8 *)LINUXBIOS_ASSEMBLER },
+ { LB_TAG_VERSION, (const u8 *)COREBOOT_VERSION },
+ { LB_TAG_EXTRA_VERSION, (const u8 *)COREBOOT_EXTRA_VERSION },
+ { LB_TAG_BUILD, (const u8 *)COREBOOT_BUILD },
+ { LB_TAG_COMPILE_TIME, (const u8 *)COREBOOT_COMPILE_TIME }, // duplicate?
+ { LB_TAG_COMPILE_BY, (const u8 *)COREBOOT_COMPILE_BY },
+ { LB_TAG_COMPILE_HOST, (const u8 *)COREBOOT_COMPILE_HOST },
+ { LB_TAG_COMPILE_DOMAIN, (const u8 *)COREBOOT_COMPILE_DOMAIN },
+ { LB_TAG_COMPILER, (const u8 *)COREBOOT_COMPILER },
+ { LB_TAG_LINKER, (const u8 *)COREBOOT_LINKER },
+ { LB_TAG_ASSEMBLER, (const u8 *)COREBOOT_ASSEMBLER },
};
unsigned int i;
for(i = 0; i < ARRAY_SIZE(strings); i++) {
@@ -231,7 +231,7 @@
head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
head->header_checksum = 0;
head->header_checksum = compute_ip_checksum(head, sizeof(*head));
- printk(BIOS_DEBUG,"Wrote LinuxBIOS table at: %p - %p checksum %x\n",
+ printk(BIOS_DEBUG,"Wrote coreboot table at: %p - %p checksum %x\n",
head, rec, head->table_checksum);
return (unsigned long)rec;
}
@@ -352,8 +352,8 @@
lb_cleanup_memory_ranges(mem);
}
-/* Routines to extract part so the linuxBIOS table or
- * information from the linuxBIOS table after we have written it.
+/* Routines to extract part so the coreboot table or
+ * information from the coreboot table after we have written it.
* Currently get_lb_mem relies on a global we can change the
* implementaiton.
*/
@@ -386,7 +386,7 @@
}
/**
- * Add pointer to device tree to LinuxBIOS table.
+ * Add pointer to device tree to coreboot table.
*
* @param head Pointer to lbtable header.
* @return TODO
@@ -405,7 +405,7 @@
return lbdev;
}
-unsigned long write_linuxbios_table(
+unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end)
{
@@ -429,7 +429,7 @@
rec_dest = lb_new_record(head);
memcpy(rec_dest, rec_src, rec_src->size);
- /* Create cmos checksum entry in linuxbios table */
+ /* Create cmos checksum entry in coreboot table */
lb_cmos_checksum(head);
}
@@ -446,9 +446,9 @@
/* Note:
* I assume that there is always memory at immediately after
- * the low_table_end. This means that after I setup the linuxbios table.
+ * the low_table_end. This means that after I setup the coreboot table.
* I can trivially fixup the reserved memory ranges to hold the correct
- * size of the linuxbios table.
+ * size of the coreboot table.
*/
/* Record our motherboard */
@@ -457,7 +457,7 @@
/* Record our various random string information */
lb_strings(head);
- /* Record a pointer to the LinuxBIOS device tree */
+ /* Record a pointer to the coreboot device tree */
lb_devtree(head);
/* Remember where my valid memory ranges are */
Modified: coreboot-v3/arch/x86/macros.h
===================================================================
--- coreboot-v3/arch/x86/macros.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/macros.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2000 Ron G. Minnich <rminnich at lanl.gov>
* Copyright (C) 2007 Stefan Reinauer <stepan at coresystems.de>
Modified: coreboot-v3/arch/x86/mc146818rtc.c
===================================================================
--- coreboot-v3/arch/x86/mc146818rtc.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/mc146818rtc.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -128,11 +128,11 @@
CMOS_WRITE(RTC_FREQ_SELECT_DEFAULT, RTC_FREQ_SELECT);
#if defined(CONFIG_OPTION_TABLE) && (CONFIG_OPTION_TABLE == 1)
- /* See if there is a LB CMOS checksum error */
- checksum_invalid = !rtc_checksum_valid(LB_CKS_RANGE_START,
- LB_CKS_RANGE_END,LB_CKS_LOC);
+ /* See if there is a coreboot CMOS checksum error */
+ checksum_invalid = !rtc_checksum_valid(CB_CKS_RANGE_START,
+ CB_CKS_RANGE_END,CB_CKS_LOC);
if(checksum_invalid)
- printk(BIOS_WARNING, "Invalid LinuxBIOS CMOS checksum.\n");
+ printk(BIOS_WARNING, "Invalid coreboot CMOS checksum.\n");
/* Make certain we have a valid checksum */
rtc_set_checksum(PC_CKS_RANGE_START,
@@ -184,8 +184,8 @@
int ret;
// FIXME - i want to be dynamic.
- archive.len=(CONFIG_LINUXBIOS_ROMSIZE_KB-16)*1024;
- archive.start=(void *)(0UL-(CONFIG_LINUXBIOS_ROMSIZE_KB*1024));
+ archive.len=(CONFIG_COREBOOT_ROMSIZE_KB-16)*1024;
+ archive.start=(void *)(0UL-(CONFIG_COREBOOT_ROMSIZE_KB*1024));
ret = find_file(&archive, "normal/option_table", &result);
if (ret) {
@@ -223,8 +223,8 @@
if(get_cmos_value(ce->bit, ce->length, dest))
return(-3);
- if(!rtc_checksum_valid(LB_CKS_RANGE_START,
- LB_CKS_RANGE_END,LB_CKS_LOC))
+ if(!rtc_checksum_valid(CB_CKS_RANGE_START,
+ CB_CKS_RANGE_END,CB_CKS_LOC))
return(-4);
#if defined(CONFIG_OPTION_TABLE) && (CONFIG_OPTION_TABLE == 1)
return(0);
@@ -255,14 +255,14 @@
u32 sum, old_sum;
sum = 0;
/* Comput the cmos checksum */
- for(addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
+ for(addr = CB_CKS_RANGE_START; addr <= CB_CKS_RANGE_END; addr++) {
sum += CMOS_READ(addr);
}
sum = (sum & 0xffff) ^ 0xffff;
/* Read the stored checksum */
- old_sum = CMOS_READ(LB_CKS_LOC) << 8;
- old_sum |= CMOS_READ(LB_CKS_LOC+1);
+ old_sum = CMOS_READ(CB_CKS_LOC) << 8;
+ old_sum |= CMOS_READ(CB_CKS_LOC+1);
return sum == old_sum;
}
Modified: coreboot-v3/arch/x86/post_code.c
===================================================================
--- coreboot-v3/arch/x86/post_code.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/post_code.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Stefan Reinauer <stepan at coresystems.de>
*
Modified: coreboot-v3/arch/x86/serial.c
===================================================================
--- coreboot-v3/arch/x86/serial.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/serial.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 coresystems GmbH
* (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/arch/x86/speaker.c
===================================================================
--- coreboot-v3/arch/x86/speaker.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/speaker.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
*
Modified: coreboot-v3/arch/x86/stage0_i586.S
===================================================================
--- coreboot-v3/arch/x86/stage0_i586.S 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/stage0_i586.S 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
## Copyright (C) 2005 Eswar Nallusamy, LANL
Modified: coreboot-v3/arch/x86/stage1.c
===================================================================
--- coreboot-v3/arch/x86/stage1.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/stage1.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Stefan Reinauer <stepan at coresystems.de>
* Copyright (C) 2007 Advanced Micro Devices, Inc.
@@ -182,7 +182,7 @@
else
die("FATAL: No usable payload found.\n");
- die ("FATAL: Last stage returned to LinuxBIOS.\n");
+ die ("FATAL: Last stage returned to coreboot.\n");
}
Modified: coreboot-v3/arch/x86/udelay_io.c
===================================================================
--- coreboot-v3/arch/x86/udelay_io.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/arch/x86/udelay_io.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2005 coresystems GmbH
* (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/device/Kconfig
===================================================================
--- coreboot-v3/device/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/device/Makefile
===================================================================
--- coreboot-v3/device/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/device/agp_device.c
===================================================================
--- coreboot-v3/device/agp_device.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/agp_device.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2005 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
Modified: coreboot-v3/device/cardbus_device.c
===================================================================
--- coreboot-v3/device/cardbus_device.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/cardbus_device.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2005 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
Modified: coreboot-v3/device/device.c
===================================================================
--- coreboot-v3/device/device.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/device.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* It was originally based on the Linux kernel (arch/i386/kernel/pci-pc.c).
*
Modified: coreboot-v3/device/device_util.c
===================================================================
--- coreboot-v3/device/device_util.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/device_util.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2003-2004 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
Modified: coreboot-v3/device/hypertransport.c
===================================================================
--- coreboot-v3/device/hypertransport.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/hypertransport.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2003-2004 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
@@ -576,7 +576,7 @@
/* Die if any leftover static devices are found.
* There's probably a problem in the Config.lb.
- * TODO: No more Config.lb in LinuxBIOSv3.
+ * TODO: No more Config.lb in coreboot-v3.
*/
if (old_devices) {
struct device *left;
Modified: coreboot-v3/device/pci_device.c
===================================================================
--- coreboot-v3/device/pci_device.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/pci_device.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* It was originally based on the Linux kernel (drivers/pci/pci.c).
*
@@ -272,7 +272,7 @@
if ((dev->on_mainboard) && (dev->rom_address == 0)) {
// Skip it if rom_address is not set in MB Config.lb.
- // TODO: No more Config.lb in LinuxBIOSv3.
+ // TODO: No more Config.lb in coreboot-v3.
return;
}
@@ -320,7 +320,7 @@
/* For on board device with embedded ROM image, the ROM image is at
* fixed address specified in the Config.lb, the dev->rom_address is
* inited by driver_pci_onboard_ops::enable_dev() */
- /* TODO: No more Config.lb in LinuxBIOSv3. */
+ /* TODO: No more Config.lb in coreboot-v3. */
if ((dev->on_mainboard) && (dev->rom_address != 0)) {
resource->base = dev->rom_address;
resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY |
@@ -1131,7 +1131,7 @@
/* Die if any leftover static devices are are found.
* There's probably a problem in the Config.lb.
- * TODO: No more Config.lb in LinuxBIOSv3.
+ * TODO: No more Config.lb in coreboot-v3.
*/
if (old_devices) {
struct device *left;
Modified: coreboot-v3/device/pci_ops.c
===================================================================
--- coreboot-v3/device/pci_ops.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/pci_ops.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2004 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
Modified: coreboot-v3/device/pci_rom.c
===================================================================
--- coreboot-v3/device/pci_rom.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/pci_rom.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2005 Li-Ta Lo <ollie at lanl.gov>
* Copyright (C) 2005 Tyan
Modified: coreboot-v3/device/pcie_device.c
===================================================================
--- coreboot-v3/device/pcie_device.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/pcie_device.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2005 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
Modified: coreboot-v3/device/pcix_device.c
===================================================================
--- coreboot-v3/device/pcix_device.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/pcix_device.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2005 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
Modified: coreboot-v3/device/pnp_device.c
===================================================================
--- coreboot-v3/device/pnp_device.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/pnp_device.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2004 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
Modified: coreboot-v3/device/pnp_raw.c
===================================================================
--- coreboot-v3/device/pnp_raw.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/pnp_raw.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
* Copyright (C) 2007 coresystems GmbH
Modified: coreboot-v3/device/root_device.c
===================================================================
--- coreboot-v3/device/root_device.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/root_device.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2003-2004 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
Modified: coreboot-v3/device/smbus_ops.c
===================================================================
--- coreboot-v3/device/smbus_ops.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/device/smbus_ops.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan
* (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
Modified: coreboot-v3/doc/design/flashlayout.fig
===================================================================
--- coreboot-v3/doc/design/flashlayout.fig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/doc/design/flashlayout.fig 2008-01-27 18:54:57 UTC (rev 564)
@@ -31,9 +31,9 @@
4 0 0 50 -1 0 12 0.0000 4 135 360 3375 900 lzma\001
4 0 0 50 -1 0 12 0.0000 4 135 420 3375 1125 nrv2b\001
4 0 0 50 -1 0 12 0.0000 4 135 1080 3375 1350 normal/initram\001
-4 0 0 50 -1 0 12 0.0000 4 135 1635 3375 1575 normal/linuxbios.lzma\001
+4 0 0 50 -1 0 12 0.0000 4 135 1635 3375 1575 normal/coreboot.lzma\001
4 0 0 50 -1 0 12 0.0000 4 135 1170 3375 1800 fallback/initram\001
-4 0 0 50 -1 0 12 0.0000 4 135 1725 3375 2025 fallback/linuxbios.lzma\001
+4 0 0 50 -1 0 12 0.0000 4 135 1725 3375 2025 fallback/coreboot.lzma\001
4 0 0 50 -1 0 12 0.0000 4 135 2130 3375 2250 memtest86/memtest86.lzma\001
4 0 0 50 -1 0 12 0.0000 4 180 990 3375 2475 vgabios.lzma\001
4 0 0 50 -1 0 12 0.0000 4 180 1020 2625 4275 Basic startup\001
Modified: coreboot-v3/doc/design/newboot.lyx
===================================================================
--- coreboot-v3/doc/design/newboot.lyx 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/doc/design/newboot.lyx 2008-01-27 18:54:57 UTC (rev 564)
@@ -30,13 +30,13 @@
\begin_body
\begin_layout Title
-LinuxBIOS boot structure
+coreboot boot structure
\newline
LA-UR-06-7928
\end_layout
\begin_layout Author
-New LinuxBIOS group
+New coreboot group
\newline
\end_layout
@@ -58,7 +58,7 @@
\end_layout
\begin_layout Abstract
-This is the new LinuxBIOS boot architecture.
+This is the new coreboot boot architecture.
\end_layout
\begin_layout Section
@@ -84,18 +84,18 @@
\end_layout
\begin_layout Standard
-The new LinuxBIOS boot architecture depends on CAR, with payloads appearing
+The new coreboot boot architecture depends on CAR, with payloads appearing
as files in a LAR archive.
The device tree is defined by a device tree blob (DTB) and all the activities
flow from that.
- For now, the DTC will produce a standard LinuxBIOS v2 device tree; this
+ For now, the DTC will produce a standard coreboot v2 device tree; this
will, we hope, be improved.
romcc is gone.
\end_layout
\begin_layout Standard
-Required attributes of a CPU for LinuxBIOS v3:
+Required attributes of a CPU for coreboot v3:
\end_layout
\begin_layout Itemize
@@ -181,7 +181,7 @@
\end_layout
\begin_layout Itemize
-Traditional LinuxBIOS RAM code (LAR, etc.)
+Traditional coreboot RAM code (LAR, etc.)
\end_layout
\begin_layout Itemize
@@ -217,7 +217,7 @@
\end_layout
\begin_layout Section
-Introduction to the LinuxBIOS device tree
+Introduction to the coreboot device tree
\end_layout
\begin_layout Subsection
@@ -225,8 +225,8 @@
\end_layout
\begin_layout Standard
-The LinuxBIOS device tree is probably the single most important concept
- in LinuxBIOS, and, in V2, was the least understood part of the software.
+The coreboot device tree is probably the single most important concept
+ in coreboot, and, in V2, was the least understood part of the software.
The device tree provides a tremendous amount of capability to the software.
The initial tree, which almost always will be an incomplete representation
of the hardware (consider pluggable devices), is created by the configuration
@@ -303,7 +303,7 @@
\end_layout
\begin_layout Standard
-There are three primary objects which are used to manage the LinuxBIOS device
+There are three primary objects which are used to manage the coreboot device
tree: devices, links, and drivers.
Devices and links are generic structures: drivers, on the other hand, are
specialized.
@@ -353,7 +353,7 @@
But, not all devices have identical capabilities.
Some PCI devices have IDE controllers, others do not; some can drive the
legacy PC XBUS, others can not; and so on.
- In LinuxBIOS V1, we attempted to create devices that were the union of
+ In coreboot V1, we attempted to create devices that were the union of
all possible devices, but creating such a union proved to be impossible,
as new devices with new capabilities came out.
So, in V2, we split off the device-specific information into a seperate
@@ -417,7 +417,7 @@
\end_layout
\begin_layout LyX-Code
-[rminnich at q ~]$ ls ~/src/bios/LinuxBIOSv3/northbridge/intel/i440bxemulation/
+[rminnich at q ~]$ ls ~/src/bios/coreboot-v3/northbridge/intel/i440bxemulation/
\end_layout
@@ -1403,7 +1403,7 @@
If the checksum fails, If the test fails, use the backup property in the
option node to find a backup.
initram is (C, PIC) as it must execute in place.
- The LinuxBIOS payload will be uncompressed to RAM, and is in C, but need
+ The coreboot payload will be uncompressed to RAM, and is in C, but need
not be PIC.
\end_layout
@@ -1780,7 +1780,7 @@
\end_layout
\begin_layout Standard
-This is for creating the linuxbios.lzma file.
+This is for creating the coreboot.lzma file.
\end_layout
@@ -1797,7 +1797,7 @@
\end_layout
\begin_layout Subsection
-linuxbios_ram
+coreboot_ram
\end_layout
\begin_layout Standard
@@ -1819,7 +1819,7 @@
\end_layout
\begin_layout Subsection
-linuxbios.lar
+coreboot.lar
\end_layout
\begin_layout Standard
@@ -1831,7 +1831,7 @@
\begin_inset Quotes erd
\end_inset
- that contains the lzma, initram, linuxbios_ram, and payload targets.
+ that contains the lzma, initram, coreboot_ram, and payload targets.
\end_layout
@@ -1913,7 +1913,7 @@
\begin_layout Itemize
Global vs.
local builds - pros/cons with kernel style (global) build (always produces
- arch/x/*Image) and LBv2 style build (produces target/x/y/z/linuxbios.rom
+ arch/x/*Image) and coreboot v2 style build (produces target/x/y/z/coreboot.rom
for each target) Either way the config/build system must be consistently
either global or local.
\end_layout
@@ -1946,15 +1946,15 @@
\begin_layout Itemize
Payload.
- I say something must be included in the LB tree or trivially added to a
+ I say something must be included in the coreboot tree or trivially added to a
tree by download or command.
FILO is candidate for inclusion.
- What's up with FILO(EB) and FILO(LB) ? Merge them? Make EB default payload?
+ What's up with FILO(EB) and FILO(CB) ? Merge them? Make EB default payload?
FILO? memtest86? All about making a usable product.
memtest86 would have to be explicitly selected in expert mode in favor
of the default option that would be able to load an OS.
Doesn't matter much if it's only Linux right now because that's the most
- likely boot candidate for early LB adopters.
+ likely boot candidate for early CB adopters.
\end_layout
\begin_layout Itemize
@@ -2118,11 +2118,11 @@
\begin_layout Standard
Next we bring in the initram.c from v2.
- This is LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c.
+ This is coreboot-v2/src/mainboard/amd/norwich/cache_as_ram_auto.c.
It will not build in V3, as the includes are wrong.
We fix these and, while we are at it, change the entry point to be called
main().
- This file will be a standalone file in the LinuxBIOS Archive (LAR), and
+ This file will be a standalone file in the coreboot Lightweight Archive (LAR), and
hence needs to have main() as the entry point.
\end_layout
@@ -2138,43 +2138,43 @@
\begin_layout LyX-Code
\size tiny
-/home/rminnich/src/bios/LinuxBIOSv3/mainboard/amd/norwich/initram.c: In function
- 'spd_read_byte': /home/rminnich/src/bios/LinuxBIOSv3/mainboard/amd/norwich/init
+/home/rminnich/src/bios/coreboot-v3/mainboard/amd/norwich/initram.c: In function
+ 'spd_read_byte': /home/rminnich/src/bios/coreboot-v3/mainboard/amd/norwich/init
ram.c:30: error: implicit declaration of function 'smbus_read_byte' /home/rminnic
-h/src/bios/LinuxBIOSv3/mainboard/amd/norwich/initram.c: In function 'msr_init':
- /home/rminnich/src/bios/LinuxBIOSv3/mainboard/amd/norwich/initram.c:41:
+h/src/bios/coreboot-v3/mainboard/amd/norwich/initram.c: In function 'msr_init':
+ /home/rminnich/src/bios/coreboot-v3/mainboard/amd/norwich/initram.c:41:
error: 'msr_t' undeclared (first use in this function) /home/rminnich/src/bios/
-LinuxBIOSv3/mainboard/amd/norwich/initram.c:41: error: (Each undeclared identifie
-r is reported only once /home/rminnich/src/bios/LinuxBIOSv3/mainboard/amd/norwic
-h/initram.c:41: error: for each function it appears in.) /home/rminnich/src/bios/L
-inuxBIOSv3/mainboard/amd/norwich/initram.c:41: error: expected ';' before
- 'msr' /home/rminnich/src/bios/LinuxBIOSv3/mainboard/amd/norwich/initram.c:43:
- error: 'msr' undeclared (first use in this function) /home/rminnich/src/bios/Li
-nuxBIOSv3/mainboard/amd/norwich/initram.c:45: error: implicit declaration
- of function 'wrmsr' /home/rminnich/src/bios/LinuxBIOSv3/mainboard/amd/norwich/i
-nitram.c: In function 'main': /home/rminnich/src/bios/LinuxBIOSv3/mainboard/amd/n
+coreboot-v3/mainboard/amd/norwich/initram.c:41: error: (Each undeclared identifie
+r is reported only once /home/rminnich/src/bios/coreboot-v3/mainboard/amd/norwic
+h/initram.c:41: error: for each function it appears in.) /home/rminnich/src/bios/c
+oreboot-v3/mainboard/amd/norwich/initram.c:41: error: expected ';' before
+ 'msr' /home/rminnich/src/bios/coreboot-v3/mainboard/amd/norwich/initram.c:43:
+ error: 'msr' undeclared (first use in this function) /home/rminnich/src/bios/co
+reboot-v3/mainboard/amd/norwich/initram.c:45: error: implicit declaration
+ of function 'wrmsr' /home/rminnich/src/bios/coreboot-v3/mainboard/amd/norwich/i
+nitram.c: In function 'main': /home/rminnich/src/bios/coreboot-v3/mainboard/amd/n
orwich/initram.c:79: error: implicit declaration of function 'POST_CODE'
- /home/rminnich/src/bios/LinuxBIOSv3/mainboard/amd/norwich/initram.c:81:
- error: array type has incomplete element type /home/rminnich/src/bios/LinuxBIOS
+ /home/rminnich/src/bios/coreboot-v3/mainboard/amd/norwich/initram.c:81:
+ error: array type has incomplete element type /home/rminnich/src/bios/coreboot-
v3/mainboard/amd/norwich/initram.c:82: error: field name not in record or
- union initializer /home/rminnich/src/bios/LinuxBIOSv3/mainboard/amd/norwich/ini
-tram.c:82: error: (near initialization for 'memctrl') /home/rminnich/src/bios/Lin
-uxBIOSv3/mainboard/amd/norwich/initram.c:85: error: implicit declaration
- of function 'SystemPreInit' /home/rminnich/src/bios/LinuxBIOSv3/mainboard/amd/n
+ union initializer /home/rminnich/src/bios/coreboot-v3/mainboard/amd/norwich/ini
+tram.c:82: error: (near initialization for 'memctrl') /home/rminnich/src/bios/cor
+eboot-v3/mainboard/amd/norwich/initram.c:85: error: implicit declaration
+ of function 'SystemPreInit' /home/rminnich/src/bios/coreboot-v3/mainboard/amd/n
orwich/initram.c:88: error: implicit declaration of function 'cs5536_early_setup'
- /home/rminnich/src/bios/LinuxBIOSv3/mainboard/amd/norwich/initram.c:95:
+ /home/rminnich/src/bios/coreboot-v3/mainboard/amd/norwich/initram.c:95:
error: implicit declaration of function 'cs5536_setup_onchipuart' /home/rminnic
-h/src/bios/LinuxBIOSv3/mainboard/amd/norwich/initram.c:97: error: implicit
- declaration of function 'uart_init' /home/rminnich/src/bios/LinuxBIOSv3/mainboa
+h/src/bios/coreboot-v3/mainboard/amd/norwich/initram.c:97: error: implicit
+ declaration of function 'uart_init' /home/rminnich/src/bios/coreboot-v3/mainboa
rd/amd/norwich/initram.c:100: error: implicit declaration of function 'pll_reset'
- /home/rminnich/src/bios/LinuxBIOSv3/mainboard/amd/norwich/initram.c:102:
- error: implicit declaration of function 'cpuRegInit' /home/rminnich/src/bios/Li
-nuxBIOSv3/mainboard/amd/norwich/initram.c:104: error: implicit declaration
- of function 'sdram_initialize' /home/rminnich/src/bios/LinuxBIOSv3/mainboard/am
+ /home/rminnich/src/bios/coreboot-v3/mainboard/amd/norwich/initram.c:102:
+ error: implicit declaration of function 'cpuRegInit' /home/rminnich/src/bios/co
+reboot-v3/mainboard/amd/norwich/initram.c:104: error: implicit declaration
+ of function 'sdram_initialize' /home/rminnich/src/bios/coreboot-v3/mainboard/am
d/norwich/initram.c:110: warning: 'return' with no value, in function returning
- non-void /home/rminnich/src/bios/LinuxBIOSv3/mainboard/amd/norwich/initram.c:81:
+ non-void /home/rminnich/src/bios/coreboot-v3/mainboard/amd/norwich/initram.c:81:
warning: unused variable 'memctrl' make: exit 2 make: *** [/home/rminnich/src/b
-ios/LinuxBIOSv3/build/mainboard/amd/norwich/initram.o] Error 1
+ios/coreboot-v3/build/mainboard/amd/norwich/initram.o] Error 1
\end_layout
\begin_layout Standard
@@ -2191,7 +2191,7 @@
\begin_layout Standard
We need to create an initram file for the LAR.
This initram file is going to set up DRAM.
- LinuxBIOS supplies a skeleton function, which we show below, and the programmer
+ Coreboot supplies a skeleton function, which we show below, and the programmer
needs to supply some functions for their chipsets, so that this function
can work.
@@ -2442,7 +2442,7 @@
\end_layout
\begin_layout Standard
-All of the LinuxBIOS code that is run after this point uses the device tree;
+All of the coreboot code that is run after this point uses the device tree;
none of the initram code uses the device tree.
The reason is simple: the device tree lives in RAM.
This bootstrap code is intentionally simple and does not use the device
@@ -2472,7 +2472,7 @@
\end_layout
\begin_layout LyX-Code
-cp LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_smbus.c southbridge/amd/cs
+cp coreboot-v2/src/southbridge/amd/cs5536/cs5536_early_smbus.c southbridge/amd/cs
5536/smbus_initram.c
\end_layout
@@ -2501,7 +2501,7 @@
\begin_layout Standard
The errors were mainly changes to printk.
Also, we had to copy the old cs5536.h from the V2 tree.
- This file is only used for the southbridge part, so, following LinuxBIOS
+ This file is only used for the southbridge part, so, following coreboot
include rules, cs5536.h does not go in include; rather, it goes in the
\family typewriter
southbridge/amd/cs5536
Modified: coreboot-v3/include/arch/x86/amd_geodelx.h
===================================================================
--- coreboot-v3/include/arch/x86/amd_geodelx.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/arch/x86/amd_geodelx.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2006 Indrek Kruusa <indrek.kruusa at artecdesign.ee>
* Copyright (C) 2006 Ronald G. Minnich <rminnich at gmail.com>
@@ -568,7 +568,7 @@
#define DCACHE_RAM_SIZE 0x08000
#define DCACHE_RAM_BASE 0x80000
/* This is where the DCache will be mapped and be used as stack. It would be
- * cool if it was the same base as LinuxBIOS normal stack.
+ * cool if it was the same base as coreboot normal stack.
*/
#define LX_STACK_BASE DCACHE_RAM_BASE
#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4)
Modified: coreboot-v3/include/arch/x86/arch/spinlock.h
===================================================================
--- coreboot-v3/include/arch/x86/arch/spinlock.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/arch/x86/arch/spinlock.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* It is based on the Linux kernel file include/asm-i386/spinlock.h.
*
Modified: coreboot-v3/include/arch/x86/cpu.h
===================================================================
--- coreboot-v3/include/arch/x86/cpu.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/arch/x86/cpu.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* It is based on the Linux kernel files include/asm-i386/processor.h
* and arch/i386/kernel/cpu/mtrr/state.c.
Modified: coreboot-v3/include/arch/x86/div64.h
===================================================================
--- coreboot-v3/include/arch/x86/div64.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/arch/x86/div64.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* It was taken from the Linux kernel, include/asm-i386/div64.h.
*/
Modified: coreboot-v3/include/arch/x86/legacy.h
===================================================================
--- coreboot-v3/include/arch/x86/legacy.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/arch/x86/legacy.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
*
Modified: coreboot-v3/include/arch/x86/msr.h
===================================================================
--- coreboot-v3/include/arch/x86/msr.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/arch/x86/msr.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/include/arch/x86/swab.h
===================================================================
--- coreboot-v3/include/arch/x86/swab.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/arch/x86/swab.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/**
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* It is based on include/linux/byteorder/swab.h from the Linux kernel.
*/
Modified: coreboot-v3/include/device/device.h
===================================================================
--- coreboot-v3/include/device/device.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/device/device.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/include/device/pci.h
===================================================================
--- coreboot-v3/include/device/pci.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/device/pci.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* PCI defines and function prototypes
* Copyright 1994, Drew Eckhardt
Modified: coreboot-v3/include/device/pci_ids.h
===================================================================
--- coreboot-v3/include/device/pci_ids.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/device/pci_ids.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,10 +1,10 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* It is based on the include/linux/pci_ids.h file from the Linux kernel.
*
* Note: we maintain our own short list of PCI vendor IDs and device IDs
- * for LinuxBIOS, as we only need very few of the entries.
+ * for coreboot, as we only need very few of the entries.
* The 'Device classes and subclasses' section is copied from the Linux file.
*/
Modified: coreboot-v3/include/elf.h
===================================================================
--- coreboot-v3/include/elf.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/elf.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* It is based on elf/elf.h from the GNU C Library, CVS rev. 1.156.
*
@@ -2628,8 +2628,8 @@
struct lb_memory;
extern int elfboot(struct lb_memory *mem);
-#define FIRMWARE_TYPE "LinuxBIOS"
+#define FIRMWARE_TYPE "coreboot"
#define BOOTLOADER "elfboot"
-#define BOOTLOADER_VERSION "1.3"
+#define BOOTLOADER_VERSION "3.0"
#endif /* ELF_H */
Modified: coreboot-v3/include/ip_checksum.h
===================================================================
--- coreboot-v3/include/ip_checksum.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/ip_checksum.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* It was taken from kexec-tools 1.101.
*
Modified: coreboot-v3/include/isa-dma.h
===================================================================
--- coreboot-v3/include/isa-dma.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/isa-dma.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Stefan Reinauer <stepan at coresystems.de>
*
Modified: coreboot-v3/include/keyboard.h
===================================================================
--- coreboot-v3/include/keyboard.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/keyboard.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Stefan Reinauer <stepan at coresystems.de>
*
@@ -20,7 +20,7 @@
#ifndef KEYBOARD_H
#define KEYBOARD_H
-/* TODO: This structure should contain typematic settings, but LinuxBIOS
+/* TODO: This structure should contain typematic settings, but coreboot
* does not care yet.
*/
struct pc_keyboard {
Modified: coreboot-v3/include/lar.h
===================================================================
--- coreboot-v3/include/lar.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/lar.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2006 coresystems GmbH
* (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/include/lib.h
===================================================================
--- coreboot-v3/include/lib.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/lib.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 coresystems GmbH
* (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/include/mc146818rtc.h
===================================================================
--- coreboot-v3/include/mc146818rtc.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/mc146818rtc.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -101,15 +101,15 @@
#define PC_CKS_RANGE_END 45
#define PC_CKS_LOC 46
-/* Linux bios checksum is built only over bytes 49..125 */
-#ifndef LB_CKS_RANGE_START
-#define LB_CKS_RANGE_START 49
+/* coreboot checksum is built only over bytes 49..125 */
+#ifndef CB_CKS_RANGE_START
+#define CB_CKS_RANGE_START 49
#endif
-#ifndef LB_CKS_RANGE_END
-#define LB_CKS_RANGE_END 125
+#ifndef CB_CKS_RANGE_END
+#define CB_CKS_RANGE_END 125
#endif
-#ifndef LB_CKS_LOC
-#define LB_CKS_LOC 126
+#ifndef CB_CKS_LOC
+#define CB_CKS_LOC 126
#endif
#define RTC_BOOT_BYTE 48
Modified: coreboot-v3/include/post_code.h
===================================================================
--- coreboot-v3/include/post_code.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/post_code.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/include/shared.h
===================================================================
--- coreboot-v3/include/shared.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/shared.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project
+ * This file is part of the coreboot project
*
* Copyright(C) 2007 coresystems GmbH
* Written by Stefan Reinauer <stepan at coresystems.de>
Modified: coreboot-v3/include/spd.h
===================================================================
--- coreboot-v3/include/spd.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/spd.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2005 Digital Design Corporation
* Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
Modified: coreboot-v3/include/spinlock.h
===================================================================
--- coreboot-v3/include/spinlock.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/spinlock.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2001 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
Modified: coreboot-v3/include/string.h
===================================================================
--- coreboot-v3/include/string.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/string.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
*
Modified: coreboot-v3/include/tables.h
===================================================================
--- coreboot-v3/include/tables.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/include/tables.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2002 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
@@ -24,15 +24,15 @@
#define TABLES_H
/*
- * Table management structs and prototypes for LinuxBIOS.
+ * Table management structs and prototypes for coreboot.
*
- * ALL structs and prototypes for tables that LinuxBIOS generates should be
+ * ALL structs and prototypes for tables that coreboot generates should be
* defined here.
*/
struct lb_memory *write_tables(void);
-/* The LinuxBIOS table information is for conveying information
+/* The coreboot table information is for conveying information
* from the firmware to the loaded OS image. Primarily this
* is expected to be information that cannot be discovered by
* other means, such as quering the hardware directly.
@@ -60,12 +60,12 @@
* table entries and be backwards compatible, but it is not required.
*/
-/* Since LinuxBIOS is usually compiled 32bit, gcc will align 64bit
- * types to 32bit boundaries. If the LinuxBIOS table is dumped on a
+/* Since coreboot is usually compiled 32bit, gcc will align 64bit
+ * types to 32bit boundaries. If the coreboot table is dumped on a
* 64bit system, a u64 would be aligned to 64bit boundaries,
* breaking the table format.
*
- * lb_uint64 will keep 64bit LinuxBIOS table values aligned to 32bit
+ * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
* to ensure compatibility. They can be accessed with the two functions
* below: unpack_lb64() and pack_lb64()
*
@@ -249,7 +249,7 @@
};
struct lb_memory *arch_write_tables(void);
-unsigned long write_linuxbios_table(
+unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end);
@@ -262,8 +262,8 @@
struct lb_mainboard *lb_mainboard(struct lb_header *header);
unsigned long lb_table_fini(struct lb_header *header);
-/* Routines to extract part so the linuxBIOS table or information
- * from the linuxBIOS table.
+/* Routines to extract part so the coreboot table or information
+ * from the coreboot table.
*/
struct lb_memory *get_lb_mem(void);
Modified: coreboot-v3/lib/Kconfig
===================================================================
--- coreboot-v3/lib/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
@@ -54,7 +54,7 @@
config DEFAULT_COMPRESSION_NONE
bool "No compression"
help
- Do not compress any LinuxBIOS modules per default.
+ Do not compress any coreboot modules per default.
endchoice
@@ -139,7 +139,7 @@
default y
depends CONSOLE
help
- Send LinuxBIOS output to serial console.
+ Send coreboot output to serial console.
choice
prompt "Serial console COM port"
@@ -194,7 +194,7 @@
boolean "USB2 console support (EXPERIMENTAL)"
depends CONSOLE && EXPERIMENTAL
help
- Send LinuxBIOS output to USB2 (EHCI) console.
+ Send coreboot output to USB2 (EHCI) console.
Note: This requires a USB2 controller which supports the EHCI
Debug Port capability. Controllers which are known to work:
@@ -210,7 +210,7 @@
* 8086:2836 Intel ICH8
* 8086:283a Intel ICH8
- See http://linuxbios.org/EHCI_Debug_Port for an up-to-date list.
+ See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list.
comment "Cosmetic console options"
depends EXPERT && (CONSOLE_SERIAL || CONSOLE_USB)
@@ -220,7 +220,7 @@
depends EXPERT && (CONSOLE_SERIAL || CONSOLE_USB)
default n
help
- When you enable this option, LinuxBIOS will prefix each line of
+ When you enable this option, coreboot will prefix each line of
console output with '(LB)'.
endmenu
Modified: coreboot-v3/lib/Makefile
===================================================================
--- coreboot-v3/lib/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2006-2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/lib/clog2.c
===================================================================
--- coreboot-v3/lib/clog2.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/clog2.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* It is based on the file js/src/jscpucfg.c from Mozilla, CVS rev. 3.25.
* See http://lxr.mozilla.org/mozilla1.8.0/source/js/src/jscpucfg.c.
Modified: coreboot-v3/lib/compute_ip_checksum.c
===================================================================
--- coreboot-v3/lib/compute_ip_checksum.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/compute_ip_checksum.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* It was taken from kexec-tools 1.101.
*
Modified: coreboot-v3/lib/console.c
===================================================================
--- coreboot-v3/lib/console.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/console.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -72,11 +72,11 @@
void console_init(void)
{
static const char console_test[] =
- "\n\nLinuxBIOS-"
- LINUXBIOS_VERSION
- LINUXBIOS_EXTRA_VERSION
+ "\n\ncoreboot-"
+ COREBOOT_VERSION
+ COREBOOT_EXTRA_VERSION
" "
- LINUXBIOS_BUILD
+ COREBOOT_BUILD
" starting...\n";
printk(BIOS_INFO, console_test);
Modified: coreboot-v3/lib/delay.c
===================================================================
--- coreboot-v3/lib/delay.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/delay.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2001 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
Modified: coreboot-v3/lib/elfboot.c
===================================================================
--- coreboot-v3/lib/elfboot.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/elfboot.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2002 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
@@ -21,7 +21,7 @@
/* elfboot -- boot elf images */
-/* This code is modified from the LinuxBIOS V2 version as follows:
+/* This code is modified from the coreboot V2 version as follows:
* great simplified
* checksum removed -- lar can do that
* can run from read-only FLASH
Modified: coreboot-v3/lib/lar.c
===================================================================
--- coreboot-v3/lib/lar.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/lar.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2006-2007 coresystems GmbH
* (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/lib/lzma.c
===================================================================
--- coreboot-v3/lib/lzma.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/lzma.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,6 +1,6 @@
/*
-LinuxBIOS interface to memory-saving variant of LZMA decoder
+coreboot interface to memory-saving variant of LZMA decoder
(C)opyright 2006 Carl-Daniel Hailfinger
Released under the GNU GPL
Modified: coreboot-v3/lib/mem.c
===================================================================
--- coreboot-v3/lib/mem.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/mem.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
* Copyright (C) 2007 Peter Stuge <peter at stuge.se>
Modified: coreboot-v3/lib/ram.c
===================================================================
--- coreboot-v3/lib/ram.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/ram.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
* Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
Modified: coreboot-v3/lib/stage2.c
===================================================================
--- coreboot-v3/lib/stage2.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/stage2.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ron Minnich <rminnich at lanl.gov>
* Copyright (C) 2007 coresystems GmbH
@@ -19,7 +19,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
*/
-/* stage2 - LinuxBIOS RAM-based setup. */
+/* stage2 - coreboot RAM-based setup. */
#include <types.h>
#include <string.h>
@@ -29,9 +29,9 @@
#include <tables.h>
/**
- * Main function of the DRAM part of LinuxBIOS.
+ * Main function of the DRAM part of coreboot.
*
- * LinuxBIOS is divided into pre-DRAM part and DRAM part. The stages before
+ * Coreboot is divided into pre-DRAM part and DRAM part. The stages before
* this part are stage 0 and stage 1. This part contains stage 2, which
* consists of phases 1 through 6.
* printk has been set up in stage 1 and is working.
Modified: coreboot-v3/lib/string.c
===================================================================
--- coreboot-v3/lib/string.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/string.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
*
Modified: coreboot-v3/lib/tables.c
===================================================================
--- coreboot-v3/lib/tables.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/tables.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2002 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
@@ -19,7 +19,7 @@
*/
/*
- * Table management code for LinuxBIOS.
+ * Table management code for coreboot.
*
* This is the architecture-independent driver; it has a hook to
* architecture-dependent code.
Modified: coreboot-v3/lib/vsprintf.c
===================================================================
--- coreboot-v3/lib/vsprintf.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/vsprintf.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* It is based on the Linux kernel (lib/vsprintf.c).
*
Modified: coreboot-v3/lib/vtxprintf.c
===================================================================
--- coreboot-v3/lib/vtxprintf.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/lib/vtxprintf.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* It is based on the Linux kernel (lib/vsprintf.c).
*
Modified: coreboot-v3/mainboard/Kconfig
===================================================================
--- coreboot-v3/mainboard/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2006 Segher Boessenkool <segher at kernel.crashing.org>
## Copyright (C) 2006-2007 coresystems GmbH
@@ -62,42 +62,42 @@
choice
prompt "ROM chip size"
- default LINUXBIOS_ROMSIZE_KB_256
+ default COREBOOT_ROMSIZE_KB_256
-config LINUXBIOS_ROMSIZE_KB_128
+config COREBOOT_ROMSIZE_KB_128
bool "128 KB"
help
Choose this option if you have a 128 KB ROM chip.
-config LINUXBIOS_ROMSIZE_KB_256
+config COREBOOT_ROMSIZE_KB_256
bool "256 KB"
help
Choose this option if you have a 256 KB ROM chip.
-config LINUXBIOS_ROMSIZE_KB_512
+config COREBOOT_ROMSIZE_KB_512
bool "512 KB"
help
Choose this option if you have a 512 KB ROM chip.
-config LINUXBIOS_ROMSIZE_KB_1024
+config COREBOOT_ROMSIZE_KB_1024
bool "1024 KB (1 MB)"
help
Choose this option if you have a 1024 KB (1 MB) ROM chip.
-config LINUXBIOS_ROMSIZE_KB_2048
+config COREBOOT_ROMSIZE_KB_2048
bool "2048 KB (2 MB)"
help
Choose this option if you have a 2048 KB (2 MB) ROM chip.
endchoice
-config LINUXBIOS_ROMSIZE_KB
+config COREBOOT_ROMSIZE_KB
int
- default 128 if LINUXBIOS_ROMSIZE_KB_128
- default 256 if LINUXBIOS_ROMSIZE_KB_256
- default 512 if LINUXBIOS_ROMSIZE_KB_512
- default 1024 if LINUXBIOS_ROMSIZE_KB_1024
- default 2048 if LINUXBIOS_ROMSIZE_KB_2048
+ default 128 if COREBOOT_ROMSIZE_KB_128
+ default 256 if COREBOOT_ROMSIZE_KB_256
+ default 512 if COREBOOT_ROMSIZE_KB_512
+ default 1024 if COREBOOT_ROMSIZE_KB_1024
+ default 2048 if COREBOOT_ROMSIZE_KB_2048
help
Map the config names to an integer.
Modified: coreboot-v3/mainboard/adl/Kconfig
===================================================================
--- coreboot-v3/mainboard/adl/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/adl/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/mainboard/adl/msm800sev/Kconfig
===================================================================
--- coreboot-v3/mainboard/adl/msm800sev/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/adl/msm800sev/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/mainboard/adl/msm800sev/Makefile
===================================================================
--- coreboot-v3/mainboard/adl/msm800sev/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/adl/msm800sev/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2006-2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
@@ -28,7 +28,7 @@
STAGE2_MAINBOARD_OBJ =
-$(obj)/linuxbios.vpd:
+$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
- $(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT)
+ $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
Modified: coreboot-v3/mainboard/adl/msm800sev/dts
===================================================================
--- coreboot-v3/mainboard/adl/msm800sev/dts 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/adl/msm800sev/dts 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
* Copyright (C) 2007 coresystems GmbH
Modified: coreboot-v3/mainboard/adl/msm800sev/initram.c
===================================================================
--- coreboot-v3/mainboard/adl/msm800sev/initram.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/adl/msm800sev/initram.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/mainboard/adl/msm800sev/stage1.c
===================================================================
--- coreboot-v3/mainboard/adl/msm800sev/stage1.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/adl/msm800sev/stage1.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/mainboard/amd/Kconfig
===================================================================
--- coreboot-v3/mainboard/amd/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/amd/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/mainboard/amd/norwich/Kconfig
===================================================================
--- coreboot-v3/mainboard/amd/norwich/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/amd/norwich/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/mainboard/amd/norwich/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/norwich/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/amd/norwich/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2006-2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
@@ -28,7 +28,7 @@
STAGE2_MAINBOARD_OBJ =
-$(obj)/linuxbios.vpd:
+$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
- $(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT)
+ $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
Modified: coreboot-v3/mainboard/amd/norwich/dts
===================================================================
--- coreboot-v3/mainboard/amd/norwich/dts 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/amd/norwich/dts 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/mainboard/amd/norwich/initram.c
===================================================================
--- coreboot-v3/mainboard/amd/norwich/initram.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/amd/norwich/initram.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/mainboard/amd/norwich/stage1.c
===================================================================
--- coreboot-v3/mainboard/amd/norwich/stage1.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/amd/norwich/stage1.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/mainboard/artecgroup/Kconfig
===================================================================
--- coreboot-v3/mainboard/artecgroup/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/artecgroup/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/mainboard/artecgroup/dbe61/Kconfig
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/artecgroup/dbe61/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/mainboard/artecgroup/dbe61/Makefile
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/artecgroup/dbe61/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2006-2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
@@ -26,7 +26,7 @@
STAGE2_MAINBOARD_OBJ =
-$(obj)/linuxbios.vpd:
+$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
- $(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT)
+ $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/mainboard/artecgroup/dbe61/stage1.c
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/stage1.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/artecgroup/dbe61/stage1.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/mainboard/emulation/Kconfig
===================================================================
--- coreboot-v3/mainboard/emulation/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/emulation/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2006 Segher Boessenkool <segher at kernel.crashing.org>
## Copyright (C) 2006-2007 coresystems GmbH
Modified: coreboot-v3/mainboard/emulation/qemu-x86/Kconfig
===================================================================
--- coreboot-v3/mainboard/emulation/qemu-x86/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/emulation/qemu-x86/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/mainboard/emulation/qemu-x86/Makefile
===================================================================
--- coreboot-v3/mainboard/emulation/qemu-x86/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/emulation/qemu-x86/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2006-2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
@@ -39,7 +39,7 @@
# Do we want to put our own stuff there, too?
#
-$(obj)/linuxbios.vpd:
+$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
- $(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT)
+ $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
Modified: coreboot-v3/mainboard/emulation/qemu-x86/dts
===================================================================
--- coreboot-v3/mainboard/emulation/qemu-x86/dts 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/emulation/qemu-x86/dts 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/mainboard/emulation/qemu-x86/initram.c
===================================================================
--- coreboot-v3/mainboard/emulation/qemu-x86/initram.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/emulation/qemu-x86/initram.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Stefan Reinauer <stepan at coresystems.de>
* Copyright (C) 2007 Carl-Daniel Hailfinger
Modified: coreboot-v3/mainboard/emulation/qemu-x86/initram_printktest.c
===================================================================
--- coreboot-v3/mainboard/emulation/qemu-x86/initram_printktest.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/emulation/qemu-x86/initram_printktest.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Carl-Daniel Hailfinger
*
Modified: coreboot-v3/mainboard/emulation/qemu-x86/stage1.c
===================================================================
--- coreboot-v3/mainboard/emulation/qemu-x86/stage1.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/emulation/qemu-x86/stage1.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/mainboard/emulation/qemu-x86/vga.c
===================================================================
--- coreboot-v3/mainboard/emulation/qemu-x86/vga.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/emulation/qemu-x86/vga.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 coresystems GmbH
* (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/mainboard/pcengines/Kconfig
===================================================================
--- coreboot-v3/mainboard/pcengines/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/pcengines/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/mainboard/pcengines/alix1c/Kconfig
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/pcengines/alix1c/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/mainboard/pcengines/alix1c/Makefile
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/pcengines/alix1c/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2006-2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
@@ -27,7 +27,7 @@
STAGE2_MAINBOARD_OBJ =
-$(obj)/linuxbios.vpd:
+$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
- $(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT)
+ $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
Modified: coreboot-v3/mainboard/pcengines/alix1c/dts
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/dts 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/mainboard/pcengines/alix1c/initram.c
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/initram.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/pcengines/alix1c/initram.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/mainboard/pcengines/alix1c/stage1.c
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/stage1.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/mainboard/pcengines/alix1c/stage1.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/northbridge/amd/geodelx/Makefile
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/northbridge/amd/geodelx/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/northbridge/amd/geodelx/dts
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/dts 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/northbridge/amd/geodelx/dts 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/northbridge/amd/geodelx/geodelxinit.c
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/geodelxinit.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/northbridge/amd/geodelx/geodelxinit.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/northbridge/amd/geodelx/raminit.h
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/raminit.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/northbridge/amd/geodelx/raminit.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/northbridge/intel/i440bxemulation/Kconfig
===================================================================
--- coreboot-v3/northbridge/intel/i440bxemulation/Kconfig 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/northbridge/intel/i440bxemulation/Kconfig 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
## Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
Modified: coreboot-v3/northbridge/intel/i440bxemulation/Makefile
===================================================================
--- coreboot-v3/northbridge/intel/i440bxemulation/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/northbridge/intel/i440bxemulation/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2006-2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/northbridge/intel/i440bxemulation/dts
===================================================================
--- coreboot-v3/northbridge/intel/i440bxemulation/dts 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/northbridge/intel/i440bxemulation/dts 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c
===================================================================
--- coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2000 Ron Minnich, Advanced Computing Lab, LANL
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
Modified: coreboot-v3/northbridge/intel/i440bxemulation/i440bx.h
===================================================================
--- coreboot-v3/northbridge/intel/i440bxemulation/i440bx.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/northbridge/intel/i440bxemulation/i440bx.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
*
Modified: coreboot-v3/southbridge/amd/cs5536/Makefile
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/southbridge/amd/cs5536/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.h
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/cs5536.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/southbridge/amd/cs5536/cs5536.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/southbridge/amd/cs5536/dts
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/dts 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/southbridge/amd/cs5536/dts 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/southbridge/amd/cs5536/smbus_initram.c
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/smbus_initram.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/southbridge/amd/cs5536/smbus_initram.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/southbridge/amd/cs5536/stage1.c
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/stage1.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/southbridge/amd/cs5536/stage1.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
Modified: coreboot-v3/southbridge/intel/i82371eb/Makefile
===================================================================
--- coreboot-v3/southbridge/intel/i82371eb/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/southbridge/intel/i82371eb/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
##
Modified: coreboot-v3/southbridge/intel/i82371eb/dts
===================================================================
--- coreboot-v3/southbridge/intel/i82371eb/dts 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/southbridge/intel/i82371eb/dts 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/southbridge/intel/i82371eb/i82371eb.c
===================================================================
--- coreboot-v3/southbridge/intel/i82371eb/i82371eb.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/southbridge/intel/i82371eb/i82371eb.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2004 Linux Networx
* Copyright (C) 2005 Bitworks
Modified: coreboot-v3/superio/fintek/f71805f/Makefile
===================================================================
--- coreboot-v3/superio/fintek/f71805f/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/superio/fintek/f71805f/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
##
Modified: coreboot-v3/superio/fintek/f71805f/dts
===================================================================
--- coreboot-v3/superio/fintek/f71805f/dts 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/superio/fintek/f71805f/dts 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
*
Modified: coreboot-v3/superio/fintek/f71805f/f71805f.h
===================================================================
--- coreboot-v3/superio/fintek/f71805f/f71805f.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/superio/fintek/f71805f/f71805f.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Corey Osgood <corey at slightlyhackish.com>
*
Modified: coreboot-v3/superio/fintek/f71805f/stage1.c
===================================================================
--- coreboot-v3/superio/fintek/f71805f/stage1.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/superio/fintek/f71805f/stage1.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright 2007 Corey Osgood <corey.osgood at gmail.com>
*
Modified: coreboot-v3/superio/fintek/f71805f/superio.c
===================================================================
--- coreboot-v3/superio/fintek/f71805f/superio.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/superio/fintek/f71805f/superio.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright 2007 Corey Osgood <corey.osgood at gmail.com>
*
Modified: coreboot-v3/superio/winbond/w83627hf/Makefile
===================================================================
--- coreboot-v3/superio/winbond/w83627hf/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/superio/winbond/w83627hf/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/superio/winbond/w83627hf/dts
===================================================================
--- coreboot-v3/superio/winbond/w83627hf/dts 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/superio/winbond/w83627hf/dts 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/superio/winbond/w83627hf/stage1.c
===================================================================
--- coreboot-v3/superio/winbond/w83627hf/stage1.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/superio/winbond/w83627hf/stage1.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright 2007 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/superio/winbond/w83627hf/superio.c
===================================================================
--- coreboot-v3/superio/winbond/w83627hf/superio.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/superio/winbond/w83627hf/superio.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright 2000 AG Electronics Ltd.
* Copyright 2003-2004 Linux Networx
Modified: coreboot-v3/superio/winbond/w83627hf/w83627hf.h
===================================================================
--- coreboot-v3/superio/winbond/w83627hf/w83627hf.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/superio/winbond/w83627hf/w83627hf.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright 2007 Ronald G. Minnich <rminnich at gmail.com>
*
Modified: coreboot-v3/util/Makefile
===================================================================
--- coreboot-v3/util/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
@@ -24,12 +24,12 @@
include util/kconfig/Makefile
include util/options/Makefile
-# Parts used by LinuxBIOS.
+# Parts used by coreboot.
include util/x86emu/Makefile
# Compressors.
include util/lzma/Makefile
include util/nrv2b/Makefile
-# LinuxBIOS archiver
+# coreboot lightweight archiver
include util/lar/Makefile
Modified: coreboot-v3/util/doxygen/Doxyfile.LinuxBIOS
===================================================================
--- coreboot-v3/util/doxygen/Doxyfile.LinuxBIOS 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/doxygen/Doxyfile.LinuxBIOS 2008-01-27 18:54:57 UTC (rev 564)
@@ -17,7 +17,7 @@
# The PROJECT_NAME tag is a single word (or a sequence of words surrounded
# by quotes) that should identify the project.
-PROJECT_NAME = LinuxBIOS
+PROJECT_NAME = coreboot
# The PROJECT_NUMBER tag can be used to enter a project or revision number.
# This could be handy for archiving the generated documentation or
Modified: coreboot-v3/util/dtc/dtc.c
===================================================================
--- coreboot-v3/util/dtc/dtc.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/dtc/dtc.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -91,7 +91,7 @@
fprintf(stderr, "\t\t\tdts - device tree source text\n");
fprintf(stderr, "\t\t\tdtb - device tree blob\n");
fprintf(stderr, "\t\t\tasm - assembler source\n");
- fprintf(stderr, "\t\t\tlinuxbios (or just lb) - linuxbios source\n");
+ fprintf(stderr, "\t\t\tcoreboot (or just lb) - coreboot source\n");
fprintf(stderr, "\t-V <output version>\n");
fprintf(stderr, "\t\tBlob version to produce, defaults to 3 (relevant for dtb\n\t\tand asm output only)\n");
fprintf(stderr, "\t-R <number>\n");
@@ -199,10 +199,10 @@
dt_to_asm(outf, bi, outversion, boot_cpuid_phys);
} else if (streq(outform, "C")) {
dt_to_C(outf, bi, outversion, boot_cpuid_phys);
- } else if (streq(outform, "linuxbios") || streq(outform, "lb")) {
- dt_to_linuxbios(outf, bi, outversion, boot_cpuid_phys);
- } else if (streq(outform, "linuxbiosinclude") || streq(outform, "lbh")) {
- dt_to_linuxbiosh(outf, bi, outversion, boot_cpuid_phys);
+ } else if (streq(outform, "coreboot") || streq(outform, "lb")) {
+ dt_to_coreboot(outf, bi, outversion, boot_cpuid_phys);
+ } else if (streq(outform, "corebootinclude") || streq(outform, "lbh")) {
+ dt_to_corebooth(outf, bi, outversion, boot_cpuid_phys);
} else if (streq(outform, "null")) {
/* do nothing */
} else {
Modified: coreboot-v3/util/dtc/dtc.h
===================================================================
--- coreboot-v3/util/dtc/dtc.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/dtc/dtc.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -218,8 +218,8 @@
void dt_to_asm(FILE *f, struct boot_info *bi, int version,
int boot_cpuid_phys);
void dt_to_C(FILE *f, struct boot_info *bi, int version, int boot_cpuid_phys);
-void dt_to_linuxbios(FILE *f, struct boot_info *bi, int version, int boot_cpuid_phys);
-void dt_to_linuxbiosh(FILE *f, struct boot_info *bi, int version, int boot_cpuid_phys);
+void dt_to_coreboot(FILE *f, struct boot_info *bi, int version, int boot_cpuid_phys);
+void dt_to_corebooth(FILE *f, struct boot_info *bi, int version, int boot_cpuid_phys);
struct boot_info *dt_from_blob(FILE *f);
Modified: coreboot-v3/util/dtc/endian.h
===================================================================
--- coreboot-v3/util/dtc/endian.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/dtc/endian.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -2,7 +2,7 @@
#define _OSDEP_ENDIAN_H
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2006 Michael Niedermayer <michaelni at gmx.at>
* Copyright (C) 2007 Patrick Georgi <patrick at georgi-clan.de>
Modified: coreboot-v3/util/dtc/flattree.c
===================================================================
--- coreboot-v3/util/dtc/flattree.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/dtc/flattree.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -405,16 +405,16 @@
};
-/* LinuxBIOS static.c */
+/* coreboot static.c */
-static void linuxbios_emit_cell(void *e, cell_t val)
+static void coreboot_emit_cell(void *e, cell_t val)
{
FILE *f = e;
fprintf(f, "\tu32\tc%d = 0x%x;\n", unique++, val);
}
-static void linuxbios_emit_string(void *e, char *str, int len)
+static void coreboot_emit_string(void *e, char *str, int len)
{
FILE *f = e;
char c = 0;
@@ -432,14 +432,14 @@
}
}
-static void linuxbios_emit_align(void *e, int a)
+static void coreboot_emit_align(void *e, int a)
{
FILE *f = e;
fprintf(f, "\tALIGN(x)\t%d\n", a);
}
-static void linuxbios_emit_data(void *e, struct property *p)
+static void coreboot_emit_data(void *e, struct property *p)
{
struct data d = p->val;
FILE *f = e;
@@ -465,7 +465,7 @@
#endif
}
-static void linuxbios_emit_beginnode(void *e, char *label)
+static void coreboot_emit_beginnode(void *e, char *label)
{
FILE *f = e;
@@ -474,7 +474,7 @@
}
}
-static void linuxbios_emit_endnode(void *e, char *label)
+static void coreboot_emit_endnode(void *e, char *label)
{
FILE *f = e;
@@ -483,8 +483,8 @@
}
}
-#ifdef LINUXBIOS_OUTPUT
-static void linuxbios_emit_struct_start(void *e, char *prefix, char *label)
+#ifdef COREBOOT_OUTPUT
+static void coreboot_emit_struct_start(void *e, char *prefix, char *label)
{
FILE *f = e;
@@ -493,7 +493,7 @@
}
}
-static void linuxbios_emit_struct_end(void *e, char *prefix, char *label)
+static void coreboot_emit_struct_end(void *e, char *prefix, char *label)
{
FILE *f = e;
@@ -504,7 +504,7 @@
#endif
-static void linuxbios_emit_property(void *e, char *label)
+static void coreboot_emit_property(void *e, char *label)
{
FILE *f = e;
@@ -514,7 +514,7 @@
fprintf(f, "\tu32 p%d = \tOF_DT_PROP;\n", unique++);
}
-static void linuxbios_emit_special(FILE *e, struct node *tree)
+static void coreboot_emit_special(FILE *e, struct node *tree)
{
FILE *f = e;
struct property *prop;
@@ -634,15 +634,15 @@
fprintf(f, "};\n");
}
-static struct emitter linuxbios_emitter = {
- .cell = linuxbios_emit_cell,
- .string = linuxbios_emit_string,
- .align = linuxbios_emit_align,
- .data = linuxbios_emit_data,
- .beginnode = linuxbios_emit_beginnode,
- .endnode = linuxbios_emit_endnode,
- .property = linuxbios_emit_property,
- .special = linuxbios_emit_special,
+static struct emitter coreboot_emitter = {
+ .cell = coreboot_emit_cell,
+ .string = coreboot_emit_string,
+ .align = coreboot_emit_align,
+ .data = coreboot_emit_data,
+ .beginnode = coreboot_emit_beginnode,
+ .endnode = coreboot_emit_endnode,
+ .property = coreboot_emit_property,
+ .special = coreboot_emit_special,
};
@@ -1279,7 +1279,7 @@
first_node = root;
}
-void dt_to_linuxbios(FILE *f, struct boot_info *bi, int version, int boot_cpuid_phys)
+void dt_to_coreboot(FILE *f, struct boot_info *bi, int version, int boot_cpuid_phys)
{
struct property *prop;
struct version_info *vi = NULL;
@@ -1339,16 +1339,16 @@
/* emit the code, if any */
if (code)
fprintf(f, "%s\n", code);
- flatten_tree_emit_structinits(bi->dt, &linuxbios_emitter, f, &strbuf, vi);
+ flatten_tree_emit_structinits(bi->dt, &coreboot_emitter, f, &strbuf, vi);
fprintf(f, "struct constructor *all_constructors[] = {\n");
- flatten_tree_emit_constructors(bi->dt, &linuxbios_emitter, f, &strbuf, vi);
+ flatten_tree_emit_constructors(bi->dt, &coreboot_emitter, f, &strbuf, vi);
fprintf(f, "\t0\n};\n");
data_free(strbuf);
/* */
}
-void dt_to_linuxbiosh(FILE *f, struct boot_info *bi, int version, int boot_cpuid_phys)
+void dt_to_corebooth(FILE *f, struct boot_info *bi, int version, int boot_cpuid_phys)
{
struct version_info *vi = NULL;
int i;
@@ -1377,9 +1377,9 @@
/* emit any includes that we need -- TODO: ONLY ONCE PER TYPE*/
fprintf(f, "#include <device/device.h>\n#include <device/pci.h>\n");
fprintf(f, "extern const char *mainboard_vendor, *mainboard_part_number;\n");
- flatten_tree_emit_includes(bi->dt, &linuxbios_emitter, f, &strbuf, vi);
+ flatten_tree_emit_includes(bi->dt, &coreboot_emitter, f, &strbuf, vi);
- flatten_tree_emit_structdecls(bi->dt, &linuxbios_emitter, f, &strbuf, vi);
+ flatten_tree_emit_structdecls(bi->dt, &coreboot_emitter, f, &strbuf, vi);
/* */
}
Modified: coreboot-v3/util/kconfig/confdata.c
===================================================================
--- coreboot-v3/util/kconfig/confdata.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/kconfig/confdata.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -381,7 +381,7 @@
fprintf(out, _("#\n"
"# Automatically generated make config: don't edit\n"
- "# LinuxBIOS version: %s\n"
+ "# coreboot version: %s\n"
"%s%s"
"#\n"),
sym_get_string_value(sym),
@@ -390,7 +390,7 @@
if (out_h)
fprintf(out_h, "/*\n"
" * Automatically generated C config: don't edit\n"
- " * LinuxBIOS version: %s\n"
+ " * coreboot version: %s\n"
"%s%s"
" */\n"
"#define AUTOCONF_INCLUDED\n",
@@ -508,7 +508,7 @@
fclose(out);
if (out_h) {
fclose(out_h);
- rename(".tmpconfig.h", "include/linuxbios/autoconf.h");
+ rename(".tmpconfig.h", "include/coreboot/autoconf.h");
file_write_dep(NULL);
}
if (!name || basename != conf_def_filename) {
Modified: coreboot-v3/util/kconfig/gconf.c
===================================================================
--- coreboot-v3/util/kconfig/gconf.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/kconfig/gconf.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -275,7 +275,7 @@
/*"style", PANGO_STYLE_OBLIQUE, */
NULL);
- sprintf(title, _("LinuxBIOS v%s Configuration"),
+ sprintf(title, _("coreboot v%s configuration"),
getenv("KERNELVERSION"));
gtk_window_set_title(GTK_WINDOW(main_wnd), title);
@@ -742,7 +742,7 @@
GtkWidget *dialog;
const gchar *intro_text = _(
"Welcome to gkc, the GTK+ graphical kernel configuration tool\n"
- "for LinuxBIOS.\n"
+ "for coreboot.\n"
"For each option, a blank box indicates the feature is disabled, a\n"
"check indicates it is enabled, and a dot indicates that it is to\n"
"be compiled as a module. Clicking on the box will cycle through the three states.\n"
Modified: coreboot-v3/util/kconfig/mconf.c
===================================================================
--- coreboot-v3/util/kconfig/mconf.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/kconfig/mconf.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1055,7 +1055,7 @@
sym = sym_lookup("KERNELVERSION", 0);
sym_calc_value(sym);
- sprintf(menu_backtitle, _("LinuxBIOS v%s Configuration"),
+ sprintf(menu_backtitle, _("coreboot v%s configuration"),
sym_get_string_value(sym));
mode = getenv("MENUCONFIG_MODE");
@@ -1089,7 +1089,7 @@
return 1;
}
printf(_("\n\n"
- "*** End of LinuxBIOS configuration.\n"
+ "*** End of coreboot configuration.\n"
"*** Execute 'make' to build the firmware or try 'make help'."
"\n\n"));
} else {
Modified: coreboot-v3/util/kconfig/util.c
===================================================================
--- coreboot-v3/util/kconfig/util.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/kconfig/util.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -44,7 +44,7 @@
else
fprintf(out, "\t%s\n", file->name);
}
- fprintf(out, "\n.config $(objtree)/include/linuxbios/autoconf.h: $(deps_config)\n\n$(deps_config):\n");
+ fprintf(out, "\n.config $(objtree)/include/coreboot/autoconf.h: $(deps_config)\n\n$(deps_config):\n");
fclose(out);
rename("..config.tmp", name);
return 0;
Modified: coreboot-v3/util/kconfig/zconf.tab.c_shipped
===================================================================
--- coreboot-v3/util/kconfig/zconf.tab.c_shipped 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/kconfig/zconf.tab.c_shipped 2008-01-27 18:54:57 UTC (rev 564)
@@ -1949,7 +1949,7 @@
sym_init();
menu_init();
modules_sym = sym_lookup("MODULES", 0);
- rootmenu.prompt = menu_add_prompt(P_MENU, "LinuxBIOS Configuration", NULL);
+ rootmenu.prompt = menu_add_prompt(P_MENU, "coreboot configuration", NULL);
#if YYDEBUG
if (getenv("ZCONF_DEBUG"))
Modified: coreboot-v3/util/kconfig/zconf.y
===================================================================
--- coreboot-v3/util/kconfig/zconf.y 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/kconfig/zconf.y 2008-01-27 18:54:57 UTC (rev 564)
@@ -459,7 +459,7 @@
sym_init();
menu_init();
modules_sym = sym_lookup("MODULES", 0);
- rootmenu.prompt = menu_add_prompt(P_MENU, "LinuxBIOS Configuration", NULL);
+ rootmenu.prompt = menu_add_prompt(P_MENU, "coreboot configuration", NULL);
#if YYDEBUG
if (getenv("ZCONF_DEBUG"))
Modified: coreboot-v3/util/lar/Makefile
===================================================================
--- coreboot-v3/util/lar/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/lar/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,7 +1,7 @@
##
-## lar - LinuxBIOS archiver
+## lar - lightweight archiver
##
-## Copyright (C) 2006-2007 coresystems GmbH
+## Copyright (C) 2006-2008 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
##
## This program is free software; you can redistribute it and/or modify
@@ -61,9 +61,9 @@
$(Q)mkdir -p tree/normal
$(Q)mkdir -p tree/fallback
$(Q)dd if=/dev/urandom of=tree/compression/lzma bs=1k count=8 &>/dev/null
- $(Q)dd if=/dev/urandom of=tree/normal/linuxbios.elf.lzma bs=1k count=32 &>/dev/null
+ $(Q)dd if=/dev/urandom of=tree/normal/coreboot.elf.lzma bs=1k count=32 &>/dev/null
$(Q)dd if=/dev/urandom of=tree/normal/initmem bs=1k count=16 &>/dev/null
- $(Q)dd if=/dev/urandom of=tree/fallback/linuxbios.elf.lzma bs=1k count=32 &>/dev/null
+ $(Q)dd if=/dev/urandom of=tree/fallback/coreboot.elf.lzma bs=1k count=32 &>/dev/null
$(Q)dd if=/dev/urandom of=tree/fallback/initmem bs=1k count=16 &>/dev/null
$(Q)printf "done.\n"
Modified: coreboot-v3/util/lar/README
===================================================================
--- coreboot-v3/util/lar/README 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/lar/README 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,4 +1,4 @@
-LinuxBIOS Archiver: lar
+Lightweight Archiver: lar
-----------------------
Table of Contents
@@ -12,7 +12,8 @@
Introduction
------------
-This is a simple archiver, similar to cpio, ar or tar.
+This is a simple archiver, similar to cpio, ar or tar. It was designed and
+written for coreboot.
Design goals were
- minimum overhead
Modified: coreboot-v3/util/lar/bootblock.c
===================================================================
--- coreboot-v3/util/lar/bootblock.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/lar/bootblock.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * lar - LinuxBIOS archiver
+ * lar - lightweight archiver
*
* Copyright (C) 2007 coresystems GmbH
* (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/util/lar/example.c
===================================================================
--- coreboot-v3/util/lar/example.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/lar/example.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * lar - LinuxBIOS archiver
+ * lar - lightweight archiver
*
* Copyright (C) 2006-2007 coresystems GmbH
* (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/util/lar/lar.c
===================================================================
--- coreboot-v3/util/lar/lar.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/lar/lar.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,7 +1,7 @@
/*
- * lar - LinuxBIOS archiver
+ * lar - lightweight archiver
*
- * Copyright (C) 2006-2007 coresystems GmbH
+ * Copyright (C) 2006-2008 coresystems GmbH
* (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
*
* This program is free software; you can redistribute it and/or modify
@@ -34,7 +34,7 @@
#include "lib.h"
#define VERSION "v0.9.1"
-#define COPYRIGHT "Copyright (C) 2006-2007 coresystems GmbH"
+#define COPYRIGHT "Copyright (C) 2006-2008 coresystems GmbH"
static int isverbose = 0;
static int iselfparse = 0;
@@ -44,7 +44,7 @@
static void usage(char *name)
{
- printf("\nLAR - the LinuxBIOS Archiver " VERSION "\n" COPYRIGHT "\n\n"
+ printf("\nLAR - the Lightweight Archiver " VERSION "\n" COPYRIGHT "\n\n"
"Usage: %s [-ecxal] archive.lar [[[file1] file2] ...]\n\n", name);
printf("Examples:\n");
printf(" lar -c -s 32k -b bootblock myrom.lar foo nocompress:bar\n");
@@ -267,7 +267,7 @@
isverbose = 1;
break;
case 'V':
- printf("LAR - the LinuxBIOS Archiver " VERSION "\n");
+ printf("LAR - the Lightweight Archiver " VERSION "\n");
break;
default:
usage(argv[0]);
Modified: coreboot-v3/util/lar/lar.h
===================================================================
--- coreboot-v3/util/lar/lar.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/lar/lar.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * lar - LinuxBIOS archiver
+ * lar - lightweight archiver
*
* Copyright (C) 2006 coresystems GmbH
* (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
@@ -61,7 +61,7 @@
typedef uint32_t u32;
typedef uint8_t u8;
-/* NOTE -- This and the linuxbios lar.h may NOT be in sync. Be careful. */
+/* NOTE -- This and the coreboot lar.h may NOT be in sync. Be careful. */
struct lar_header {
char magic[8];
u32 len;
Modified: coreboot-v3/util/lar/lib.c
===================================================================
--- coreboot-v3/util/lar/lib.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/lar/lib.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * lar - LinuxBIOS archiver
+ * lar - lightweight archiver
*
* Copyright (C) 2006-2007 coresystems GmbH
* (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/util/lar/lib.h
===================================================================
--- coreboot-v3/util/lar/lib.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/lar/lib.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * lar - LinuxBIOS archiver
+ * lar - lightweight archiver
*
* Copyright (C) 2006-2007 coresystems GmbH
* (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/util/lar/stream.c
===================================================================
--- coreboot-v3/util/lar/stream.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/lar/stream.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
/*
- * lar - LinuxBIOS archiver
+ * lar - lightweight archiver
*
* This includes code from previous versions of the LAR utility,
* including create.c, list.c, extract.c and bootblock.c
Modified: coreboot-v3/util/lzma/Makefile
===================================================================
--- coreboot-v3/util/lzma/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/lzma/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
##
Modified: coreboot-v3/util/nrv2b/Makefile
===================================================================
--- coreboot-v3/util/nrv2b/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/nrv2b/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/util/options/Makefile
===================================================================
--- coreboot-v3/util/options/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/options/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
Modified: coreboot-v3/util/options/build_opt_tbl.c
===================================================================
--- coreboot-v3/util/options/build_opt_tbl.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/options/build_opt_tbl.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -462,17 +462,17 @@
exit(1);
}
/* And since we are not ready to be fully general purpose yet.. */
- if ((cs->range_start/8) != LB_CKS_RANGE_START) {
+ if ((cs->range_start/8) != CB_CKS_RANGE_START) {
fprintf(stderr, "Error - Range start(%d) does not match define(%d) in line\n%s\n",
- cs->range_start/8, LB_CKS_RANGE_START, line);
+ cs->range_start/8, CB_CKS_RANGE_START, line);
exit(1);
}
- if ((cs->range_end/8) != LB_CKS_RANGE_END) {
+ if ((cs->range_end/8) != CB_CKS_RANGE_END) {
fprintf(stderr, "Error - Range end (%d) does not match define (%d) in line\n%s\n",
- (cs->range_end/8), LB_CKS_RANGE_END, line);
+ (cs->range_end/8), CB_CKS_RANGE_END, line);
exit(1);
}
- if ((cs->location/8) != LB_CKS_LOC) {
+ if ((cs->location/8) != CB_CKS_LOC) {
fprintf(stderr, "Error - Location does not match define in line\n%s\n", line);
exit(1);
}
Modified: coreboot-v3/util/x86emu/Makefile
===================================================================
--- coreboot-v3/util/x86emu/Makefile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/x86emu/Makefile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,5 +1,5 @@
##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
##
Modified: coreboot-v3/util/x86emu/biosemu.c
===================================================================
--- coreboot-v3/util/x86emu/biosemu.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/x86emu/biosemu.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -17,7 +17,7 @@
* it with the version available from LANL.
*/
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* (c) Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
*
Modified: coreboot-v3/util/x86emu/include/x86emu/x86emu.h
===================================================================
--- coreboot-v3/util/x86emu/include/x86emu/x86emu.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/x86emu/include/x86emu/x86emu.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -43,7 +43,7 @@
#define __X86EMU_X86EMU_H
/* FIXME: undefine printk for the moment */
-#ifdef LINUXBIOS_VERSION
+#ifdef COREBOOT_VERSION
#include <console.h>
#define printk(x...) printk(BIOS_DEBUG, x)
#else
Modified: coreboot-v3/util/x86emu/pcbios/pcibios.c
===================================================================
--- coreboot-v3/util/x86emu/pcbios/pcibios.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/x86emu/pcbios/pcibios.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -17,7 +17,7 @@
* it with the version available from LANL.
*/
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* (c) Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
*
Modified: coreboot-v3/util/x86emu/pcbios/pcibios.h
===================================================================
--- coreboot-v3/util/x86emu/pcbios/pcibios.h 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/x86emu/pcbios/pcibios.h 2008-01-27 18:54:57 UTC (rev 564)
@@ -17,7 +17,7 @@
* it with the version available from LANL.
*/
/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* (c) Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
*
Modified: coreboot-v3/util/x86emu/vm86.c
===================================================================
--- coreboot-v3/util/x86emu/vm86.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/x86emu/vm86.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -341,10 +341,10 @@
// that simplifies a lot of things ...
// we'll just push all the registers on the stack as longwords,
// and pop to protected mode.
-// second, since this only ever runs as part of linuxbios,
+// second, since this only ever runs as part of coreboot,
// we know all the segment register values -- so we don't save any.
// keep the handler that calls things small. It can do a call to
-// more complex code in linuxbios itself. This helps a lot as we don't
+// more complex code in coreboot itself. This helps a lot as we don't
// have to do address fixup in this little stub, and calls are absolute
// so the handler is relocatable.
void handler(void)
Modified: coreboot-v3/util/x86emu/x86emu/sys.c
===================================================================
--- coreboot-v3/util/x86emu/x86emu/sys.c 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/x86emu/x86emu/sys.c 2008-01-27 18:54:57 UTC (rev 564)
@@ -45,7 +45,7 @@
#include <x86emu/regs.h>
#include "debug.h"
#include "prim_ops.h"
-#ifdef LINUXBIOS_VERSION
+#ifdef COREBOOT_VERSION
#include "io.h"
#else
#include <sys/io.h>
Modified: coreboot-v3/util/xcompile/xcompile
===================================================================
--- coreboot-v3/util/xcompile/xcompile 2008-01-26 04:07:14 UTC (rev 563)
+++ coreboot-v3/util/xcompile/xcompile 2008-01-27 18:54:57 UTC (rev 564)
@@ -1,6 +1,6 @@
#!/bin/sh
#
-# This file is part of the LinuxBIOS project.
+# This file is part of the coreboot project.
#
# Copyright (C) 2007 coresystems GmbH
# (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
@@ -110,5 +110,5 @@
echo "CFLAGS_x86 := $CFLAGS"
# TODO: The same as above for PowerPC, and other architectures
-# as soon as they are supported by LinuxBIOSv3.
+# as soon as they are supported by coreboot v3.
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