[coreboot] LX RAM I/O delay
peter at stuge.se
Sat Jul 12 17:58:33 CEST 2008
On Fri, Jul 11, 2008 at 08:33:12AM -0700, ron minnich wrote:
> > Does DBE62 have an unterminated memory interface? Can you compare
> > MSR 0x4c00000f from coreboot to a working BIOS? Unterminated
> > platforms are supposed to have a special value (0xF2F100FF
> > 0x56960004) for that register
> That's interesting! The coreboot value is 83:f1:00:aa:56:96:03:44
Decoded those values per page 549-550 of LX_databook.
The coreboot value means:
Half power drive of DQ DQS DQM TLA RAS CAS CKE CS WE MA and BA.
Full SDCLK setup.
DDR read latch enable position set to 1.
SDCLK disabled on SDCLK[1,3,5] outputs.
Output delay for CKE CS RAS CAS WE BA and MA set to 2.
The reference value means:
Full power drive of DQ DQS DQM TLA RAS CAS CKE CS WE MA and BA.
Half SDCLK setup for control signals.
DDR read latch enable position set to 3.
All SDCLK outputs enabled.
Output delay for CKE CS RAS CAS WE BA and MA set to 3.
More information about the coreboot