[coreboot] msrtool

[ron minnich]

On Sat, Jul 12, 2008 at 9:05 PM, ron minnich <rminnich at gmail.com> wrote:
> On Sat, Jul 12, 2008 at 3:36 PM, Tom Sylla <tsylla at gmail.com> wrote:
>> The decode might seem interesting, but this is close to veering down a
>> bad path.
>>
>> You do *not* want to try and futz around with any of those settings. The
>> values in the table (plus the missing one for unterminated) are the only
>> ones you will ever want to use. Thousands of hours of debug and
>> validation time by AMD came up with those numbers. You should not have
>> to "tweak" any of those settings to get something to work. There are
>> comments in the coreboot source to that effect, too.
>
> believe me, I dont' want to mess with them.
>
>>
>> My only reason to point this out is that by decoding it, you are sort of
>> implying that the fields might need to be tweaked.
>
> no. Here's my thinking. It could decode those bits and then say,
> "This is appropriate to an UNTERMINATED bus with ONE row of DIMMS and
> 4 devices. "
> "The DRAM hardware is configured for CL 2.5'
>
> and so on.
>
> I.e. allow people to backtrack from the settings to the hardware and
> see if things make sense. The goals is NOT to tweak the individual
> bits.
>

in fact I'm actually working with a mobo vendor RIGHT NOW to create
this type of 'what are the settings' tool for barcelona so we can
track down a bug. Would that we had it.

Although, really, would that they had listened and done coreboot in
the first place; they're having trouble on a DRAM config problem and
lack of coreboot means it is hard to help them .

In fact, make that *2* vendors I am talking to in this situation; same
problem, different (very different) boards.

ron