[coreboot] [PATCH] Support for the ASI MB-5BLGP (Neoware Eon 4000s)
c-d.hailfinger.devel.2006 at gmx.net
Mon Jul 14 14:06:39 CEST 2008
On 14.07.2008 11:59, Juergen Beisert wrote:
> Hi Carl-Daniel,
> On Montag, 14. Juli 2008, Carl-Daniel Hailfinger wrote:
>> I think I have figured out where to merge your code into the existing
>> Geode LX CAR code.
> The Geode LX lacks these cache test registers! Only the GX1 supports them.
Let me reword this:
We currently perform some early processor init, the switch to protected
mode and other stuff in one big file. The "merge" is more like cutting
out the LX code and replacing it with your cache test code in that file,
then storing the result in a new file.
More information about the coreboot