[coreboot] HT credits and the Opteron

Marc Jones marc.jones at amd.com
Fri Jul 18 01:00:04 CEST 2008

Myles Watson wrote:
>> I assume that you are talking about the XBAR buffer allocation, 4.6.12?
> Sorry. I should have been more clear.  I was talking about 3.3.15: LDTi
> Buffer Count Registers.  Does your answer still apply?
I am looking at the public BKDG Publication # 32559 Revision: 3.08 draft
Issue Date: July 2007.

The LDTi buffers(4.3.15) are part of the XBAR buffers (4.6.10).

"4.3.15 LDTi Buffer Count Registers
These registers specify the number of command and data buffers for each 
virtual channel available for
use by the transmitter at the other end of the specific HyperTransport™ 
technology link. See “XBAR
Flow Control Buffers” on page 156 for more information on command and 
data buffers.
Note: The reset values for each of the LDTn Buffer Count registers 
depend on the link connection
type (coherent HyperTransport or noncoherent HyperTransport technology). 
hardware attempts to choose optimal settings, this register should not, 
in general, need to be
> Now that there is an open-source HT core from the University of Mannheim,
> anyone could do this, but maybe most people will leave it alone.
The core should still be profiled by the designers and recommended 
values documented by them. If none are given than I would assume that it 
is optimized to work with the default settings.


Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com

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