[coreboot] flashrom on gigabyte GA-G33-DS3R : success!
stepan at coresystems.de
Sun Jul 20 13:55:37 CEST 2008
Carl-Daniel Hailfinger wrote:
> On 20.07.2008 02:55, Stefan Reinauer wrote:
>> Carl-Daniel Hailfinger wrote:
>>>> flashrom -c MX25L8005 -w g33ds3r.f7h
>>> That's interesting. This command does write to the chip without erasing
>>> first, so the image you now have in ROM is supposed to be a mixture of
>>> the old and new BIOS.
>> The ichspi driver erases a block prior to writing it, as all the
>> non-spi drivers do. The only behavior that would possibly make sense
>> from a user perspective.
> Ah yes. I forgot about the silent data corruption bug in the ICH SPI
> driver. It works most of the time, but there are quite a few chips
> listed in flashchips.c which will act weird or require a separate erase
In fact, my experience was the other way around. The seperate erase
command does not work for most of the chips in the list on ICH7.
What ICH did you make this experience on?
> Besides that, the block erase code does not belong in the chipset
> driver, it belongs in the flash chip driver.
I guess you are right. Patches, someone?
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