[coreboot] alix1c PATA

ron minnich rminnich at gmail.com
Mon May 5 19:01:11 CEST 2008

You mean this I suppose?

#define IDE_CFG	  0x40
	#define CHANEN  (1L <<  1)
	#define PWB	(1L << 14)
	#define CABLE	(1L << 16)
#define IDE_DTC	  0x48
#define IDE_CAST  0x4C
#define IDE_ETC	  0x50

static void ide_init(struct device *dev)
	uint32_t ide_cfg;

	printk_spew("cs5536_ide: %s\n", __FUNCTION__);
	/* GPIO and IRQ setup are handled in the main chipset code. */

	// Enable the channel and Post Write Buffer
	// NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set
	ide_cfg = pci_read_config32(dev, IDE_CFG);
	ide_cfg |= CHANEN | PWB;
	pci_write_config8(dev, IDE_CFG, ide_cfg);

That code is there in v3.

It depends on this:
	if (sb->enable_ide)

but that's there too:
mainboard/artecgroup/dbe62/dts:                 enable_ide = "1";
mainboard/pcengines/alix1c/dts:                 enable_ide = "1";

I'm not near a board. Do you see this message:
	printk(BIOS_DEBUG, "cs5536_ide: %s\n", __func__);


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