[coreboot] patch: two bugs in the cs5536 ide code
c-d.hailfinger.devel.2006 at gmx.net
Tue May 6 14:15:44 CEST 2008
On 06.05.2008 07:54, ron minnich wrote:
> I know some people will get upset by the find_pci_device, but:
Indeed. Since we don't use the struct device passed in to ide_init, why
don't we give Geode IDE its own struct device_operations and store the
IDE config there?
> This patch fixes a long-standing problem in the cs5536 driver, that is
> probably also in v2.
> The ide_init is called with the sb device but needs the IDE device,
> which is different.
> It also did a write_config8,not write_config32; this bug has been in there since
> the code was written for v2. I don't know how or why it ever worked,
> since PWB is 1<<14.
> Works fine with 2.6.24. 2.6.15 hangs on boot, but I don't think it was
> ever IDE. POST on the 2.6.25 boot hang is 00.
I have problems parsing the sentence above: "... I don't think it was
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
> Index: southbridge/amd/cs5536/cs5536.c
> --- southbridge/amd/cs5536/cs5536.c (revision 676)
> +++ southbridge/amd/cs5536/cs5536.c (working copy)
> @@ -589,15 +589,18 @@
> static void ide_init(struct device *dev)
> u32 ide_cfg;
> + struct device *ide_dev;
> printk(BIOS_DEBUG, "cs5536_ide: %s\n", __func__);
> /* GPIO and IRQ setup are handled in the main chipset code. */
> + ide_dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
> + PCI_DEVICE_ID_AMD_CS5536_B0_IDE, 0);
> // Enable the channel and Post Write Buffer
> // NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set
> - ide_cfg = pci_read_config32(dev, IDE_CFG);
> + ide_cfg = pci_read_config32(ide_dev, IDE_CFG);
> ide_cfg |= CHANEN | PWB;
> - pci_write_config8(dev, IDE_CFG, ide_cfg);
> + pci_write_config32(ide_dev, IDE_CFG, ide_cfg);
You know my preference for killing dev_find_pci_device, but that can
come later if it is too difficult.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
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