[coreboot] proposed patch, notsigned off, comments welcome.

Peter Stuge peter at stuge.se
Mon May 12 18:38:19 CEST 2008

On Mon, May 12, 2008 at 08:51:53AM -0700, ron minnich wrote:
> INTC, GPIO pin 12
> Input Enabled and Inverted
> Interrupt:IG 0
> INTD, GPIO pin 13
> Input Enabled and Inverted
> Interrupt:IG 0

IG 0 means that the interrupt source is disabled. Try setting that
mapping to the same two numbers you've specified in the PIR table for

I think things will start working automagically if you write directly
to that mapping MSR.

You can also try writing to VR 0x5d, but that's the same code as I
suppose has run at least once already when coreboot wrote to 0x5d.

Strange that the mapping is not set. Does coreboot in fact write to
0x5d? It does seem so since inputs are not enabled by default.

Oh, wait. I just discovered something i VSA sysmgr/mapper.h:

Z_IRQ_INTA..D are always set to 9..12.

This means that external PCI interrupts will always trigger 9..12,
and if 5536 modules are supposed to share the same lines then all LX
PIR tables must also use 9..12.

As far as I can see, the SYS_MAP_IRQ call in legacy/cs5536.c
PCI_Interrupt_Steering() will always change only the YLOW mapping MSR.
Strange. I think I need to look through VSA another few hours.

There simply seems to be no call to IRQZ_Mapper in VSA that will set
up interrupt mapping for the GPIOs, but obviously something is set up
for two of the GPIO interrupts.

What about GPIO Mapper Y and Z (E4 or thereabout) and PIC mapping for
Unrestricted inputs 8..15? (PIC MSR 23h)


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