[coreboot] proposed patch, notsigned off, comments welcome.

ron minnich rminnich at gmail.com
Tue May 13 06:49:13 CEST 2008

Enough for one night. I'm also checking 51400024 for mask in this pass.

So, it's all wired right, eth0 works fine as it is swizzled to INTB,
and it behaves as expected and as this program says it should. what
doesn't work is PCI 3v slot to INTS C or D. And, they're shared with
USB, and I'm convinced that's part of it.

But maybe somebody out there can see it; I can not yet.

Code attached; hack away.


input enable 0f7af085 invert 0xcf7e3081
irqmap from vr is 0xd0c0700
4d1:4d0 0e00
GPIOmap (e0 to e8): 0/20000001 4/08051538 8/14000e00 12/00000000
GPIO0: Interrupt:IG 1
GPIO7: Interrupt:IG 2
GPIO12: Interrupt:IG 3
GPIO13: Interrupt:IG 4
MSR 0x51400023: 0x9bab2

MSR 0x51400024: 0xffff

INTA, GPIO pin 0;Input Enabled and Inverted,Interrupt:GPIO BIT 1,IG
11,Not masked,
INTB, GPIO pin 7;Input Enabled and Inverted,Interrupt:GPIO BIT 2,IG
10,Not masked,
INTC, GPIO pin 12;Input Enabled and Inverted,Interrupt:GPIO BIT 3,IG
11,Not masked,
INTD, GPIO pin 13;Input Enabled and Inverted,Interrupt:GPIO BIT 4,IG
9,Not masked,
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