[coreboot] epia-cn patch

[Peter Stuge]

Hi Aaron,

On Tue, May 13, 2008 at 05:40:43PM +0800, aaron lwe wrote:
> This is a working patch for epia-cn which uses C7 + CN700 + VT8237R.
> Signed-off-by: Aaron Lwe <aaron.lwe at gmail.com>

Cool!


> Index: src/mainboard/via/epia-cn/dsdt.c
> ===================================================================
> --- src/mainboard/via/epia-cn/dsdt.c	(revision 0)
> +++ src/mainboard/via/epia-cn/dsdt.c	(revision 0)
> @@ -0,0 +1,2487 @@
> +/*
> + * 
> + * Intel ACPI Component Architecture
> + * ASL Optimizing Compiler version 20061109 [Aug 11 2007]
> + * Copyright (C) 2000 - 2006 Intel Corporation
> + * Supports ACPI Specification Revision 3.0a
> + * 
> + * Compilation of "dsdt.dsl" - Mon Jan 28 11:04:07 2008
> + * 
> + * C source code output
> + *
> + */

Do you have the dsdt.dsl source? Where did it come from?


> Index: src/mainboard/via/epia-cn/fadt.c
> ===================================================================
> --- src/mainboard/via/epia-cn/fadt.c	(revision 0)
> +++ src/mainboard/via/epia-cn/fadt.c	(revision 0)
> @@ -0,0 +1,154 @@
> +/*
> + * ACPI - create the Fixed ACPI Description Tables (FADT)
> + * Copyright (C) 2004 Nick Barker <nick.barker9 at btinternet.com>

Did you change anything in this file? Then I think you should add
your copyright, possibly even remove Nick's.


> +void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
> +	acpi_header_t *header=&(fadt->header);
> +
> +	memset((void *)fadt,0,sizeof(acpi_fadt_t));
> +	memcpy(header->signature,"FACP",4);
> +	header->length = 244;
> +	header->revision = 1;
> +	memcpy(header->oem_id,"CN700 ",6);
> +	memcpy(header->oem_table_id,"AWRDACPI",8);
> +	memcpy(header->asl_compiler_id,"AWRD",4);

We are not Award. What is this about?


> +	header->asl_compiler_revision=0;
> +
> +	fadt->firmware_ctrl=facs;
> +	fadt->dsdt= dsdt;
> +	fadt->preferred_pm_profile=0;
> +	fadt->sci_int=9;
> +	fadt->smi_cmd = 0x0;
> +	fadt->acpi_enable = 0x0;
> +	fadt->acpi_disable = 0x0;
> +	fadt->s4bios_req = 0x0;
> +	fadt->pstate_cnt = 0x0;
> +
> +	fadt->pm1a_evt_blk = 0x400;
> +	fadt->pm1b_evt_blk = 0x0;
> +	fadt->pm1a_cnt_blk = 0x404;
> +	fadt->pm1b_cnt_blk = 0x0;
> +	fadt->pm2_cnt_blk = 0x0;
> +	fadt->pm_tmr_blk = 0x408;
> +	fadt->gpe0_blk = 0x420;
> +	fadt->gpe1_blk = 0x0;

Where do all these magic values come from?


> -/**
> - * Configure the bus between the cpu and the northbridge. This might be able to 
> - * be moved to post-ram code in the future. For the most part, these registers
> - * should not be messed around with. These are too complex to explain short of
> - * copying the datasheets into the comments, but most of these values are from
> - * the BIOS Porting Guide, so they should work on any board. If they don't,
> - * try the values from your factory BIOS.
> - *
> - * TODO: Changing the DRAM frequency doesn't work (hard lockup)
> - *
> - * @param dev The northbridge's CPU Host Interface (D0F2)
> - */
>  static void c7_cpu_setup(device_t dev)
>  {

Hey, please don't remove doxygen. :)


> Index: src/northbridge/via/cn700/northbridge.c
> ===================================================================
> --- src/northbridge/via/cn700/northbridge.c	(revision 3300)
> +++ src/northbridge/via/cn700/northbridge.c	(working copy)
> @@ -1,6 +1,8 @@
>  /*
>   * This file is part of the coreboot project.
>   *
> + * Copyright (C) 2008 VIA Technologies, Inc.
> + * Copyright (C) 2008 Aaron Lwe <aaron.lwe at gmail.com>

How is VIA involved in this?


Thanks a lot for the patch! I guess Corey and Bari will have a go at
it but I'll try to test as well.


//Peter