[coreboot] r3321 - trunk/util/flashrom

svn at coreboot.org svn at coreboot.org
Thu May 15 05:24:43 CEST 2008


Author: hailfinger
Date: 2008-05-15 05:24:43 +0200 (Thu, 15 May 2008)
New Revision: 3321

Modified:
   trunk/util/flashrom/flash.h
   trunk/util/flashrom/flashchips.c
Log:
Lots of new SST flash chip IDs. Only a subset has been added to
flashchips.c, but the IDs in flash.h will make lookups easier if anybody
wants to add support for them.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/util/flashrom/flash.h
===================================================================
--- trunk/util/flashrom/flash.h	2008-05-15 03:19:49 UTC (rev 3320)
+++ trunk/util/flashrom/flash.h	2008-05-15 03:24:43 UTC (rev 3321)
@@ -237,8 +237,21 @@
 #define SST_25VF032B		0x254A
 #define SST_25VF040B		0x258D
 #define SST_25VF080B		0x258E
+#define SST_27SF512		0xA4
+#define SST_27SF010		0xA5
+#define SST_27SF020		0xA6
+#define SST_27VF010		0xA9
+#define SST_27VF020		0xAA
+#define SST_28SF040		0x04
+#define SST_29EE512		0x5D
+#define SST_29EE010		0x07
+#define SST_29LE010		0x08	/* also SST29VE010 */
 #define SST_29EE020A		0x10
-#define SST_28SF040		0x04
+#define SST_29LE020		0x12	/* also SST29VE020 */
+#define SST_29SF020		0x24
+#define SST_29VF020		0x25
+#define SST_29SF040		0x13
+#define SST_29VF040		0x14
 #define SST_39SF010		0xB5
 #define SST_39SF020		0xB6
 #define SST_39SF040		0xB7

Modified: trunk/util/flashrom/flashchips.c
===================================================================
--- trunk/util/flashrom/flashchips.c	2008-05-15 03:19:49 UTC (rev 3320)
+++ trunk/util/flashrom/flashchips.c	2008-05-15 03:24:43 UTC (rev 3321)
@@ -70,7 +70,10 @@
 	{"SST",		"SST25VF016B",		SST_ID,		SST_25VF016B,		2048,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
 	{"SST",		"SST25VF040B",		SST_ID,		SST_25VF040B,		512,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
 	{"SST",		"SST28SF040A",		SST_ID,		SST_28SF040,		512,	256,		TEST_UNTESTED,	probe_28sf040,		erase_28sf040,			write_28sf040},
+	{"SST",		"SST29EE010",		SST_ID,		SST_29EE010,		128,	128,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
+	{"SST",		"SST29LE010",		SST_ID,		SST_29LE010,		128,	128,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec, 		write_jedec},
 	{"SST",		"SST29EE020A",		SST_ID,		SST_29EE020A,		256,	128,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
+	{"SST",		"SST29LE020",		SST_ID,		SST_29LE020,		256,	128,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
 	{"SST",		"SST39SF010A",		SST_ID,		SST_39SF010,		128,	4096,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_39sf020},
 	{"SST",		"SST39SF020A",		SST_ID,		SST_39SF020,		256,	4096,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_39sf020},
 	{"SST",		"SST39SF040",		SST_ID,		SST_39SF040,		512,	4096,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_39sf020},





More information about the coreboot mailing list