[coreboot] v2[PATCH] Initial support for the Thomson IP1000
Joseph Smith
joe at settoplinux.org
Fri May 16 04:23:48 CEST 2008
Hello,
Here is a patch to add initial support for the Thomson IP1000. It is a
cousin to the RCA RM4100. More info on it can be found here:
http://www.settoplinux.org/index.php?title=Thomson_IP1000
Also attached is a coreboot bootlog with full debugging.
Signed-off-by: Joseph Smith <joe at settoplinux.org>
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
-------------- next part --------------
Index: src/mainboard/thomson/ip1000/gpio.c
===================================================================
--- src/mainboard/thomson/ip1000/gpio.c (revision 0)
+++ src/mainboard/thomson/ip1000/gpio.c (revision 0)
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define PME_DEV PNP_DEV(0x2e, 0x0a)
+#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
+#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
+
+/* Early mainboard specific GPIO setup. */
+static void mb_gpio_init(void)
+{
+ device_t dev;
+ uint16_t port;
+ uint32_t set_gpio;
+
+ /* Southbridge GPIOs. */
+ /* Set the LPC device statically. */
+ dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+ /* Set the value for GPIO base address register and enable GPIO. */
+ pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
+ pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
+
+ /* Set GPIO25 to input and drive GPIO23 to high,
+ * this enables the LAN controller.
+ */
+ udelay(10);
+ set_gpio = 0x0000ffff;
+ set_gpio |= 1 << 25;
+ outl(set_gpio, ICH_IO_BASE_ADDR + 0x04);
+
+ set_gpio = 0x1b3f0000;
+ set_gpio |= 1 << 23;
+ outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
+
+ /* Super I/O GPIOs. */
+ dev = PME_DEV;
+ port = dev >> 8;
+
+ outb(0x55, port); /* Enter the configuration state. */
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
+ pnp_set_enable(dev, 1);
+ outl(0x03, PME_IO_BASE_ADDR + 0x1e); /* Force Disk Change */
+ outl(0x02, PME_IO_BASE_ADDR + 0x1f); /* Floppy Data Rate */
+ outl(0x81, PME_IO_BASE_ADDR + 0x20); /* UART1 FIFO */
+ outl(0x81, PME_IO_BASE_ADDR + 0x21); /* UART2 FIFO */
+ outl(0x00, PME_IO_BASE_ADDR + 0x22); /* Device Disable */
+ outl(0x01, PME_IO_BASE_ADDR + 0x23); /* GP10 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x24); /* GP11 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x25); /* GP12 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x26); /* GP13 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x27); /* GP14 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x28); /* GP15 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x29); /* GP16 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x2a); /* GP17 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x2b); /* GP20 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x2c); /* GP21 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x2d); /* GP22 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x2f); /* GP24 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x30); /* GP25 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x31); /* GP26 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x32); /* GP27 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP30 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP31 */
+ outl(0x84, PME_IO_BASE_ADDR + 0x35); /* GP32 */
+ outl(0x84, PME_IO_BASE_ADDR + 0x36); /* GP33 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x37); /* GP34 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x38); /* GP35 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x39); /* GP36 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x3a); /* GP37 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x3b); /* GP40 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x3c); /* GP41 */
+ outl(0x86, PME_IO_BASE_ADDR + 0x3d); /* GP42 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x3e); /* GP43 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x3f); /* GP50 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x40); /* GP51 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x41); /* GP52 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x42); /* GP53 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x43); /* GP54 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x44); /* GP55 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x45); /* GP56 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x46); /* GP57 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x47); /* GP58 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x48); /* GP59 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x4b); /* GP1 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x4c); /* GP2 */
+ outl(0xc0, PME_IO_BASE_ADDR + 0x4d); /* GP3 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x4e); /* GP4 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x4f); /* GP5 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x50); /* GP6 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x56); /* FAN1 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x57); /* FAN2 */
+ outl(0x58, PME_IO_BASE_ADDR + 0x58); /* Fan Control */
+ outl(0xff, PME_IO_BASE_ADDR + 0x59); /* Fan1 Tachometer */
+ outl(0x50, PME_IO_BASE_ADDR + 0x5a); /* Fan2 Tachometer */
+ outl(0x00, PME_IO_BASE_ADDR + 0x5b); /* Fan1 Preload */
+ outl(0x00, PME_IO_BASE_ADDR + 0x5c); /* Fan2 Preload */
+ outl(0x00, PME_IO_BASE_ADDR + 0x5d); /* LED1 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x5e); /* LED2 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x5f); /* Keyboard Scan Code */
+ outb(0xaa, port); /* Exit the configuration state. */
+}
Index: src/mainboard/thomson/ip1000/Config.lb
===================================================================
--- src/mainboard/thomson/ip1000/Config.lb (revision 0)
+++ src/mainboard/thomson/ip1000/Config.lb (revision 0)
@@ -0,0 +1,145 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
+else
+ default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
+ default ROM_SECTION_OFFSET = 0
+end
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
+default XIP_ROM_SIZE = 65536
+default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+arch i386 end
+driver mainboard.o
+if HAVE_PIRQ_TABLE object irq_tables.o end
+# object reset.o
+if HAVE_ACPI_TABLES
+ object fadt.o
+ object dsdt.o
+ object acpi_tables.o
+end
+makerule ./failover.E
+ depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./failover.inc
+ depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./auto.E
+ # depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ depends "$(MAINBOARD)/auto.c ./romcc"
+ action "./romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+ # depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ depends "$(MAINBOARD)/auto.c ./romcc"
+ action "./romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+mainboardinit arch/i386/lib/cpu_reset.inc
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+if USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+end
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+dir /pc80
+config chip.h
+
+chip northbridge/intel/i82830 # Northbridge
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ chip drivers/pci/onboard # Onboard VGA
+ device pci 2.0 on end # VGA (Intel 82830 CGC)
+ register "rom_address" = "0xfff00000"
+ end
+ chip southbridge/intel/i82801xx # Southbridge
+ device pci 1d.0 on end # USB UHCI Controller #1
+ device pci 1d.1 on end # USB UHCI Controller #2
+ device pci 1d.2 on end # USB UHCI Controller #3
+ device pci 1d.7 on end # USB2 EHCI Controller
+ device pci 1e.0 on # PCI bridge
+ device pci 08.0 on end # Intel 82801DB PRO/100 VE Ethernet
+ end
+ device pci 1f.0 on # ISA/LPC bridge
+ chip superio/smsc/smscsuperio # Super I/O
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 4
+ end
+ device pnp 2e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 on # Com2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.7 on # PS/2 keyboard/mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # Keyboard interrupt
+ irq 0x72 = 12 # Mouse interrupt
+ end
+ device pnp 2e.9 off end # Game port
+ device pnp 2e.a on # PME
+ io 0x60 = 0x800
+ end
+ device pnp 2e.b off end # MPU-401
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 on end # AC'97 audio
+ device pci 1f.6 off end # AC'97 modem
+ end
+ end
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_PGA370 # Low Voltage PIII Micro-FCBGA Socket 479
+ device apic 0 on end # APIC
+ end
+ end
+end
+
Index: src/mainboard/thomson/ip1000/spd_table.h
===================================================================
--- src/mainboard/thomson/ip1000/spd_table.h (revision 0)
+++ src/mainboard/thomson/ip1000/spd_table.h (revision 0)
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <spd.h>
+
+struct spd_entry {
+ unsigned int address;
+ unsigned int data;
+};
+
+/*
+ * The onboard 64MB PC133 memory does not have an SPD EEPROM so the values
+ * have to be set manually, the onboard memory is located in socket1 (0x51).
+ */
+const struct spd_entry spd_table [] = {
+ {SPD_MEMORY_TYPE, 0x04}, /* (Fundamental) memory type */
+ {SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */
+ {SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */
+ {SPD_MODULE_DATA_WIDTH_LSB, 0x40}, /* Module data width (LSB) */
+ {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
+ {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */
+ {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x10}, /* Density of each row on module */
+};
Index: src/mainboard/thomson/ip1000/irq_tables.c
===================================================================
--- src/mainboard/thomson/ip1000/irq_tables.c (revision 0)
+++ src/mainboard/thomson/ip1000/irq_tables.c (revision 0)
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x24c0, /* Device */
+ 0, /* Crap (miniport) */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xcd, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] VGA compatible controller */
+ {0x00,(0x1d<<3)|0x0, {{0x60, 0x1ef8}, {0x63, 0x1ef8}, {0x62, 0x1ef8}, {0x6b, 0x01ef8}}, 0x0, 0x0}, /* [D] USB2 EHCI Controller */
+ {0x00,(0x1f<<3)|0x0, {{0x62, 0x1ef8}, {0x61, 0x1ef8}, {0x6b, 0x1ef8}, {0x63, 0x01ef8}}, 0x0, 0x0}, /* [A] IDE Controller */
+ {0x01,(0x08<<3)|0x0, {{0x68, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] Ethernet controller */
+ {0x01,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x01ef8}}, 0x1, 0x0}, /* [A] USB UHCI Controller #1 */
+ {0x01,(0x01<<3)|0x0, {{0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x01ef8}}, 0x2, 0x0}, /* [B] USB UHCI Controller #2 */
+ {0x01,(0x02<<3)|0x0, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x01ef8}}, 0x3, 0x0}, /* [C] USB UHCI Controller #3 */
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
Index: src/mainboard/thomson/ip1000/Options.lb
===================================================================
--- src/mainboard/thomson/ip1000/Options.lb (revision 0)
+++ src/mainboard/thomson/ip1000/Options.lb (revision 0)
@@ -0,0 +1,95 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+uses CC
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_IOAPIC
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses CONFIG_UDELAY_TSC
+uses CONFIG_VIDEO_MB
+uses CROSS_COMPILE
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses FALLBACK_SIZE
+uses HAVE_ACPI_TABLES
+uses HAVE_FALLBACK_BOOT
+uses HAVE_MP_TABLE
+uses HAVE_OPTION_TABLE
+uses HAVE_PIRQ_TABLE
+uses HEAP_SIZE
+uses HOSTCC
+uses IRQ_SLOT_COUNT
+uses COREBOOT_EXTRA_VERSION
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses OBJCOPY
+uses PAYLOAD_SIZE
+uses _RAMBASE
+uses _ROMBASE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses ROM_SIZE
+uses STACK_SIZE
+uses TTYS0_BASE
+uses TTYS0_BAUD
+uses TTYS0_LCS
+uses USE_FALLBACK_IMAGE
+uses USE_OPTION_TABLE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+
+default ROM_SIZE = 512 * 1024
+default ROM_IMAGE_SIZE = 128 * 1024
+default HAVE_FALLBACK_BOOT = 1
+default FALLBACK_SIZE = 256 * 1024
+default CONFIG_UDELAY_TSC = 1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
+default HAVE_PIRQ_TABLE = 1
+default IRQ_SLOT_COUNT = 7
+default HAVE_MP_TABLE = 0
+default HAVE_ACPI_TABLES = 0
+default CONFIG_IOAPIC = 0
+default HAVE_OPTION_TABLE = 0
+default CONFIG_CONSOLE_VGA = 0
+default CONFIG_PCI_ROM_RUN = 0
+default CONFIG_VIDEO_MB = 0
+default STACK_SIZE = 0x2000
+default HEAP_SIZE = 0x4000
+default _RAMBASE = 0x00004000
+default USE_OPTION_TABLE = 0
+default CONFIG_ROM_PAYLOAD = 1
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+default CONFIG_CONSOLE_SERIAL8250 = 1
+default TTYS0_BAUD = 115200
+default TTYS0_BASE = 0x3f8
+default TTYS0_LCS = 0x3 # 8n1
+default DEFAULT_CONSOLE_LOGLEVEL = 9
+default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default MAINBOARD_VENDOR = "THOMSON"
+default MAINBOARD_PART_NUMBER = "IP1000"
+end
Index: src/mainboard/thomson/ip1000/chip.h
===================================================================
--- src/mainboard/thomson/ip1000/chip.h (revision 0)
+++ src/mainboard/thomson/ip1000/chip.h (revision 0)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_thomson_ip1000_ops;
+
+struct mainboard_thomson_ip1000_config {
+ int nothing;
+};
Index: src/mainboard/thomson/ip1000/auto.c
===================================================================
--- src/mainboard/thomson/ip1000/auto.c (revision 0)
+++ src/mainboard/thomson/ip1000/auto.c (revision 0)
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "pc80/udelay_io.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "northbridge/intel/i82830/raminit.h"
+#include "northbridge/intel/i82830/memory_initialized.c"
+#include "southbridge/intel/i82801xx/i82801xx.h"
+#include "southbridge/intel/i82801xx/i82801xx_reset.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "spd_table.h"
+#include "gpio.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+
+#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
+#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"
+
+/**
+ * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
+ * values have to be set manually, the SO-DIMM socket is located in
+ * socket0 (0x50), and the onboard memory is located in socket1 (0x51).
+ */
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ int i;
+
+ if (device == 0x50) {
+ return smbus_read_byte(device, address);
+ } else if (device == 0x51) {
+ for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
+ if (spd_table[i].address == address)
+ return spd_table[i].data;
+ }
+ return 0xFF; /* Return 0xFF when address is not found. */
+ } else {
+ return 0xFF; /* Return 0xFF on any failures. */
+ }
+}
+
+#include "northbridge/intel/i82830/raminit.c"
+#include "sdram/generic_sdram.c"
+
+/**
+ * The AC'97 Audio Controller I/O space registers are read only by default
+ * so we need to enable them by setting register 0x41 to 0x01.
+ */
+static void ac97_io_enable(void)
+{
+ device_t dev;
+
+ /* Set the ac97 audio device staticly. */
+ dev = PCI_DEV(0x0, 0x1f, 0x5);
+
+ /* Enable access to the IO space. */
+ pci_write_config8(dev, 0x41, 0x01);
+}
+
+static void main(unsigned long bist)
+{
+ static const struct mem_controller memctrl[] = {
+ {
+ .d0 = PCI_DEV(0, 0, 0),
+ .channel0 = {0x50, 0x51},
+ }
+ };
+
+ if (bist == 0)
+ early_mtrr_init();
+ if (memory_initialized()) {
+ hard_reset();
+ }
+
+ enable_smbus();
+
+ smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ mb_gpio_init();
+ uart_init();
+ console_init();
+
+ /* Prevent the TCO timer from rebooting us */
+ i82801xx_halt_tco_timer();
+
+ /* Halt if there was a built in self test failure. */
+ report_bist_failure(bist);
+
+ sdram_set_registers(memctrl);
+ sdram_set_spd_registers(memctrl);
+ sdram_enable(0, memctrl);
+
+ /* Check RAM. */
+ /* ram_check(0, 640 * 1024); */
+ /* ram_check(64512 * 1024, 65536 * 1024); */
+
+ ac97_io_enable();
+}
Property changes on: src/mainboard/thomson/ip1000/auto.c
___________________________________________________________________
Name: svn:executable
+ *
Index: src/mainboard/thomson/ip1000/mainboard.c
===================================================================
--- src/mainboard/thomson/ip1000/mainboard.c (revision 0)
+++ src/mainboard/thomson/ip1000/mainboard.c (revision 0)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_thomson_ip1000_ops = {
+ CHIP_NAME("THOMSON IP1000 Mainboard")
+};
Index: targets/thomson/ip1000/Config-abuild.lb
===================================================================
--- targets/thomson/ip1000/Config-abuild.lb (revision 0)
+++ targets/thomson/ip1000/Config-abuild.lb (revision 0)
@@ -0,0 +1,30 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+target thomson_ip1000
+mainboard thomson/ip1000
+
+romimage "fallback"
+ option USE_FALLBACK_IMAGE = 1
+ payload __PAYLOAD__
+end
+
+buildrom ./coreboot.rom ROM_SIZE "fallback"
+
Index: targets/thomson/ip1000/Config.lb
===================================================================
--- targets/thomson/ip1000/Config.lb (revision 0)
+++ targets/thomson/ip1000/Config.lb (revision 0)
@@ -0,0 +1,63 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+target ip1000
+mainboard thomson/ip1000
+
+##
+## Total number of bytes allocated for coreboot use
+## (fallback images and payloads).
+##
+# option ROM_SIZE = 1024 * 1024
+## For VGA BIOS (-64k)
+option ROM_SIZE = (1024 * 1024) - (64 * 1024)
+
+##
+## VGA Console
+## NOTE: to initialize VGA, you need to copy
+## the VGA option ROM from the factory BIOS
+## 0=disable 1=enable
+##
+option CONFIG_CONSOLE_VGA = 1
+option CONFIG_PCI_ROM_RUN = 1
+
+##
+## Choose the amount of memory pre-allocated for VGA
+## 0 for No memory pre-allocated (Graphics memory Disabled)
+## 512 for DVMT (UMA) mode, 512K of memory pre-allocated for frame buffer
+## 1 for DVMT (UMA) mode, 1M of memory pre-allocated for frame buffer
+## 8 for DVMT (UMA) mode, 8M of memory pre-allocated for frame buffer
+##
+option CONFIG_VIDEO_MB = 8
+
+##
+## Request this level of debugging output
+##
+option DEFAULT_CONSOLE_LOGLEVEL = 7
+
+romimage "fallback"
+ option USE_FALLBACK_IMAGE = 1
+ option FALLBACK_SIZE = ROM_SIZE
+ option COREBOOT_EXTRA_VERSION = "_IP1000"
+ payload /tmp/filo.elf
+# payload /tmp/eb-5.4.3-eepro100.elf
+end
+
+buildrom ./coreboot.rom ROM_SIZE "fallback"
-------------- next part --------------
coreboot-2.0.0_RM4100 Wed May 14 19:50:46 EDT 2008 starting...
Setting initial registers....
Initial registers have been set.
No DIMM found in slot 00
DRB 0x60 has been set to 0x00
DRB1 0x61 has been set to 0x00
Found DIMM in slot 01
DIMM is 0x0040 on side 1
DIMM is 0x0000 on side 2
DRB2 0x62 has been set to 0x02
DRB3 0x63 has been set to 0x02
No DIMM found in slot 00, setting DRA to 0xFF
DRA 0x70 has been set to 0xff
Found DIMM in slot 01, setting DRA...
DRA 0x71 has been set to 0xf1
RAM Enable 1: Apply NOP
Sending RAM command 0x00000010 to 0x00000000
RAM Enable 2: Precharge all
Sending RAM command 0x00000020 to 0x00000000
RAM Enable 3: CBR
Sending RAM command 0x00000060 to 0x00000000
Sending RAM command 0x00000060 to 0x00000000
Sending RAM command 0x00000060 to 0x00000000
Sending RAM command 0x00000060 to 0x00000000
Sending RAM command 0x00000060 to 0x00000000
Sending RAM command 0x00000060 to 0x00000000
Sending RAM command 0x00000060 to 0x00000000
Sending RAM command 0x00000060 to 0x00000000
RAM Enable 4: Mode register set
Sending RAM command 0x00000030 to 0x000001d0
RAM Enable 5: Normal operation
Sending RAM command 0x20000270 to 0x00000000
Northbridge following SDRAM init:
PCI: 00:00.00
00: 86 80 75 35 06 00 10 20 04 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e
50: 72 a0 40 00 00 00 00 00 00 30 33 33 33 33 33 33
60: 00 00 02 02 02 02 00 00 00 00 00 00 00 00 00 00
70: ff f1 ff ff 00 00 00 00 10 00 00 00 70 02 00 20
80: 00 00 00 00 00 00 00 00 80 60 33 0b 00 00 00 00
90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 1b 49 9b fc
f0: 11 11 01 00 00 00 0b 05 35 d0 2c d0 21 cd 1d cc
Copying coreboot to RAM.
Jumping to coreboot.
coreboot-2.0.0_RM4100 Wed May 14 19:50:46 EDT 2008 booting...
end 85599ec0, start 0
32-bit delta 1826
calibrate_tsc 32-bit result is 1826
clocks_per_usec: 1826
Enumerating buses...
scan_static_bus for Root Device
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/3575] ops
PCI: 00:00.0 [8086/3575] enabled
PCI: devfn 0x8, bad id 0xffffffff
PCI: 00:02.0 [8086/3577] enabled
PCI: devfn 0x18, bad id 0xffffffff
PCI: devfn 0x20, bad id 0xffffffff
PCI: devfn 0x28, bad id 0xffffffff
PCI: devfn 0x30, bad id 0xffffffff
PCI: devfn 0x38, bad id 0xffffffff
PCI: devfn 0x40, bad id 0xffffffff
PCI: devfn 0x48, bad id 0xffffffff
PCI: devfn 0x50, bad id 0xffffffff
PCI: devfn 0x58, bad id 0xffffffff
PCI: devfn 0x60, bad id 0xffffffff
PCI: devfn 0x68, bad id 0xffffffff
PCI: devfn 0x70, bad id 0xffffffff
PCI: devfn 0x78, bad id 0xffffffff
PCI: devfn 0x80, bad id 0xffffffff
PCI: devfn 0x88, bad id 0xffffffff
PCI: devfn 0x90, bad id 0xffffffff
PCI: devfn 0x98, bad id 0xffffffff
PCI: devfn 0xa0, bad id 0xffffffff
PCI: devfn 0xa8, bad id 0xffffffff
PCI: devfn 0xb0, bad id 0xffffffff
PCI: devfn 0xb8, bad id 0xffffffff
PCI: devfn 0xc0, bad id 0xffffffff
PCI: devfn 0xc8, bad id 0xffffffff
PCI: devfn 0xd0, bad id 0xffffffff
PCI: devfn 0xd8, bad id 0xffffffff
PCI: devfn 0xe0, bad id 0xffffffff
PCI: 00:1d.0 [8086/24c2] ops
PCI: 00:1d.0 [8086/24c2] enabled
PCI: 00:1d.1 [8086/24c4] ops
PCI: 00:1d.1 [8086/24c4] enabled
PCI: 00:1d.2 [8086/24c7] ops
PCI: 00:1d.2 [8086/24c7] enabled
PCI: devfn 0xeb, bad id 0xffffffff
PCI: devfn 0xec, bad id 0xffffffff
PCI: devfn 0xed, bad id 0xffffffff
PCI: devfn 0xee, bad id 0xffffffff
PCI: 00:1d.7 [8086/24cd] ops
PCI: 00:1d.7 [8086/24cd] enabled
PCI: 00:1e.0 [8086/244e] bus ops
PCI: 00:1e.0 [8086/244e] enabled
PCI: 00:1f.0 [8086/24c0] bus ops
PCI: 00:1f.0 [8086/24c0] enabled
PCI: 00:1f.1 [8086/24cb] ops
PCI: 00:1f.1 [8086/24cb] enabled
PCI: devfn 0xfa, bad id 0xffffffff
PCI: 00:1f.3 [8086/24c3] enabled
PCI: devfn 0xfc, bad id 0xffffffff
PCI: 00:1f.5 [8086/24c5] ops
PCI: 00:1f.5 [8086/24c5] enabled
PCI: 00:1f.6 [8086/24c6] ops
PCI: 00:1f.6 [8086/24c6] enabled
PCI: devfn 0xff, bad id 0xffffffff
do_pci_scan_bridge for PCI: 00:1e.0
PCI: pci_scan_bus for bus 01
PCI: devfn 0x0, bad id 0xffffffff
PCI: devfn 0x8, bad id 0xffffffff
PCI: devfn 0x10, bad id 0xffffffff
PCI: devfn 0x18, bad id 0xffffffff
PCI: devfn 0x20, bad id 0xffffffff
PCI: devfn 0x28, bad id 0xffffffff
PCI: devfn 0x30, bad id 0xffffffff
PCI: devfn 0x38, bad id 0xffffffff
PCI: 01:08.0 [8086/103a] ops
PCI: 01:08.0 [8086/103a] enabled
PCI: devfn 0x48, bad id 0xffffffff
PCI: devfn 0x50, bad id 0xffffffff
PCI: devfn 0x58, bad id 0xffffffff
PCI: devfn 0x60, bad id 0xffffffff
PCI: devfn 0x68, bad id 0xffffffff
PCI: devfn 0x70, bad id 0xffffffff
PCI: devfn 0x78, bad id 0xffffffff
PCI: devfn 0x80, bad id 0xffffffff
PCI: devfn 0x88, bad id 0xffffffff
PCI: devfn 0x90, bad id 0xffffffff
PCI: devfn 0x98, bad id 0xffffffff
PCI: devfn 0xa0, bad id 0xffffffff
PCI: devfn 0xa8, bad id 0xffffffff
PCI: devfn 0xb0, bad id 0xffffffff
PCI: devfn 0xb8, bad id 0xffffffff
PCI: devfn 0xc0, bad id 0xffffffff
PCI: devfn 0xc8, bad id 0xffffffff
PCI: devfn 0xd0, bad id 0xffffffff
PCI: devfn 0xd8, bad id 0xffffffff
PCI: devfn 0xe0, bad id 0xffffffff
PCI: devfn 0xe8, bad id 0xffffffff
PCI: devfn 0xf0, bad id 0xffffffff
PCI: devfn 0xf8, bad id 0xffffffff
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:1f.0
Found SMSC Super I/O (ID=0x60, rev=0x01)
PNP: 002e.0 disabled
PNP: 002e.3 enabled
PNP: 002e.4 enabled
PNP: 002e.5 enabled
PNP: 002e.7 enabled
PNP: 002e.9 disabled
PNP: 002e.a enabled
PNP: 002e.b disabled
scan_static_bus for PCI: 00:1f.0 done
PCI: pci_scan_bus returning with max=001
scan_static_bus for Root Device done
done
Allocating resources...
Reading resources...
Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0
Root Device read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:1e.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 01:08.0 14 * [0x00000000 - 0x0000003f] io
PCI: 00:1e.0 compute_allocate_io: base: 00000040 size: 00001000 align: 12 gran: 12 done
PCI: 00:1e.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:1e.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 01:08.0 10 * [0x00000000 - 0x00000fff] mem
PCI: 00:1e.0 compute_allocate_mem: base: 00001000 size: 00100000 align: 20 gran: 20 done
PCI: 00:1f.0 read_resources bus 0 link: 0
PCI: 00:1f.0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
PCI: 00:1e.0 1c * [0x00001000 - 0x00001fff] io
PCI: 00:1f.5 10 * [0x00002000 - 0x000020ff] io
PCI: 00:1f.6 10 * [0x00002400 - 0x000024ff] io
PCI: 00:1f.6 14 * [0x00002800 - 0x0000287f] io
PCI: 00:1f.5 14 * [0x00002880 - 0x000028bf] io
PCI: 00:1d.0 20 * [0x000028c0 - 0x000028df] io
PCI: 00:1d.1 20 * [0x000028e0 - 0x000028ff] io
PCI: 00:1d.2 20 * [0x00002c00 - 0x00002c1f] io
PCI: 00:1f.3 20 * [0x00002c20 - 0x00002c3f] io
PCI: 00:1f.1 20 * [0x00002c40 - 0x00002c4f] io
PCI: 00:1f.1 10 * [0x00002c50 - 0x00002c57] io
PCI: 00:1f.1 18 * [0x00002c60 - 0x00002c67] io
PCI: 00:1f.1 14 * [0x00002c70 - 0x00002c73] io
PCI: 00:1f.1 1c * [0x00002c80 - 0x00002c83] io
Root Device compute_allocate_io: base: 00002c84 size: 00002884 align: 12 gran: 0 done
Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
PCI: 00:02.0 10 * [0x00000000 - 0x07ffffff] prefmem
PCI: 00:1e.0 20 * [0x08000000 - 0x080fffff] mem
PCI: 00:02.0 14 * [0x08100000 - 0x0817ffff] mem
PCI: 00:1d.7 10 * [0x08180000 - 0x081803ff] mem
PCI: 00:1f.1 24 * [0x08181000 - 0x081813ff] mem
PCI: 00:1f.5 18 * [0x08182000 - 0x081821ff] mem
PCI: 00:1f.5 1c * [0x08183000 - 0x081830ff] mem
Root Device compute_allocate_mem: base: 08183100 size: 08183100 align: 27 gran: 0 done
Done reading resources.
Allocating VGA resource PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Setting resources...
Root Device compute_allocate_io: base: 00001000 size: 00002884 align: 12 gran: 0
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
PCI: 00:1e.0 1c * [0x00001000 - 0x00001fff] io
PCI: 00:1f.5 10 * [0x00002000 - 0x000020ff] io
PCI: 00:1f.6 10 * [0x00002400 - 0x000024ff] io
PCI: 00:1f.6 14 * [0x00002800 - 0x0000287f] io
PCI: 00:1f.5 14 * [0x00002880 - 0x000028bf] io
PCI: 00:1d.0 20 * [0x000028c0 - 0x000028df] io
PCI: 00:1d.1 20 * [0x000028e0 - 0x000028ff] io
PCI: 00:1d.2 20 * [0x00002c00 - 0x00002c1f] io
PCI: 00:1f.3 20 * [0x00002c20 - 0x00002c3f] io
PCI: 00:1f.1 20 * [0x00002c40 - 0x00002c4f] io
PCI: 00:1f.1 10 * [0x00002c50 - 0x00002c57] io
PCI: 00:1f.1 18 * [0x00002c60 - 0x00002c67] io
PCI: 00:1f.1 14 * [0x00002c70 - 0x00002c73] io
PCI: 00:1f.1 1c * [0x00002c80 - 0x00002c83] io
Root Device compute_allocate_io: base: 00002c84 size: 00001c84 align: 12 gran: 0 done
Root Device compute_allocate_mem: base: f0000000 size: 08183100 align: 27 gran: 0
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
PCI: 00:02.0 10 * [0xf0000000 - 0xf7ffffff] prefmem
PCI: 00:1e.0 20 * [0xf8000000 - 0xf80fffff] mem
PCI: 00:02.0 14 * [0xf8100000 - 0xf817ffff] mem
PCI: 00:1d.7 10 * [0xf8180000 - 0xf81803ff] mem
PCI: 00:1f.1 24 * [0xf8181000 - 0xf81813ff] mem
PCI: 00:1f.5 18 * [0xf8182000 - 0xf81821ff] mem
PCI: 00:1f.5 1c * [0xf8183000 - 0xf81830ff] mem
Root Device compute_allocate_mem: base: f8183100 size: 08183100 align: 27 gran: 0 done
Root Device assign_resources, bus 0 link: 0
Setting RAM size to 57344
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:02.0 10 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x1b prefmem
PCI: 00:02.0 14 <- [0x00f8100000 - 0x00f817ffff] size 0x00080000 gran 0x13 mem
PCI: 00:02.0 30 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x00 romem
PCI: 00:1d.0 20 <- [0x00000028c0 - 0x00000028df] size 0x00000020 gran 0x05 io
PCI: 00:1d.1 20 <- [0x00000028e0 - 0x00000028ff] size 0x00000020 gran 0x05 io
PCI: 00:1d.2 20 <- [0x0000002c00 - 0x0000002c1f] size 0x00000020 gran 0x05 io
PCI: 00:1d.7 10 <- [0x00f8180000 - 0x00f81803ff] size 0x00000400 gran 0x0a mem
PCI: 00:1e.0 compute_allocate_io: base: 00001000 size: 00001000 align: 12 gran: 12
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 01:08.0 14 * [0x00001000 - 0x0000103f] io
PCI: 00:1e.0 compute_allocate_io: base: 00001040 size: 00001000 align: 12 gran: 12 done
PCI: 00:1e.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:1e.0 compute_allocate_mem: base: f8000000 size: 00100000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 01:08.0 10 * [0xf8000000 - 0xf8000fff] mem
PCI: 00:1e.0 compute_allocate_mem: base: f8001000 size: 00100000 align: 20 gran: 20 done
PCI: 00:1e.0 20 <- [0x00f8000000 - 0x00f80fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:1e.0 assign_resources, bus 1 link: 0
PCI: 01:08.0 10 <- [0x00f8000000 - 0x00f8000fff] size 0x00001000 gran 0x0c mem
PCI: 01:08.0 14 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
PCI: 00:1e.0 assign_resources, bus 1 link: 0
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io
PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
PNP: 002e.3 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq
PNP: 002e.4 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.4 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 002e.5 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 002e.7 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.7 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.7 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.7 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
PNP: 002e.a 60 <- [0x0000000800 - 0x00000007ff] size 0x00000000 gran 0x00 io
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.1 10 <- [0x0000002c50 - 0x0000002c57] size 0x00000008 gran 0x03 io
PCI: 00:1f.1 14 <- [0x0000002c70 - 0x0000002c73] size 0x00000004 gran 0x02 io
PCI: 00:1f.1 18 <- [0x0000002c60 - 0x0000002c67] size 0x00000008 gran 0x03 io
PCI: 00:1f.1 1c <- [0x0000002c80 - 0x0000002c83] size 0x00000004 gran 0x02 io
PCI: 00:1f.1 20 <- [0x0000002c40 - 0x0000002c4f] size 0x00000010 gran 0x04 io
PCI: 00:1f.1 24 <- [0x00f8181000 - 0x00f81813ff] size 0x00000400 gran 0x0a mem
PCI: 00:1f.3 20 <- [0x0000002c20 - 0x0000002c3f] size 0x00000020 gran 0x05 io
PCI: 00:1f.5 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 00:1f.5 14 <- [0x0000002880 - 0x00000028bf] size 0x00000040 gran 0x06 io
PCI: 00:1f.5 18 <- [0x00f8182000 - 0x00f81821ff] size 0x00000200 gran 0x09 mem
PCI: 00:1f.5 1c <- [0x00f8183000 - 0x00f81830ff] size 0x00000100 gran 0x08 mem
PCI: 00:1f.6 10 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io
PCI: 00:1f.6 14 <- [0x0000002800 - 0x000000287f] size 0x00000080 gran 0x07 io
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 00/00
PCI: 00:02.0 cmd <- 03
PCI: 00:1d.0 cmd <- 01
PCI: 00:1d.1 cmd <- 01
PCI: 00:1d.2 cmd <- 01
PCI: 00:1d.7 subsystem <- 00/00
PCI: 00:1d.7 cmd <- 02
PCI: 00:1e.0 bridge ctrl <- 0003
PCI: 00:1e.0 cmd <- 07
PCI: 01:08.0 cmd <- 03
PCI: 00:1f.0 cmd <- 0f
PCI: 00:1f.1 cmd <- 03
PCI: 00:1f.3 subsystem <- 00/00
PCI: 00:1f.3 cmd <- 01
PCI: 00:1f.5 cmd <- 03
PCI: 00:1f.6 cmd <- 01
done.
Initializing devices...
Root Device init
PCI: 00:00.0 init
Northbridge init
PCI: 00:02.0 init
rom address for PCI: 00:02.0 = fff00000
PCI Expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040
PCI ROM Image, Vendor 8086, Device 3577,
PCI ROM Image, Class Code 030000, Code Type 00
copying VGA ROM Image from 0xfff00000 to 0xc0000, 0x10000 bytes
entering emulator
halt_sys: file /home/joe/coreboot-v2/src/devices/emulator/x86emu/ops.c, line 4387
PCI: 00:1d.0 init
PCI: 00:1d.1 init
PCI: 00:1d.2 init
PCI: 00:1d.7 init
EHCI: Setting up controller.. done.
PCI: 00:1e.0 init
PCI: 00:1f.0 init
IOAPIC Southbridge enabled 2186
Southbridge APIC ID = 2000000
Set power on if power fails
RTC Init
PNP: 002e.3 init
PNP: 002e.4 init
PNP: 002e.5 init
PNP: 002e.7 init
Keyboard init...
PNP: 002e.a init
PCI: 00:1f.1 init
IDE0 IDE1 PCI: 00:1f.3 init
APIC_CLUSTER: 0 init
malloc Enter, size 1100, free_mem_ptr 00028000
malloc 0x00028000
Initializing CPU #0
CPU: vendor Intel device 6b4
CPU: family 06, model 0b, stepping 04
Enabling cache
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB
DONE fixed MTRRs
call enable_fixed_mtrr()
Setting variable MTRR 0, base: 0MB, range: 32MB, type WB
ADDRESS_MASK_HIGH=0xf
Setting variable MTRR 1, base: 32MB, range: 16MB, type WB
ADDRESS_MASK_HIGH=0xf
Setting variable MTRR 2, base: 48MB, range: 8MB, type WB
ADDRESS_MASK_HIGH=0xf
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
microcode_info: sig = 0x000006b4 pf=0x00000010 rev = 0x00000000
Disabling local apic...done.
CPU #0 Initialized
Devices initialized
Copying IRQ routing tables to 0xf0000...done.
Verifing copy of IRQ routing tables at 0xf0000...done
Checking IRQ routing table consistency...
check_pirq_routing_table() - irq_routing_table located at: 0x000f0000
done.
Moving GDT to 0x500...ok
Adjust low_table_end from 0x00000530 to 0x00001000
Adjust rom_table_end from 0x000f0400 to 0x00100000
Wrote coreboot table at: 00000530 - 00000768 checksum a720
Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.3
rom_stream: 0xfff10000 - 0xfffdffff
Found ELF candidate at offset 0
header_offset is 0
Try to load at offset 0x0
malloc Enter, size 32, free_mem_ptr 0002844c
malloc 0x0002844c
New segment addr 0x100000 size 0x3ce80 offset 0xc0 filesize 0x12e68
(cleaned up) New segment addr 0x100000 size 0x3ce80 offset 0xc0 filesize 0x12e68
lb: [0x0000000000004000, 0x000000000002c000)
malloc Enter, size 32, free_mem_ptr 0002846c
malloc 0x0002846c
New segment addr 0x13ce80 size 0x48 offset 0x12f40 filesize 0x48
(cleaned up) New segment addr 0x13ce80 size 0x48 offset 0x12f40 filesize 0x48
lb: [0x0000000000004000, 0x000000000002c000)
Dropping non PT_LOAD segment
Dropping non PT_LOAD segment
Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000003ce80 filesz: 0x0000000000012e68
[ 0x0000000000100000, 0000000000112e68, 0x000000000013ce80) <- 00000000000000c0
Clearing Segment: addr: 0x0000000000112e68 memsz: 0x000000000002a018
Loading Segment: addr: 0x000000000013ce80 memsz: 0x0000000000000048 filesz: 0x0000000000000048
[ 0x000000000013ce80, 000000000013cec8, 0x000000000013cec8) <- 0000000000012f40
Loaded segments
verified segments
closed down stream
Jumping to boot code at 0x10e61c
entry = 0x0010e61c
lb_start = 0x00004000
lb_size = 0x00028000
adjust = 0x037d4000
buffer = 0x037b0000
elf_boot_notes = 0x00021c20
adjusted_boot_notes = 0x037f5c20
FILO version 0.5 (joe at localhost.localdomain) Fri Mar 28 09:16:02 EDT 2008
menu: hdc1:/grub/grub.conf
hdc: LBA 40GB: WDC WD400BB-23FJA0
Mounted ext2fs
Press any key to continue.
Press any key to continue.
Press any key to continue.
[H[J
FILO 0.5
[m[4;2H+-------------------------------------------------------------------------+[5;2H|[5;76H|[6;2H|[6;76H|[7;2H|[7;76H|[8;2H|[8;76H|[9;2H|[9;76H|[10;2H|[10;76H|[11;2H|[11;76H|[12;2H|[12;76H|[13;2H|[13;76H|[14;2H|[14;76H|[15;2H|[15;76H|[16;2H|[16;76H|[17;2H+-------------------------------------------------------------------------+[m
Use the ^ and v keys to select which entry is highlighted.
Press enter to boot the selected OS, 'e' to edit the
commands before booting, 'a' to modify the kernel arguments
before booting, or 'c' for a command-line.[5;78H [m[7m[5;3H Fedora (2.6.23.15-80.fc7) [5;75H[m[m[6;3H Fedora Console (2.6.23.15-80.fc7) [6;75H[m[m[7;3H [7;75H[m[m[8;3H [8;75H[m[m[9;3H [9;75H[m[m[10;3H [10;75H[m[m[11;3H [11;75H[m[m[12;3H [12;75H[m[m[13;3H [13;75H[m[m[14;3H [14;75H[m[m[15;3H [15;75H[m[m[16;3H [16;75H[m[16;78H [5;75H[23;4HThe highlighted entry will be booted automatically in 10 seconds. [5;75H[23;4HThe highlighted entry will be booted automatically in 9 seconds. [5;75H[23;4HThe highlighted entry will be booted automatically in 8 seconds. [5;75H[23;4H [5;75H[H[J Booting 'Fedora (2.6.23.15-80.fc7)'
root (hd2,0)
kernel /vmlinuz-2.6.23.15-80.fc7 ro root=LABEL=/ rhgb quiet
initrd /initrd-2.6.23.15-80.fc7.img
[H[J
Booting 'hdc1:/vmlinuz-2.6.23.15-80.fc7 ro root=LABEL=/ rhgb quiet initrd=/init
rd-2.6.23.15-80.fc7.img'
Found Linux version 2.6.23.15-80.fc7 (mockbuild at xenbuilder4.fedora.phx.redhat.com) #1 SMP Sun Feb 10 17:29:10 EST 2008 bzImage.
Loading kernel... ok
Loading initrd... ok
Jumping to entry point...
�
Fedora release 7 (Moonshine)
Kernel 2.6.23.15-80.fc7 on an i686
Serial Console Login: root
Password:
Last login: Mon Aug 1 04:01:13 on ttyS0
[root at localhost ~]# lspci -xxx
00:00.0 Host bridge: Intel Corporation 82830 830 Chipset Host Bridge (rev 04)
00: 86 80 75 35 06 00 10 20 04 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e
50: 72 a0 44 00 00 00 00 00 00 30 33 33 33 33 33 33
60: 00 00 02 02 02 02 00 00 00 00 00 00 00 00 00 00
70: ff f1 ff ff 00 00 00 00 10 00 00 00 70 02 00 20
80: 00 00 00 00 00 00 00 00 80 60 33 0b 00 00 00 00
90: 02 38 00 10 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 1b 49 9b fc
f0: 11 11 01 00 00 00 0b 05 36 cf 2f cf 22 cc 1f cc
00:02.0 VGA compatible controller: Intel Corporation 82830 CGC [Chipset Graphics Controller] (rev 04)
00: 86 80 77 35 07 00 90 00 04 00 00 03 00 00 80 00
10: 08 00 00 f0 00 00 10 f8 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 d0 00 00 00 00 00 00 00 00 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 01 00 21 02 00 00 00 00 00 80 13 23 00 00 00 00
e0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:1d.0 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1 (rev 02)
00: 86 80 c2 24 05 00 80 02 02 00 03 0c 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: c1 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 27 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00
00:1d.1 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2 (rev 02)
00: 86 80 c4 24 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: e1 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 27 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00
00:1d.2 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3 (rev 02)
00: 86 80 c7 24 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 2c 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 27 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00
00:1d.7 USB Controller: Intel Corporation 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller (rev 02)
00: 86 80 cd 24 06 00 90 02 02 20 03 0c 00 00 00 00
10: 00 00 18 f8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 04 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 58 c2 c9 00 00 00 00 0a 00 80 20 00 00 00 00
60: 20 20 7f 00 00 00 00 00 01 00 00 00 00 00 08 c0
70: 00 00 c5 0f 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 78 bf 1f 00 88 83 00 00 60 0f 00 00 06 00 00 00
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 82)
00: 86 80 4e 24 07 00 80 80 82 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 40 10 10 80 02
20: 00 f8 00 f8 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00
40: 02 28 20 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 14 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 10 00 08 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 01 00 02 00 00 00 c0 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 3a 3c
00:1f.0 ISA bridge: Intel Corporation 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge (rev 02)
00: 86 80 c0 24 0f 00 80 02 02 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 01 04 00 00 10 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 01 05 00 00 10 00 00 00
60: 03 05 06 07 90 00 00 00 09 0a 0b 0c 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: ff fc 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 02 00 00 02 00 00 00 0d 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 86 21 00 00 02 0f 00 00 04 00 00 00 00 00 00 00
e0: 10 00 00 ff 00 00 0f 30 33 22 11 00 00 00 67 45
f0: 0f 00 00 00 00 00 00 00 60 0f 02 00 00 00 01 00
00:1f.1 IDE interface: Intel Corporation 82801DB (ICH4) IDE Controller (rev 02)
00: 86 80 cb 24 07 00 80 02 02 8a 01 01 00 00 00 00
10: 51 2c 00 00 71 2c 00 00 61 2c 00 00 81 2c 00 00
20: 41 2c 00 00 00 10 18 f8 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00
40: 00 80 07 a3 00 00 00 00 04 00 00 02 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 08 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00
00:1f.3 SMBus: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller (rev 02)
00: 86 80 c3 24 01 00 80 02 02 00 05 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 21 2c 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00
40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00
00:1f.5 Multimedia audio controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller (rev 02)
00: 86 80 c5 24 07 00 90 02 02 00 01 04 00 00 00 00
10: 01 20 00 00 81 28 00 00 00 20 18 f8 00 30 18 f8
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 02 00 00
40: 09 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 c9 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00
00:1f.6 Modem: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Modem Controller (rev 02)
00: 86 80 c6 24 01 00 90 02 02 00 03 07 00 00 00 00
10: 01 24 00 00 01 28 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 02 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 c9 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00
01:08.0 Ethernet controller: Intel Corporation 82801DB PRO/100 VE (CNR) Ethernet Controller (rev 82)
00: 86 80 3a 10 07 00 90 02 82 00 00 02 10 40 00 00
10: 00 00 00 f8 01 10 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00
30: 00 00 00 00 dc 00 00 00 00 00 00 00 00 01 08 38
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 22 fe
e0: 00 40 00 3a 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[root at localhost ~]#
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