[coreboot] [PATCH] flashrom: Add support for SPI-Chips on ICH9

[Carl-Daniel Hailfinger]

On 16.05.2008 16:04, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> There's another question I have for you: How should we handle the
>> situation if the opcode table has been locked by the BIOS? One way would
>> be to load the locked opcode table from the southbridge and proceed as
>> normal. If any opcodes we want are not in the table, fail the
>> transaction with an error message. program_opcodes() could check the
>> lock bit and return failure, then another function would malloc
>> curopcodes and read the chipset opcodes into it.
>>   
>>     
> Sounds reasonable.
>   
>> By the way, some people have volunteered to test flashrom on ICH7 and I
>> think ICH7/ICH8 support would be rather easy to add to the ICH9 driver,
>> resulting in improved testing coverage. It's your decision, though, and
>> I am very thankful you wrote the ICH9 driver.
>>   
>>     
> How different are they wrt their SPI interface?
>   

ICH8 and ICH9 are identical AFAICS. In theory, the patch below should be
enough to get working ICH8 support.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-ich8/chipset_enable.c
===================================================================
--- flashrom-ich8/chipset_enable.c	(Revision 3326)
+++ flashrom-ich8/chipset_enable.c	(Arbeitskopie)
@@ -234,13 +234,19 @@
 	return enable_flash_ich_dc(dev, name);
 }
 
-static int enable_flash_ich78(struct pci_dev *dev, const char *name)
+static int enable_flash_ich7(struct pci_dev *dev, const char *name)
 {
 	return enable_flash_ich_dc_spi(dev, name, 0x3020);
 }
 
 int ich9_detected = 0;
 
+static int enable_flash_ich8(struct pci_dev *dev, const char *name)
+{
+	ich9_detected = 1;
+	return enable_flash_ich_dc_spi(dev, name, 0x3020);
+}
+
 static int enable_flash_ich9(struct pci_dev *dev, const char *name)
 {
 	ich9_detected = 1;
@@ -597,15 +603,15 @@
 	{0x8086, 0x25a1, "Intel 6300ESB",	enable_flash_ich_4e},
 	{0x8086, 0x2640, "Intel ICH6/ICH6R",	enable_flash_ich_dc},
 	{0x8086, 0x2641, "Intel ICH6-M",	enable_flash_ich_dc},
-	{0x8086, 0x27b0, "Intel ICH7DH",	enable_flash_ich78},
-	{0x8086, 0x27b8, "Intel ICH7/ICH7R",	enable_flash_ich78},
-	{0x8086, 0x27b9, "Intel ICH7M",		enable_flash_ich78},
-	{0x8086, 0x27bd, "Intel ICH7MDH",	enable_flash_ich78},
-	{0x8086, 0x2810, "Intel ICH8/ICH8R",	enable_flash_ich78},
-	{0x8086, 0x2811, "Intel ICH8M-E",	enable_flash_ich78},
-	{0x8086, 0x2812, "Intel ICH8DH",	enable_flash_ich78},
-	{0x8086, 0x2814, "Intel ICH8DO",	enable_flash_ich78},
-	{0x8086, 0x2815, "Intel ICH8M",		enable_flash_ich78},
+	{0x8086, 0x27b0, "Intel ICH7DH",	enable_flash_ich7},
+	{0x8086, 0x27b8, "Intel ICH7/ICH7R",	enable_flash_ich7},
+	{0x8086, 0x27b9, "Intel ICH7M",		enable_flash_ich7},
+	{0x8086, 0x27bd, "Intel ICH7MDH",	enable_flash_ich7},
+	{0x8086, 0x2810, "Intel ICH8/ICH8R",	enable_flash_ich8},
+	{0x8086, 0x2811, "Intel ICH8M-E",	enable_flash_ich8},
+	{0x8086, 0x2812, "Intel ICH8DH",	enable_flash_ich8},
+	{0x8086, 0x2814, "Intel ICH8DO",	enable_flash_ich8},
+	{0x8086, 0x2815, "Intel ICH8M",		enable_flash_ich8},
 	{0x8086, 0x2912, "Intel ICH9DH",	enable_flash_ich9},
 	{0x8086, 0x2914, "Intel ICH9DO",	enable_flash_ich9},
 	{0x8086, 0x2916, "Intel ICH9R",		enable_flash_ich9},