[coreboot] r3334 - in trunk/coreboot-v2: src/mainboard/via src/mainboard/via/epia-cn src/northbridge/via/cn700 targets/via targets/via/epia-cn
svn at coreboot.org
svn at coreboot.org
Mon May 19 14:17:44 CEST 2008
Author: uwe
Date: 2008-05-19 14:17:43 +0200 (Mon, 19 May 2008)
New Revision: 3334
Added:
trunk/coreboot-v2/src/mainboard/via/epia-cn/
trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb
trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb
trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c
trunk/coreboot-v2/src/mainboard/via/epia-cn/chip.h
trunk/coreboot-v2/src/mainboard/via/epia-cn/cmos.layout
trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c
trunk/coreboot-v2/src/mainboard/via/epia-cn/mainboard.c
trunk/coreboot-v2/targets/via/epia-cn/
trunk/coreboot-v2/targets/via/epia-cn/Config.lb
Modified:
trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c
trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c
Log:
Add support for the VIA EPIA-CN baord, which uses C7 + CN700 + VT8237R.
This also contains various improvements of the CN700 code in svn.
Signed-off-by: Aaron Lwe <aaron.lwe at gmail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb 2008-05-19 12:17:43 UTC (rev 3334)
@@ -0,0 +1,142 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 VIA Technologies, Inc.
+## (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
+else
+ default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
+ default ROM_SECTION_OFFSET = 0
+end
+default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
+default XIP_ROM_SIZE = 64 * 1024
+default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+arch i386 end
+driver mainboard.o
+if HAVE_PIRQ_TABLE object irq_tables.o end
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_ACPI_TABLES
+ object fadt.o
+ object dsdt.o
+ object acpi_tables.o
+end
+makerule ./failover.E
+ depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./failover.inc
+ depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+mainboardinit arch/i386/lib/cpu_reset.inc
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+if USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+end
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+dir /pc80
+config chip.h
+
+chip northbridge/via/cn700 # Northbridge
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # AGP Bridge
+ device pci 0.1 on end # Error Reporting
+ device pci 0.2 on end # Host Bus Control
+ device pci 0.3 on end # Memory Controller
+ device pci 0.4 on end # Power Management
+ device pci 0.7 on end # V-Link Controller
+ device pci 1.0 on end # PCI Bridge
+ chip southbridge/via/vt8237r # Southbridge
+ # Enable both IDE channels.
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ # Both cables are 40pin.
+ register "ide0_80pin_cable" = "0"
+ register "ide1_80pin_cable" = "0"
+ device pci f.0 on end # IDE
+ register "fn_ctrl_lo" = "0x8a"
+ register "fn_ctrl_hi" = "0x9d"
+ device pci 10.0 on end # USB 1.1
+ device pci 10.1 on end # USB 1.1
+ device pci 10.2 on end # USB 1.1
+ device pci 10.3 on end # USB 1.1
+ device pci 11.0 on # Southbridge LPC
+ chip superio/via/vt1211 # Super I/O
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.b on # HWM
+ io 0x60 = 0xec00
+ end
+ end
+ end
+ device pci 11.5 on end # AC'97 audio
+ # device pci 11.6 off end # AC'97 Modem
+ device pci 12.0 on end # Ethernet
+ end
+ end
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/via/model_c7 # VIA C7
+ device apic 0 on end # APIC
+ end
+ end
+end
Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2008-05-19 12:17:43 UTC (rev 3334)
@@ -0,0 +1,108 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 VIA Technologies, Inc.
+## (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses HAVE_OPTION_TABLE
+uses USE_OPTION_TABLE
+uses CONFIG_ROM_PAYLOAD
+uses IRQ_SLOT_COUNT
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses COREBOOT_EXTRA_VERSION
+uses ARCH
+uses FALLBACK_SIZE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses _RAMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses HAVE_MP_TABLE
+uses HAVE_ACPI_TABLES
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_MAX_PCI_BUSES
+uses TTYS0_BAUD
+uses CONFIG_CHIP_NAME
+uses CONFIG_VIDEO_MB
+uses CONFIG_IOAPIC
+
+default ROM_SIZE = 512 * 1024
+default CONFIG_IOAPIC = 0
+default CONFIG_VIDEO_MB = 32
+default CONFIG_CONSOLE_SERIAL8250 = 1
+default CONFIG_PCI_ROM_RUN = 0
+default CONFIG_CONSOLE_VGA = 0
+default CONFIG_CHIP_NAME = 1
+default HAVE_FALLBACK_BOOT = 1
+default HAVE_MP_TABLE = 0
+default CONFIG_UDELAY_TSC = 1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
+default HAVE_HARD_RESET = 0
+default HAVE_PIRQ_TABLE = 1
+default IRQ_SLOT_COUNT = 10
+default HAVE_ACPI_TABLES = 0
+default HAVE_OPTION_TABLE = 1
+default ROM_IMAGE_SIZE = 64 * 1024
+default FALLBACK_SIZE = ROM_SIZE
+default USE_FALLBACK_IMAGE = 1
+default STACK_SIZE = 8 * 1024
+default HEAP_SIZE = 16 * 1024
+#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default USE_OPTION_TABLE = 0
+default _RAMBASE = 0x00004000
+default CONFIG_ROM_PAYLOAD = 1
+default CROSS_COMPILE = ""
+default CC = "$(CROSS_COMPILE)gcc -m32"
+default HOSTCC = "gcc"
+
+##
+## Set this to the max PCI bus number you would ever use for PCI config I/O.
+## Setting this number very high will make pci_locate_device() take a long
+## time when it can't find a device.
+##
+default CONFIG_MAX_PCI_BUSES = 3
+
+end
+
Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c 2008-05-19 12:17:43 UTC (rev 3334)
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "northbridge/via/cn700/raminit.h"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8235/vt8235_early_serial.c"
+
+static void memreset_setup(void)
+{
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/via/cn700/raminit.c"
+
+static void enable_mainboard_devices(void)
+{
+ device_t dev;
+ u8 reg;
+
+ /*
+ * If I enable SATA, FILO will not find the IDE disk, so I'll disable
+ * SATA here. To not conflict with PCI spec, I'll move IDE device
+ * from 00:0f.1 to 00:0f.0.
+ */
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT6420_SATA), 0);
+ if (dev != PCI_DEV_INVALID) {
+ /* Enable PATA. */
+ reg = pci_read_config8(dev, 0xd1);
+ reg |= 0x08;
+ pci_write_config8(dev, 0xd1, reg);
+ reg = pci_read_config8(dev, 0x49);
+ reg |= 0x80;
+ pci_write_config8(dev, 0x49, reg);
+ } else {
+ print_debug("No SATA device\r\n");
+ }
+
+ /* Disable SATA, and PATA device will be 00:0f.0. */
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+ if (dev == PCI_DEV_INVALID)
+ die("Southbridge not found!!!\r\n");
+ reg = pci_read_config8(dev, 0x50);
+ reg |= 0x08;
+ pci_write_config8(dev, 0x50, reg);
+}
+
+static const struct mem_controller ctrl = {
+ .d0f0 = 0x0000,
+ .d0f2 = 0x2000,
+ .d0f3 = 0x3000,
+ .d0f4 = 0x4000,
+ .d0f7 = 0x7000,
+ .d1f0 = 0x8000,
+ .channel0 = { 0x50 },
+};
+
+static void main(unsigned long bist)
+{
+ unsigned long x;
+ device_t dev;
+
+ /* Enable multifunction for northbridge. */
+ pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
+
+ enable_vt8235_serial();
+ uart_init();
+ console_init();
+
+ print_spew("In auto.c:main()\r\n");
+
+ enable_smbus();
+ smbus_fixup(&ctrl);
+
+ if (bist == 0) {
+ print_debug("doing early_mtrr\r\n");
+ early_mtrr_init();
+ }
+
+ /* Halt if there was a built-in self test failure. */
+ report_bist_failure(bist);
+
+ print_debug("Enabling mainboard devices\r\n");
+ enable_mainboard_devices();
+
+ ddr_ram_setup(&ctrl);
+
+ /* ram_check(0, 640 * 1024); */
+
+ print_spew("Leaving auto.c:main()\r\n");
+}
Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/chip.h
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/chip.h (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/chip.h 2008-05-19 12:17:43 UTC (rev 3334)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_via_epia_cn_ops;
+
+struct mainboard_via_epia_cn_config {
+ int nothing;
+};
Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/cmos.layout (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/cmos.layout 2008-05-19 12:17:43 UTC (rev 3334)
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c 2008-05-19 12:17:43 UTC (rev 3334)
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE,
+ PIRQ_VERSION,
+ 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x11 << 3) | 0x0, /* Interrupt router device */
+ 0x828, /* IRQs devoted exclusively to PCI usage */
+ 0x1106, /* Vendor */
+ 0x596, /* Device */
+ 0, /* Crap (miniport) */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x3e, /* Checksum */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
+ {0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
+ {0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
+ {0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
+ {0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
+ {0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+ {0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+ {0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+ {0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+ {0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/mainboard.c (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/mainboard.c 2008-05-19 12:17:43 UTC (rev 3334)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_via_epia_cn_ops = {
+ CHIP_NAME("VIA EPIA-CN Mainboard")
+};
Modified: trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c 2008-05-17 21:33:35 UTC (rev 3333)
+++ trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c 2008-05-19 12:17:43 UTC (rev 3334)
@@ -1,6 +1,8 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
* Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
*
* This program is free software; you can redistribute it and/or modify
@@ -34,10 +36,12 @@
static void memctrl_init(device_t dev)
{
+ device_t vlink_dev;
u16 reg16;
+ u8 ranks;
+ u8 pagec, paged, pagee, pagef;
+ u8 shadowreg;
- pci_write_config8(dev, 0x86, 0x2d);
-
/* Set up the vga framebuffer size */
reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15);
pci_write_config16(dev, 0xa0, reg16);
@@ -45,8 +49,41 @@
/* Set up VGA timers */
pci_write_config8(dev, 0xa2, 0x44);
- pci_write_config16(dev, 0xb0, 0xaa60);
+ for (ranks = 0x4b; ranks >= 0x48; ranks--) {
+ if (pci_read_config8(dev, ranks)) {
+ ranks -= 0x48;
+ break;
+ }
+ }
+ if (ranks == 0x47)
+ ranks = 0x00;
+ reg16 = 0xaae0;
+ reg16 |= ranks;
+ /* GMINT Misc. FrameBuffer rank */
+ pci_write_config16(dev, 0xb0, reg16);
+ /* AGPCINT Misc. */
pci_write_config8(dev, 0xb8, 0x08);
+
+ /* shadown ram */
+ pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30;
+ /* PAGE C, D, E are all read write enable */
+ pci_write_config8(dev, 0x80, pagec);
+ pci_write_config8(dev, 0x81, paged);
+ pci_write_config8(dev, 0x82, pagee);
+ /* PAGE F are read/writable */
+ shadowreg = pci_read_config8(dev, 0x83);
+ shadowreg |= pagef;
+ pci_write_config8(dev, 0x83, shadowreg);
+ /* vlink mirror */
+ vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN700_VLINK, 0);
+ if (vlink_dev) {
+ pci_write_config8(vlink_dev, 0x61, pagec);
+ pci_write_config8(vlink_dev, 0x62, paged);
+ pci_write_config8(vlink_dev, 0x64, pagee);
+ shadowreg = pci_read_config8(vlink_dev, 0x63);
+ shadowreg |= pagef;
+ pci_write_config8(vlink_dev, 0x63, shadowreg);
+ }
}
static const struct device_operations memctrl_operations = {
@@ -124,7 +161,10 @@
static void pci_domain_set_resources(device_t dev)
{
- static const u8 ramregs[] = {0x40, 0x41, 0x42, 0x43};
+ /*
+ * the order is important to find the correct ram size.
+ */
+ static const u8 ramregs[] = {0x43, 0x42, 0x41, 0x40};
device_t mc_dev;
u32 pci_tolm;
@@ -133,19 +173,25 @@
pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
-
+
if (mc_dev) {
unsigned long tomk, tolmk;
unsigned char rambits;
int i, idx;
+ /*
+ * once the register value is not zero, the ramsize is
+ * this register's value multiply 64 * 1024 * 1024
+ */
for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
- reg = pci_read_config8(mc_dev, ramregs[i]);
- rambits += reg;
+ rambits = pci_read_config8(mc_dev, ramregs[i]);
+ if (rambits != 0)
+ break;
}
- tomk = rambits;
+ tomk = rambits * 64 * 1024;
+ printk_spew("tomk is 0x%x\n", tomk);
/* Compute the Top Of Low Memory, in Kb */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
@@ -156,16 +202,15 @@
idx = 10;
/* TODO: Hole needed? */
ram_resource(dev, idx++, 0, 640); /* first 640k */
- /* Leave a hole for vga */
- ram_resource(dev, idx++, 768, (tolmk - 768 -
- (CONFIG_VIDEO_MB * 1024)));
+ /* Leave a hole for vga, 0xa0000 - 0xc0000 */
+ ram_resource(dev, idx++, 768, (tolmk - 768 - CONFIG_VIDEO_MB * 1024));
}
assign_resources(&dev->link[0]);
}
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
- printk_spew("Entering cn700 pci_domain_scan_bus.\n");
+ printk_debug("Entering cn700 pci_domain_scan_bus.\n");
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
Modified: trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c 2008-05-17 21:33:35 UTC (rev 3333)
+++ trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c 2008-05-19 12:17:43 UTC (rev 3334)
@@ -1,6 +1,8 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
* Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
*
* This program is free software; you can redistribute it and/or modify
@@ -39,7 +41,7 @@
#define DUMPNORTH()
#endif
-static void do_ram_command(device_t dev, u8 command, u32 addr_offset)
+static void do_ram_command(device_t dev, u8 command)
{
u8 reg;
@@ -55,11 +57,8 @@
PRINT_DEBUG_MEM(" to 0x");
PRINT_DEBUG_MEM_HEX32(0 + addr_offset);
PRINT_DEBUG_MEM("\r\n");
-
- read32(0 + addr_offset);
}
-
/**
* Configure the bus between the cpu and the northbridge. This might be able to
* be moved to post-ram code in the future. For the most part, these registers
@@ -83,7 +82,7 @@
/* Arbitration */
pci_write_config8(dev, 0x53, 0x88);
/* Miscellaneous Control */
- pci_write_config8(dev, 0x54, 0x10);
+ pci_write_config8(dev, 0x54, 0x1e);
pci_write_config8(dev, 0x55, 0x16);
/* Write Policy */
pci_write_config8(dev, 0x56, 0x01);
@@ -93,9 +92,8 @@
* 010 : 166MHz 011 : 200MHz
* 100 : 266MHz 101 : 333MHz
* 110/111 : Reserved */
- //pci_write_config8(dev, 0x57, 0x60);//set 200MHz dram clock
/* CPU Miscellaneous Control */
- pci_write_config8(dev, 0x59, 0x60);
+ pci_write_config8(dev, 0x59, 0x44);
/* Write Policy */
pci_write_config8(dev, 0x5d, 0xb2);
/* Bandwidth Timer */
@@ -113,16 +111,16 @@
pci_write_config8(dev, 0x65, 0x0f);
/* Read Line Burst DRDY# Timing Control */
pci_write_config8(dev, 0x66, 0xff);
- pci_write_config8(dev, 0x67, 0x70);
+ pci_write_config8(dev, 0x67, 0x30);
/* Host Bus IO Circuit (See datasheet) */
/* Host Address Pullup/down Driving */
- pci_write_config8(dev, 0x70, 0x33);
- pci_write_config8(dev, 0x71, 0x00);
- pci_write_config8(dev, 0x72, 0x33);
- pci_write_config8(dev, 0x73, 0x00);
+ pci_write_config8(dev, 0x70, 0x11);
+ pci_write_config8(dev, 0x71, 0x11);
+ pci_write_config8(dev, 0x72, 0x11);
+ pci_write_config8(dev, 0x73, 0x11);
/* Miscellaneous Control */
- pci_write_config8(dev, 0x74, 0x00);
+ pci_write_config8(dev, 0x74, 0x35);
/* AGTL+ I/O Circuit */
pci_write_config8(dev, 0x75, 0x28);
/* AGTL+ Compensation Status */
@@ -135,239 +133,330 @@
pci_write_config8(dev, 0x79, 0xaa);
/* Address Strobe Input Delay Control */
pci_write_config8(dev, 0x7a, 0x24);
- /* Address CKG Rising/Falling Time Control */
- pci_write_config8(dev, 0x7b, 0x00);
+ // Address CKG Rising/Falling Time Control
+ pci_write_config8(dev, 0x7b, 0xaa);
/* Address CKG Clock Rising/Falling Time Control */
pci_write_config8(dev, 0x7c, 0x00);
/* Undefined (can't remember why I did this) */
- pci_write_config8(dev, 0x7d, 0x6d);
+ pci_write_config8(dev, 0x7d, 0x6d);
+ pci_write_config8(dev, 0x7e, 0x00);
+ pci_write_config8(dev, 0x7f, 0x00);
+ pci_write_config8(dev, 0x80, 0x1b);
+ pci_write_config8(dev, 0x81, 0x0a);
+ pci_write_config8(dev, 0x82, 0x0a);
+ pci_write_config8(dev, 0x83, 0x0a);
}
/**
+ * Set up dram size according to spd data. Eventually, DRAM timings should be
+ * done in a similar manner.
+ *
+ * @param ctrl The northbridge devices and spd addresses.
+ */
+static void sdram_set_size(const struct mem_controller *ctrl)
+{
+ u8 density, ranks, result, col;
+
+ ranks = spd_read_byte(ctrl->channel0[0], SPD_NUM_DIMM_BANKS);
+ ranks = (ranks & 0x07) + 1;
+ density = spd_read_byte(ctrl->channel0[0], SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
+ switch (density)
+ {
+ case 0x80:
+ result = 0x08; /* 512MB / 64MB = 0x08 */
+ break;
+ case 0x40:
+ result = 0x04;
+ break;
+ case 0x20:
+ result = 0x02;
+ break;
+ case 0x10:
+ result = 0xff; /* 16GB */
+ break;
+ case 0x08:
+ result = 0xff; /* 8GB */
+ break;
+ case 0x04:
+ result = 0xff; /* 4GB */
+ break;
+ case 0x02:
+ result = 0x20; /* 2GB */
+ break;
+ case 0x01:
+ result = 0x10; /* 1GB */
+ break;
+ }
+
+ if (result == 0xff)
+ die("dram module size too big, not supported by cn700\r\n");
+
+ pci_write_config8(ctrl->d0f3, 0x40, result);
+ pci_write_config8(ctrl->d0f3, 0x48, 0x00);
+ if (ranks == 2) {
+ pci_write_config8(ctrl->d0f3, 0x41, result * ranks);
+ pci_write_config8(ctrl->d0f3, 0x49, result);
+ }
+ /* size mirror */
+ pci_write_config8(ctrl->d0f7, 0xe5, (result * ranks) << 2);
+ pci_write_config8(ctrl->d0f7, 0x57, (result * ranks) << 2);
+ /* Low Top Address */
+ pci_write_config8(ctrl->d0f3, 0x84, 0x00);
+ pci_write_config8(ctrl->d0f3, 0x85, (result * ranks) << 2);
+ pci_write_config8(ctrl->d0f3, 0x88, (result * ranks) << 2);
+
+ /* Physical-Virtual Mapping */
+ if (ranks == 2)
+ pci_write_config8(ctrl->d0f3, 0x54, 1 << 7 | 0 << 4 | 1 << 3 | 1 << 0);
+ if (ranks == 1)
+ pci_write_config8(ctrl->d0f3, 0x54, 1 << 7 | 0 << 4);
+ pci_write_config8(ctrl->d0f3, 0x55, 0x00);
+ /* virtual rank interleave, disable */
+ pci_write_config32(ctrl->d0f3, 0x58, 0x00);
+
+ /* MA Map Type */
+ result = spd_read_byte(ctrl->channel0[0], SPD_NUM_BANKS_PER_SDRAM);
+ if (result == 8) {
+ col = spd_read_byte(ctrl->channel0[0], SPD_NUM_COLUMNS);
+ switch (col)
+ {
+ case 10:
+ pci_write_config8(ctrl->d0f3, 0x50, 0xa0);
+ break;
+ case 11:
+ pci_write_config8(ctrl->d0f3, 0x50, 0xc0);
+ break;
+ case 12:
+ pci_write_config8(ctrl->d0f3, 0x50, 0xe0);
+ break;
+ }
+ }
+ else if (result == 4) {
+ col = spd_read_byte(ctrl->channel0[0], SPD_NUM_COLUMNS);
+ switch (col)
+ {
+ case 9:
+ pci_write_config8(ctrl->d0f3, 0x50, 0x00);
+ break;
+ case 10:
+ pci_write_config8(ctrl->d0f3, 0x50, 0x20);
+ break;
+ case 11:
+ pci_write_config8(ctrl->d0f3, 0x50, 0x40);
+ break;
+ case 12:
+ pci_write_config8(ctrl->d0f3, 0x50, 0x60);
+ break;
+ }
+ }
+ pci_write_config8(ctrl->d0f3, 0x51, 0x00);
+}
+
+/**
* Set up various ram and other control registers statically. Some of these may
* not be needed, other should be done with spd info, but that's a project for
* the future
*/
static void sdram_set_registers(const struct mem_controller *ctrl)
{
+ u8 reg;
+
+ /* Set WR=5 */
+ pci_write_config8(ctrl->d0f3, 0x61, 0xe0);
+ /* Set CAS=4 */
+ pci_write_config8(ctrl->d0f3, 0x62, 0xfa);
+ /* dram timing-3 */
+ pci_write_config8(ctrl->d0f3, 0x63, 0xca);
+ /* dram timing-4 */
+ pci_write_config8(ctrl->d0f3, 0x64, 0xcc);
+ /* DIMM command / Address Selection */
+ pci_write_config8(ctrl->d0f3, 0x67, 0x00);
+ /* Disable cross bank/multi page mode */
+ pci_write_config8(ctrl->d0f3, 0x69, 0x00);
+ /* disable refresh now */
+ pci_write_config8(ctrl->d0f3, 0x6a, 0x00);
+
+ /* frequency 100MHZ */
+ pci_write_config8(ctrl->d0f3, 0x90, 0x00);
+ pci_write_config8(ctrl->d0f2, 0x57, 0x18);
+ /* Allow manual dll reset */
+ pci_write_config8(ctrl->d0f3, 0x6b, 0x10);
+
+ /* Bank/Rank Interleave Address Select */
+ pci_write_config8(ctrl->d0f3, 0x52, 0x33);
+ pci_write_config8(ctrl->d0f3, 0x53, 0x3f);
+
+ /* Set to DDR2 sdram, BL=8 (0xc8, 0xc0 for bl=4) */
+ pci_write_config8(ctrl->d0f3, 0x6c, 0xc8);
+
+ /* DRAM Bus Turn-Around Setting */
+ pci_write_config8(ctrl->d0f3, 0x60, 0x03);
+ /* DRAM Arbitration Control */
+ pci_write_config8(ctrl->d0f3, 0x66, 0x80);
+ /* DQS Tuning: testing on a couple different boards has shown this is
+ * static, or close enough that it can be. Which is good, because the
+ * tuning function used too many registers
+ */
+ /* DQS Output Delay for CHannel A */
+ pci_write_config8(ctrl->d0f3, 0x70, 0x00);
+ /* MD Output Delay for Channel A */
+ pci_write_config8(ctrl->d0f3, 0x71, 0x01);
+ pci_write_config8(ctrl->d0f3, 0x73, 0x01);
+
+ /* dram arbitration timer */
+ pci_write_config8(ctrl->d0f3, 0x65, 0xd9);
+
+ /* dram signal timing control */
+ pci_write_config8(ctrl->d0f3, 0x74, 0x01);
+ pci_write_config8(ctrl->d0f3, 0x75, 0x01);
+ pci_write_config8(ctrl->d0f3, 0x76, 0x06);
+ pci_write_config8(ctrl->d0f3, 0x77, 0x92);
+ pci_write_config8(ctrl->d0f3, 0x78, 0x83);
+ pci_write_config8(ctrl->d0f3, 0x79, 0x83);
+ pci_write_config8(ctrl->d0f3, 0x7a, 0x00);
+ pci_write_config8(ctrl->d0f3, 0x7b, 0x10);
+
+ /* dram clocking control */
+ pci_write_config8(ctrl->d0f3, 0x91, 0x01);
+ /* CS/CKE Clock Phase Control */
+ pci_write_config8(ctrl->d0f3, 0x92, 0x02);
+ /* SCMD/MA Clock Phase Control */
+ pci_write_config8(ctrl->d0f3, 0x93, 0x02);
+ /* DCLKO Feedback Mode Output Control */
+ pci_write_config8(ctrl->d0f3, 0x94, 0x00);
+ pci_write_config8(ctrl->d0f3, 0x9d, 0x0f);
+
+ /* SDRAM ODT Control */
+ pci_write_config8(ctrl->d0f3, 0xda, 0x80);
+ /* Channel A DQ/DQS CKG Output Delay Control */
+ pci_write_config8(ctrl->d0f3, 0xdc, 0x54);
+ /* Channel A DQ/DQS CKG Output Delay Control */
+ pci_write_config8(ctrl->d0f3, 0xdd, 0x55);
+ /* odt lookup table */
+ pci_write_config8(ctrl->d0f3, 0xd8, 0x01);
+ pci_write_config8(ctrl->d0f3, 0xd9, 0x0a);
+
+ /* ddr sdram control */
+ pci_write_config8(ctrl->d0f3, 0x6d, 0xc0);
+ pci_write_config8(ctrl->d0f3, 0x6f, 0x41);
+
/* DQ/DQS Strength Control */
- pci_write_config8(ctrl->d0f3, 0xd0, 0x88);
- pci_write_config8(ctrl->d0f3, 0xd1, 0x8b);
- pci_write_config8(ctrl->d0f3, 0xd2, 0x89);
- /* SMM and APIC Decoding */
- pci_write_config8(ctrl->d0f3, 0x86, 0x2d);
-
- /* Driving selection */
- /* DQ / DQS ODT Driving and Range Select */
+ pci_write_config8(ctrl->d0f3, 0xd0, 0xaa);
+
+ /* Compensation Control */
+ pci_write_config8(ctrl->d0f3, 0xd3, 0x01); /*enable auto compensation*/
+ /* ODT (some are set with driving select above) */
+ pci_write_config8(ctrl->d0f3, 0xd4, 0x80);
pci_write_config8(ctrl->d0f3, 0xd5, 0x8a);
/* Memory Pads Driving and Range Select */
pci_write_config8(ctrl->d0f3, 0xd6, 0xaa);
- /* DRAM Driving – Group DQS */
+
pci_write_config8(ctrl->d0f3, 0xe0, 0xee);
- /* DRAM Driving – Group DQ (DQ, MPD, DQM) */
- pci_write_config8(ctrl->d0f3, 0xe2, 0xac);//ba
- /* DRAM Driving – Group CS */
+ pci_write_config8(ctrl->d0f3, 0xe2, 0xac);
pci_write_config8(ctrl->d0f3, 0xe4, 0x66);
- /* DRAM Driving – Group MA */
+ pci_write_config8(ctrl->d0f3, 0xe6, 0x33);
pci_write_config8(ctrl->d0f3, 0xe8, 0x86);
- /* DRAM Driving – Group MCLK */
- pci_write_config8(ctrl->d0f3, 0xe6, 0xaa);
-
- /* ODT (some are set with driving select above) */
- /* Memory Pad ODT Pullup / Pulldown Control */
- pci_write_config8(ctrl->d0f3, 0xd4, 0x0a);
- /* Memory Ranks ODT Lookup Table */
- pci_write_config8(ctrl->d0f3, 0xd8, 0x00);//was 1
- /* Compensation Control */
- pci_write_config8(ctrl->d0f3, 0xd3, 0x89);//enable auto compensation
-
- /* MCLKO Phase Control */
- pci_write_config8(ctrl->d0f3, 0x91, 0x02);
- /* CS/CKE Clock Phase Control */
- pci_write_config8(ctrl->d0f3, 0x92, 0x06);
- /* SCMD/MA Clock Phase Control */
- pci_write_config8(ctrl->d0f3, 0x93, 0x07);
- /* Channel A DQS Input Capture Range Control */
- pci_write_config8(ctrl->d0f3, 0x78, 0x83);
- /* DQS Input Capture Range Control */
- /* Set in accordance with the BIOS update note */
- pci_write_config8(ctrl->d0f3, 0x7a, 0x00);
- /* DQS Input Delay Offset Control */
- pci_write_config8(ctrl->d0f3, 0x7c, 0x00);
- /* SDRAM ODT Control */
- pci_write_config8(ctrl->d0f3, 0xda, 0x80);
- /* DQ/DQS CKG Output Delay Control - I */
- pci_write_config8(ctrl->d0f3, 0xdc, 0xff);
- /* DQ/DQS CKG Output Delay Control - II */
- pci_write_config8(ctrl->d0f3, 0xdd, 0xff);
/* DQS / DQ CKG Duty Cycle Control */
- pci_write_config8(ctrl->d0f3, 0xec, 0x88);
+ pci_write_config8(ctrl->d0f3, 0xec, 0x00);
/* MCLK Output Duty Control */
pci_write_config8(ctrl->d0f3, 0xee, 0x00);
- pci_write_config8(ctrl->d0f3, 0xed, 0x10);
/* DQS CKG Input Delay Control */
pci_write_config8(ctrl->d0f3, 0xef, 0x10);
-
- pci_write_config8(ctrl->d0f3, 0x77, 0x9d);
- pci_write_config8(ctrl->d0f3, 0x79, 0x83);
- pci_write_config16(ctrl->d0f3, 0x88, 0x0020);
- pci_write_config8(ctrl->d0f4, 0xa7, 0x80);
+ /* dram duty control */
+ pci_write_config8(ctrl->d0f3, 0xed, 0x10);
- /* VLink Control */
- pci_write_config8(ctrl->d0f7, 0xb0, 0x05);
- pci_write_config8(ctrl->d0f7, 0xb1, 0x01);
-
- /* Memory base */
- pci_write_config16(ctrl->d1f0, 0x20, 0xfb00);
- /* Memory limit */
- pci_write_config16(ctrl->d1f0, 0x22, 0xfcf0);
- /* Prefetch memory base */
- pci_write_config16(ctrl->d1f0, 0x24, 0xf400);
- /* Prefetch memory limit */
- pci_write_config16(ctrl->d1f0, 0x26, 0xf7f0);
- /* PCI to PCI bridge control */
- pci_write_config16(ctrl->d1f0, 0x3e, 0x0008);
-
- /* CPU to PCI flow control 1 */
- pci_write_config8(ctrl->d1f0, 0x40, 0x83);
- pci_write_config8(ctrl->d1f0, 0x41, 0xc3);//clear reset error, set to 43
- pci_write_config8(ctrl->d1f0, 0x42, 0xe2);
- pci_write_config8(ctrl->d1f0, 0x43, 0x44);
- pci_write_config8(ctrl->d1f0, 0x44, 0x34);
- pci_write_config8(ctrl->d1f0, 0x45, 0x72);
+ /* SMM and APIC deocoding, we donot use SMM */
+ reg = 0x29;
+ pci_write_config8(ctrl->d0f3, 0x86, reg);
+ /* SMM and APIC decoding mirror */
+ pci_write_config8(ctrl->d0f7, 0xe6, reg);
- /* Disable cross bank/multi page mode */
- pci_write_config8(ctrl->d0f3, DDR_PAGE_CTL, 0x80);
- pci_write_config8(ctrl->d0f3, DRAM_REFRESH_COUNTER, 0x00);
-
- /* Set WR=5 and RFC */
- pci_write_config8(ctrl->d0f3, 0x61, 0xc7);
- /* Set CAS=5 */
- pci_write_config8(ctrl->d0f3, 0x62, 0xaf);
- pci_write_config8(ctrl->d0f3, 0x63, 0xca);
- /* Set to DDR2 sdram, BL=8 (0xc8, 0xc0 for bl=4) */
- pci_write_config8(ctrl->d0f3, 0x6c, 0xc8);
- /* Allow manual dll reset */
- pci_write_config8(ctrl->d0f3, 0x6b, 0x10);
-
+ /* dram module configuration */
pci_write_config8(ctrl->d0f3, 0x6e, 0x89);
- pci_write_config8(ctrl->d0f3, 0x67, 0x50);
- pci_write_config8(ctrl->d0f3, 0x65, 0xd9);
-
- /* Only enable bank 1, for now */
- /* TODO: Multiple, dynamically controlled bank enables */
- pci_write_config8(ctrl->d0f3, 0x54, 0x80);
- pci_write_config8(ctrl->d0f3, 0x55, 0x00);
-
- /* Set to 2T, MA Map type 1.
- * TODO: Needs to become dynamic */
- pci_write_config16(ctrl->d0f3, 0x50, 0x0020);
+}
- /* BA0-2 Selection. Don't mess with */
- pci_write_config8(ctrl->d0f3, 0x52, 0x33);
- pci_write_config8(ctrl->d0f3, 0x53, 0x3f);
-
- /* Disable bank interleaving. This feature seems useless anyways */
- pci_write_config32(ctrl->d0f3, 0x58, 0x00000000);
- pci_write_config8(ctrl->d0f3, 0x88, 0x08);
+static void sdram_set_post(const struct mem_controller *ctrl)
+{
+ device_t dev = ctrl->d0f3;
+ /* Enable multipage mode. */
+ pci_write_config8(dev, 0x69, 0x03);
- /* Some DQS control stuffs */
- pci_write_config8(ctrl->d0f3, 0x74, 0x04);
- pci_write_config8(ctrl->d0f3, 0x75, 0x04);
- pci_write_config8(ctrl->d0f3, 0x76, 0x00);
-}
+ /* Enable refresh. */
+ pci_write_config8(dev, 0x6a, 0x32);
-/**
- * Set up dram size according to spd data. Eventually, DRAM timings should be
- * done in a similar manner.
- *
- * @param ctrl The northbridge devices and spd addresses.
- */
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
-{
- u8 spd_data, spd_data2;
+ // vga device
+ pci_write_config16(dev, 0xa0, (1 <<15));
+ pci_write_config16(dev, 0xa4, 0x0010);
- /* DRAM Bank Size */
- spd_data = spd_read_byte(ctrl->channel0[0],
- SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
- /* I know this seems weird. Blame JEDEC/Via. */
- if(spd_data >= 0x10)
- spd_data = spd_data >> 1;
- else
- spd_data = spd_data << 1;
-
- /* Check for double sided dimm and adjust size accordingly */
- spd_data2 = spd_read_byte(ctrl->channel0[0], SPD_NUM_BANKS_PER_SDRAM);
- /* There should be 4 banks on a single sided dimm,
- * or 8 on a dual sided one */
- spd_data = spd_data * (spd_data2 / 4);
- pci_write_config8(ctrl->d0f3, 0x40, spd_data);
- /* TODO: The rest of the DIMMs */
}
-static void sdram_enable(device_t dev)
+static void sdram_enable(device_t dev, unsigned long rank_address)
{
- int i;
+ u8 i;
/* 1. Apply NOP. */
PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\r\n");
- do_ram_command(dev, RAM_COMMAND_NOP, 0);
- udelay(200);
+ do_ram_command(dev, RAM_COMMAND_NOP);
+ udelay(100);
+ read32(rank_address + 0x10);
/* 2. Precharge all. */
+ udelay(400);
PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
- do_ram_command(dev, RAM_COMMAND_PRECHARGE, 0);
+ do_ram_command(dev, RAM_COMMAND_PRECHARGE);
+ read32(rank_address + 0x10);
/* 3. Mode register set. */
PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
- do_ram_command(dev, RAM_COMMAND_MRS, 0x2000);//enable dll
- do_ram_command(dev, RAM_COMMAND_MRS, 0x800);//reset dll
+ do_ram_command(dev, RAM_COMMAND_MRS);
+ read32(rank_address + 0x120000);// EMRS DLL Enable
+ read32(rank_address + 0x800); // MRS DLL Reset
/* 4. Precharge all again. */
PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
- do_ram_command(dev, RAM_COMMAND_PRECHARGE, 0);
+ do_ram_command(dev, RAM_COMMAND_PRECHARGE);
+ read32(rank_address + 0x0);
/* 5. Perform 8 refresh cycles. Wait tRC each time. */
PRINT_DEBUG_MEM("RAM Enable 3: CBR\r\n");
- do_ram_command(dev, RAM_COMMAND_CBR, 0);
- /* First read is actually done by do_ram_command */
- for(i = 0; i < 7; i++) {
+ do_ram_command(dev, RAM_COMMAND_CBR);
+ for(i = 0; i < 8; i++) {
+ read32(rank_address + 0x20);
udelay(100);
- read32(0);
}
/* 6. Mode register set. */
PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
- //safe value for now, BL=8, WR=5, CAS=5
+ //safe value for now, BL=8, WR=5, CAS=4
/* (E)MRS values are from the BPG. No direct explanation is given, but
* they should somehow conform to the JEDEC DDR2 SDRAM Specification
* (JESD79-2C). */
- do_ram_command(dev, RAM_COMMAND_MRS, 0x0022d8);
+ do_ram_command(dev, RAM_COMMAND_MRS);
+ read32(rank_address + 0x002258); // MRS command
+ read32(rank_address + 0x121c20); // EMRS OCD Default
+ read32(rank_address + 0x120020); // EMRS OCD Calibration Mode Exit
- /* 7. Mode register set. */
- PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
- do_ram_command(dev, RAM_COMMAND_MRS, 0x21c20);//default OCD calibration
- do_ram_command(dev, RAM_COMMAND_MRS, 0x20020);//exit calibration mode
-
/* 8. Normal operation */
PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n");
- do_ram_command(dev, RAM_COMMAND_NORMAL, 0);
-
- /* Enable multipage mode. */
- pci_write_config8(dev, DDR_PAGE_CTL, 0x83);
- /* Enable refresh. */
- pci_write_config8(dev, DRAM_REFRESH_COUNTER, 0x32);
-
- /* DQS Tuning: testing on a couple different boards has shown this is
- * static, or close enough that it can be. Which is good, because the
- * tuning function used too many registers. */
- pci_write_config8(dev, CH_A_DQS_OUTPUT_DELAY, 0x00);
- pci_write_config8(dev, CH_A_MD_OUTPUT_DELAY, 0x03);
+ do_ram_command(dev, RAM_COMMAND_NORMAL);
+ read32(rank_address + 0x30);
+}
- /* Enable VGA device with no memory, add memory later. We need this
- * here to enable the actual device, otherwise it won't show up until
- * later and LB will have a fit. */
- pci_write_config16(dev, 0xa0, (1 << 15));
- pci_write_config16(dev, 0xa4, 0x0010);
+/*
+ * Support one dimm with up to 2 ranks
+ */
+static void ddr_ram_setup(const struct mem_controller *ctrl)
+{
+ u8 reg;
+
+ c7_cpu_setup(ctrl->d0f2);
+ sdram_set_registers(ctrl);
+ sdram_set_size(ctrl);
+ sdram_enable(ctrl->d0f3, 0);
+ reg = pci_read_config8(ctrl->d0f3, 0x41);
+ if (reg != 0)
+ sdram_enable(ctrl->d0f3, pci_read_config8(ctrl->d0f3, 0x40) << 26);
+ sdram_set_post(ctrl);
}
+
Added: trunk/coreboot-v2/targets/via/epia-cn/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/via/epia-cn/Config.lb (rev 0)
+++ trunk/coreboot-v2/targets/via/epia-cn/Config.lb 2008-05-19 12:17:43 UTC (rev 3334)
@@ -0,0 +1,36 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 VIA Technologies, Inc.
+## (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+target via_epia_cn
+mainboard via/epia-cn
+
+#
+# Generate the final ROM like this:
+# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
+#
+option ROM_SIZE = (512 * 1024) - (64 * 1024) - (64 * 1024)
+
+romimage "image"
+ option COREBOOT_EXTRA_VERSION = "-epiacn"
+ payload ../payload.elf
+end
+
+buildrom ./coreboot.rom ROM_SIZE "image"
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