[coreboot] ram init help on the i82830

Joseph Smith joe at settoplinux.org
Wed May 28 04:27:39 CEST 2008


Hello,
Now that I got coreboot running on the IP1000, I finally am able to test
out the so-dimm socket. I maxed out the slot with a big 512MB so-dimm. I
don't think the "for" statement we came up with is working correctly:

	/* NOTE: Dual-sided ready. */
	read32(0 + addr_offset);
	for (i = 0; i < 4; i++) {
		reg8 = pci_read_config8(ctrl->d0, DRB + i);
		if (reg8 != reg8_2)
			read32(reg8 * 32 * 1024 * 1024);
		reg8_2 = reg8;
	}

The memory is detecting correctly, but I don't think coreboot can find the
end of the side of the so-dimm, thus causing a lockup after Jumping to
coreboot. I think I need to setup something more like the E7501
do_ram_command() but I want to keep it simple. Here is the bootlog, Help??

coreboot-2.0.0_IP1000 Tue May 27 21:18:23 EDT 2008 starting...
Setting initial registers....
Initial registers have been set.
Found DIMM in slot 00
DIMM is 0x0100 on side 1
DIMM is 0x0100 on side 2
DRB 0x60 has been set to 0x08
DRB1 0x61 has been set to 0x10
Found DIMM in slot 01
DIMM is 0x0040 on side 1
DIMM is 0x0000 on side 2
DRB2 0x62 has been set to 0x12
DRB3 0x63 has been set to 0x12
Found DIMM in slot 00, setting DRA...
DRA 0x70 has been set to 0x08
Found DIMM in slot 01, setting DRA...
DRA 0x71 has been set to 0xf1
RAM Enable 1: Apply NOP
    Sending RAM command 0x00000010 to 0x00000000
RAM Enable 2: Precharge all
    Sending RAM command 0x00000020 to 0x00000000
RAM Enable 3: CBR
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x00000000
RAM Enable 4: Mode register set
    Sending RAM command 0x00000030 to 0x000001d0
RAM Enable 5: Normal operation
    Sending RAM command 0x20000270 to 0x00000000
Northbridge following SDRAM init:
PCI: 00:00.00
00: 86 80 75 35 06 00 10 20 04 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e
50: 72 a0 40 00 00 00 00 00 00 30 33 33 33 33 33 33
60: 08 10 12 12 12 12 00 00 00 00 00 00 00 00 00 00
70: 08 f1 ff ff 00 00 00 00 10 00 00 00 70 02 00 20
80: 00 00 00 00 00 00 00 00 80 60 33 09 00 00 00 00
90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 1b 49 9b fc
f0: 11 11 01 00 00 00 0b 05 35 d0 2c cf 22 cd 1d cc
Copying coreboot to RAM.
Jumping to coreboot.

<----LOCKS UP HERE---->

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org





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