[coreboot] r3724 - trunk/coreboot-v2/src/mainboard/via/epia-cn

[svn at coreboot.org]

Author: rminnich
Date: 2008-11-03 05:08:35 +0100 (Mon, 03 Nov 2008)
New Revision: 3724

Modified:
   trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c
Log:
modify pirq tables for epia-cn.

Not tested, builds, derived from getpir. Definitely better than what was there. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Bari Ari <bari at onelabs.com>


Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb	2008-11-03 00:20:22 UTC (rev 3723)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb	2008-11-03 04:08:35 UTC (rev 3724)
@@ -81,7 +81,7 @@
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
 default HAVE_HARD_RESET = 0
 default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 10
+default IRQ_SLOT_COUNT = 9
 default HAVE_ACPI_TABLES = 0
 default HAVE_OPTION_TABLE = 1
 default ROM_IMAGE_SIZE = 64 * 1024

Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c	2008-11-03 00:20:22 UTC (rev 3723)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c	2008-11-03 04:08:35 UTC (rev 3724)
@@ -27,24 +27,23 @@
 	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x11 << 3) | 0x0,	/* Interrupt router device */
-	0x828,			/* IRQs devoted exclusively to PCI usage */
+	0xc20,			/* IRQs devoted exclusively to PCI usage */
 	0x1106,			/* Vendor */
 	0x596,			/* Device */
 	0,			/* Crap (miniport) */
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x3e,			/* Checksum */
+	0x66,			/* Checksum */
 	{
 		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
-		{0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
-		{0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
-		{0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
-		{0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
-		{0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
-		{0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
-		{0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
-		{0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
-		{0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
+		{0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
+		{0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0},
+		{0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0},
+		{0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x4, 0x0},
+		{0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
 	}
 };