[coreboot] Artec Group Dongle II cvs is up on opencores.org

jyrit jyrit at artecdesign.ee
Tue Nov 4 20:27:37 CET 2008

Peter Stuge <peter <at> stuge.se> writes:
> Not so impressed with the (lack of) hardware improvements. :\

There is actually lot of thought put in into the hardware to
get all the requested features with small changes.
The write time of 4 MByte image to added PSRAM is now 4 sec. (using the same
FTDI chip this prob. can be reduced to about 2 sec. with VHDL tweaks). 
The "BitBang" mode of the FTDI chip makes it possible to update the firmware
without any need for ByteBlaster cable.
There is UltraCap so that the PSRAM retains it's image up to 2 hours. :)

There is automatic power switch now.
There is EPROM to make it possible to remove the physical jumpers.
There are SMD leds

Cyclone III has faster up time than Cyclone I but it still might not be fast
enough. On the other hand there is the existing updater code that can be
reused and Cyclone III is cheaper than Actel FPGA's and there are other
reasons why we went with Cyclone III.

That's all that was on the Santa's list for Peter :D

All the best,

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