[coreboot] [PATCH] CN700/VT8237R stage2
corey.osgood at gmail.com
Wed Nov 5 06:17:51 CET 2008
On Wed, Nov 5, 2008 at 12:07 AM, Carl-Daniel Hailfinger <
c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 05.11.2008 06:03, Carl-Daniel Hailfinger wrote:
> > On 05.11.2008 05:58, ron minnich wrote:
> >> On Tue, Nov 4, 2008 at 8:29 PM, Corey Osgood <corey.osgood at gmail.com>
> >>> That did the trick!
> >> So where do we stand on the via and v3?
> > I'd say the CAR code (both enable and disable) is complete and perfect
> > Corey knows about the other stuff.
> > Does anybody have a VIA Nano board where he can try the stage1 code?
> > Using the jetway target with minor adjustments for SuperIO should give
> > serial output. And if serial output works, we know the CAR code is OK
> > for the Nano. That would certainly be a welcome event.
> > Similar tests appreciated for VIA C3 and anything else you can lay your
> > hands on.
> The reason why I'm asking for this is simple: Give people serial output
> and they feel success even if lots of stuff is still to be done. That's
> an important motivator and one of the areas where v3 can shine due to
> its structure.
cn700 & v3: if you comment out vt8237_enable()'s content in vt8237.c, it
might boot a payload, I'm tracking down the problem there right now. I don't
think we can use eg dev->pci.id.vendor in stage2.phase2? I want to clean
that up by the end of the night.
other cpus: I've got a Nehemiah C3 board here I'll try at some point, but
I'm focusing on c7 atm. I think the CPU is too different there, but I could
be wrong. If anyone wants to give me a Nano board, I'll try it out :D
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the coreboot