[coreboot] [PATCH] flashrom: sector-based flashing

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Wed Nov 5 12:01:11 CET 2008

On 05.11.2008 10:21, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>> @@ -64,6 +69,7 @@
>>  	int total_size;
>>  	int page_size;
>> +	struct eraseblock eraseblocks[4];
> I don't know.. What about chips with more blocks than 4?

No problem. Let me quote another part of the patch.

>> +struct eraseblock{
>> +	int size; /* Eraseblock size */
>> +	int count; /* Number of contiguous blocks with that size */
>> +};

struct eraseblock doesn't correspond with a single erase block, but with
a group of contiguous erase blocks having the same size.
Given a (top boot block) flash chip with the following weird, but
real-life structure:


we get the following encoding:

Although the number of blocks is bigger than 4, the number of block
groups is only 4. If you ever add some flash chips with more than 4
contiguous block groups, the definition will not fit into the 4-member
array anymore and gcc will recognize that and error out. No undetected
overflow possible. In that case, you simply increase array size a bit.
For modern flash chips with uniform erase block size, you only need one
array member anyway.

Of course data types will need to be changed if you ever get flash chips
with more than 2^30 erase blocks, but even with the lowest known erase
granularity of 256 bytes, these flash chips will have to have a size of
a quarter Terabyte. I'm pretty confident we won't see such big EEPROMs
in the near future (or at least not attached in a way that makes
flashrom usable). For SPI chips, we even have a guaranteed safety factor
of 4096 over the maximum SPI chip size (which is 2^24).
And if such a big flash chip has uniform erase block size, you could
even split it among the 4 array members. If you change int count to
unsigned int count, the storable size doubles. So with a split and a
slight change of data type, the maximum ROM chip size is 2 Terabytes.



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