[coreboot] Max pci bus number?
kevin at koconnor.net
Sun Nov 9 22:07:59 CET 2008
On Sun, Nov 09, 2008 at 12:03:38PM +0100, Stefan Reinauer wrote:
> On 09.11.2008, at 03:52, Kevin O'Connor <kevin at koconnor.net> wrote:
>> Right now, SeaBIOS has a compile time definition for the max, but that
>> is awkward and it can lead to hard to debug failures.
> Yes, look at coreinfo. The idea is to start at bus 0 and whenever you
> see a bridge, iterate over it's secondary bus. This way you get all
> devices but never scan a single bus too much.
Thanks for the hint. I've added max bus detection to the latest
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