[coreboot] Resource allocation
marcj303 at yahoo.com
Tue Nov 11 18:56:33 CET 2008
----- Original Message ----
> From: Myles Watson <mylesgw at gmail.com>
> To: Marc Jones <marcj303 at yahoo.com>; Coreboot <coreboot at coreboot.org>; ron minnich <rminnich at gmail.com>
> Sent: Tuesday, November 11, 2008 10:33:47 AM
> Subject: RE: [coreboot] Resource allocation
> > > All right. So the legacy IO resources shouldn't be grouped with the
> > others.
> > > Should they be marked Subtractive? Are they declared to be special in a
> > > different way?
> > Yes but those legacy addresses could be positively decoded anywhere along
> > the subtractive path. They will usually go as far as the chipset with an
> > integrated controller. So, if someone put a legacy IDE controller farther
> > on the path it (like lpc) it would never get the IO. For completeness in
> > the dts you could have all the addresses in the system but I don't know if
> > it is that important. I guess we need to add legacy io reserve code to the
> > chipsets similar to the SIOs.
> Thanks for the help; sorry to be dense. Could we flesh this out a little
> The problem I'm having is that the SuperIO is declaring several resources,
> some of which are below the 0x1000 threshold, and some of which are not.
> They are all declared to be IO, so they need to fit in the same bridge
> resource, and can't. If they were a different type, or if they were ignored
> by the resource code, it could still work.
> I understand that the subtractive decode and VGA bits need to be set on the
> bridge (amd8111), but I don't know how we protect the legacy IDE area if
> someone added an IDE card to the PCI bus of the amd8111.
Legacy can be completely ignored by the bridges. As long as the device is on the subtractive path(which an sio should be) it will get the cycles so those cycles can also be ignored by bridges. The question is how they are handled in the dts. Do we care to track those addresses there? I think so since that is the point. So, PCI bridges ignore legacy/subtractive decode io ranges (and technically memory ranges as well) and the dts understands them, maybe check for an overlap and prints warning. No other action is needed. In the case of IDE. If a card is added in front of the 8111 and positivly decodes the legacy range, the 8111 will never get the cycles. This is not a problem for coreboot as there isn't anything we can do about it. This is very very unlikely. Most PCI addin cards don't decode legacy ranges for this reason. They assume tha there is a legacy device on the subtractive bus and do everything in PCI native mode.
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