[coreboot] Resource allocation

[Peter Stuge]

Marc Jones wrote:
> Legacy can be completely ignored by the bridges. As long as the
> device is on the subtractive path(which an sio should be) it will
> get the cycles so those cycles can also be ignored by bridges. The
> question is how they are handled in the dts. Do we care to track
> those addresses there? I think so since that is the point.

We must - so that we do not allocate conflicting resources to other
devices.

We might also want to make sure that we never change the subtractive
decoding. Maybe hardware doesn't even allow that?


> So, PCI bridges ignore legacy/subtractive decode io ranges (and
> technically memory ranges as well) and the dts understands them,
> maybe check for an overlap and prints warning. No other action is
> needed.

Again, we should exclude them from available resources so that the
allocator algorithm can not use them, even if by bug.


> In the case of IDE. If a card is added in front of the 8111 and
> positivly decodes the legacy range, the 8111 will never get the
> cycles. This is not a problem for coreboot as there isn't anything
> we can do about it. This is very very unlikely. Most PCI addin
> cards don't decode legacy ranges for this reason.

But they could still be configured to do so, right? Would such an IDE
card not accept config cycles?


> They assume tha there is a legacy device on the subtractive bus and
> do everything in PCI native mode.

At least something moves away from legacy. :)


//Peter