[coreboot] Resource allocation
mylesgw at gmail.com
Tue Nov 11 20:20:54 CET 2008
> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Peter Stuge
> Sent: Tuesday, November 11, 2008 11:12 AM
> To: Coreboot
> Subject: Re: [coreboot] Resource allocation
> Marc Jones wrote:
> > Legacy can be completely ignored by the bridges. As long as the
> > device is on the subtractive path(which an sio should be) it will
> > get the cycles so those cycles can also be ignored by bridges. The
> > question is how they are handled in the dts. Do we care to track
> > those addresses there? I think so since that is the point.
> We must - so that we do not allocate conflicting resources to other
> We might also want to make sure that we never change the subtractive
> decoding. Maybe hardware doesn't even allow that?
> > So, PCI bridges ignore legacy/subtractive decode io ranges (and
> > technically memory ranges as well) and the dts understands them,
> > maybe check for an overlap and prints warning. No other action is
> > needed.
> Again, we should exclude them from available resources so that the
> allocator algorithm can not use them, even if by bug.
> > In the case of IDE. If a card is added in front of the 8111 and
> > positivly decodes the legacy range, the 8111 will never get the
> > cycles. This is not a problem for coreboot as there isn't anything
> > we can do about it. This is very very unlikely. Most PCI addin
> > cards don't decode legacy ranges for this reason.
> But they could still be configured to do so, right? Would such an IDE
> card not accept config cycles?
My understanding is that their BARs would be too large to allow them to be
allocated at 0x3xx.
Can we try a concrete example?
Opteron -> 8111 -> 8111lpc -> Winbond SuperIO
The SuperIO has resources like this:
PNP 2e.0: size 8 align 3 gran 3 limit 7ff flags 100 index 60
- IO resource that has to be allocated below 7ff
PNP 2e.5: size 1 align 0 gran 0 limit ffffffff flags 60000100 index
- IO resource that has to be allocated below ffffffff
Then does the 8111lpc need to have an IO subtractive resource? the 8111? the
Are either of them supposed to be positively decoded by the bridge, or
should we let them both live under 7ff? What code takes care of this? What
code makes sure that these resources don't conflict?
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