[coreboot] r1008 - in coreboot-v3: arch/x86/intel/core2 mainboard/kontron/986lcd-m northbridge/intel/i945 southbridge/intel/i82801gx

svn at coreboot.org svn at coreboot.org
Wed Nov 12 23:43:50 CET 2008


Author: rminnich
Date: 2008-11-12 23:43:50 +0100 (Wed, 12 Nov 2008)
New Revision: 1008

Modified:
   coreboot-v3/arch/x86/intel/core2/stage0.S
   coreboot-v3/mainboard/kontron/986lcd-m/Makefile
   coreboot-v3/northbridge/intel/i945/Makefile
   coreboot-v3/northbridge/intel/i945/northbridge.c
   coreboot-v3/southbridge/intel/i82801gx/Makefile
   coreboot-v3/southbridge/intel/i82801gx/usb.c
Log:
I'm committing often as I don't want people to run over each other (and I am waiting on BlueGene to schedule me
and keep getting called away ... waiting for 1024 procs takes patience!)

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/arch/x86/intel/core2/stage0.S
===================================================================
--- coreboot-v3/arch/x86/intel/core2/stage0.S	2008-11-12 22:23:46 UTC (rev 1007)
+++ coreboot-v3/arch/x86/intel/core2/stage0.S	2008-11-12 22:43:50 UTC (rev 1008)
@@ -18,12 +18,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE
-#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE
-#define post_code(x) intel_chip_post_macro(x)
+#define ASSEMBLY
+#define CACHE_AS_RAM_SIZE CONFIG_CARSIZE
+#define CACHE_AS_RAM_BASE CONFIG_CARBASE
 
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/mtrr.h>
+#include <mtrr.h>
 
 #include <macros.h>
 
@@ -67,7 +66,7 @@
 cache_as_ram:
 #if USE_FALLBACK_IMAGE == 1
 
-	post_code(0x20)
+	port80_post(0x20)
 
 	/* Send INIT IPI to all excluding ourself */
         movl	$0x000C4500, %eax
@@ -164,11 +163,11 @@
 	movl	%esp, %ebp
 	pushl	%eax
 
-	post_code(0x23)
+	port80_post(0x23)
 
 	call	stage1_phase1
 
-	post_code(0x2f)
+	port80_post(0x2f)
 error:
 	hlt
 	jmp	error

Modified: coreboot-v3/mainboard/kontron/986lcd-m/Makefile
===================================================================
--- coreboot-v3/mainboard/kontron/986lcd-m/Makefile	2008-11-12 22:23:46 UTC (rev 1007)
+++ coreboot-v3/mainboard/kontron/986lcd-m/Makefile	2008-11-12 22:43:50 UTC (rev 1008)
@@ -26,7 +26,7 @@
 			
 
 INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
-			$(src)/northbridge/northbridge/intel/i945/raminit.c \
+			$(src)/northbridge/intel/i945/raminit.c \
 
 
 STAGE2_MAINBOARD_SRC = 

Modified: coreboot-v3/northbridge/intel/i945/Makefile
===================================================================
--- coreboot-v3/northbridge/intel/i945/Makefile	2008-11-12 22:23:46 UTC (rev 1007)
+++ coreboot-v3/northbridge/intel/i945/Makefile	2008-11-12 22:43:50 UTC (rev 1008)
@@ -21,11 +21,6 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y)
 
-STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i945/get_sblk_pci1234.c \
-					$(src)/northbridge/intel/i945/common.c \
-					$(src)/northbridge/intel/i945/cpu.c \
-					$(src)/northbridge/intel/i945/domain.c \
-					$(src)/northbridge/intel/i945/pci.c \
-					$(src)/northbridge/intel/i945/util.c
+STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i945/northbridge.c \
 
 endif

Modified: coreboot-v3/northbridge/intel/i945/northbridge.c
===================================================================
--- coreboot-v3/northbridge/intel/i945/northbridge.c	2008-11-12 22:23:46 UTC (rev 1007)
+++ coreboot-v3/northbridge/intel/i945/northbridge.c	2008-11-12 22:43:50 UTC (rev 1008)
@@ -259,10 +259,11 @@
 {
 }
 
+#warning get a number of the 945 mc
 struct device_operations i945_mc_ops = {
 	.id = {.type = DEVICE_ID_PCI,
 		{.pci = {.vendor = PCI_VENDOR_ID_INTEL,
-			      .device = anu,ber}}},
+			      .device = 0x1233}}},
 	.constructor		 = default_device_constructor,
 	.phase4_read_resources	 = cpu_bus_noop,
 	.phase4_set_resources	 = cpu_bus_noop,

Modified: coreboot-v3/southbridge/intel/i82801gx/Makefile
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/Makefile	2008-11-12 22:23:46 UTC (rev 1007)
+++ coreboot-v3/southbridge/intel/i82801gx/Makefile	2008-11-12 22:43:50 UTC (rev 1008)
@@ -32,13 +32,13 @@
 					$(src)/southbridge/intel/i82801gx/pcie.c \
 					$(src)/southbridge/intel/i82801gx/sata.c \
 					$(src)/southbridge/intel/i82801gx/smbus.c \
-					$(src)/southbridge/intel/i82801gx/libsmbus.c \
 					$(src)/southbridge/intel/i82801gx/usb_ehci.c \
   					$(src)/southbridge/intel/i82801gx/usb.c	\
   					$(src)/southbridge/intel/i82801gx/watchdog.c
+#					$(src)/southbridge/intel/i82801gx/libsmbus.c \
 					
 STAGE0_CHIPSET_SRC += \
 					$(src)/southbridge/intel/i82801gx/stage1_smbus.c \
-					$(src)/southbridge/intel/i82801gx/libsmbus.c \
+#					$(src)/southbridge/intel/i82801gx/libsmbus.c \
 
 endif

Modified: coreboot-v3/southbridge/intel/i82801gx/usb.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/usb.c	2008-11-12 22:23:46 UTC (rev 1007)
+++ coreboot-v3/southbridge/intel/i82801gx/usb.c	2008-11-12 22:43:50 UTC (rev 1008)
@@ -46,6 +46,7 @@
 
 	printk(BIOS_DEBUG, "done.\n");
 }
+void i82801gx_enable(struct device * dev);
 
 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
 struct device_operations i82801gb_usb1 = {





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