[coreboot] Spi flash

[Dupont Yves]

Hi Carl-Daneil,

Thanks for your help, could you tell me what is REMS?
regards,

Yves

2008/11/13 Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

> Hi Yves,
>
> please keep the list in CC so they know what's going on. Thanks.
>
> On 13.11.2008 18:51, Dupont Yves wrote:
> > here is the corresponding dump :
> >
> > Calibrating delay loop... 326M loops per second, 100 myus = 193 us. OK.
> > No coreboot table found.
> > Found chipset "Intel ICH7M", enabling flash write...
> > BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1
> >
> > Root Complex Register Block address = 0xfed1c000
> > GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1
> (SPI)
> > [...]
> > SPI Read Configuration: prefetching disabled, caching enabled, OK.
> > [...]
> > Probing for Atmel AT25DF321, 4096 KB: Programming OPCODES... done
> > RDID returned ff ff ff.
> >
>
> The flash chip doesn't support RDID.
>
> > RDID byte 0 parity violation.
> > probe_spi_rdid_generic: id1 0xff, id2 0xffff
> > [...]
> > Probing for ST M25P40-old, 512 KB: RDID returned ff ff ff.
> > RES returned 13.
> >
>
> But the chip supports RES.
>
> > probe_spi_res: id 0x13
> > [....]
> > No EEPROM/flash device found.
> >
>
> The big problem is that ~30 chips from different manufacturers with
> different sizes all have the same RES ID. I will try to cook up a patch
> checking REMS (which is more accurate).
>
> > It seems to bea SPI flash device but I don't want to open my laptop.
> > Any idea?
> >
>
> I will create a patch to improve detection, but that may take a week or
> so. If you don't hear anything back from me in the next 7 days, please
> ask me for a status.
>
>
> Regards,
> Carl-Daniel
>
> --
> http://www.hailfinger.org/
>
>
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