[coreboot] How to find out "page size" of a flash chip?

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Wed Nov 19 13:34:19 CET 2008

On 19.11.2008 07:50, Peter Stuge wrote:
> Hello Yu Ning,
> FENG Yu Ning wrote:
>> Questions:
>> 1. How do we decide the page-sizes of other SST(and other vendors)
>> flash chips, which have no page mechanism?
> The page_size member is considered an eraseblock size by the code.

Sorry, that is incorrect.

>> 2. Since we operate the flash chips (in case of ich) with
>> ich_spi_read/write, which in turn call ich_spi_read/write_page,
>> what happens to those chips without a page-read/write operation? I
>> am going to investigate the source code and data sheets further,
>> but it is appreciated if anyone familiar with this tell me directly
>> (and it would guide me through the investigation).
> As you may have found, the code is pretty ugly overall. In the case
> of ichspi, read_page and write_page simply assume that it is possible
> to read or write all of page_size bytes in a loop.
> Other SPI "bus" drivers work differently, but page_size is always
> assumed to describe an eraseblock size.

On ICH SPI, page_size is the maximum number of bytes you can write and
read in one operation. ICH SPI hardcodes eraseblock size to 4k. ITE SPI
is different.

I sent a patch to use explicit erase block sizes, but that patch does
not have any Ack yet.



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