[coreboot] How to find out "page size" of a flash chip?

[FENG Yu Ning]

On 11/19/08, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 19.11.2008 07:50, Peter Stuge wrote:
>> The page_size member is considered an eraseblock size by the code.
>
> Sorry, that is incorrect.
>
> On ICH SPI, page_size is the maximum number of bytes you can write and
> read in one operation.

I have just read related part of ichspi.c carefully. The conclusion
is, in the ich7 part of ichspi.c(I have not investigated others),
page_size is neither erase-block size, nor the maximum number of data
bytes per operaion. It is simply meaningless.

Carl-Daniel, I think the variable fitting your explanation would be maxdata.

> ICH SPI hardcodes eraseblock size to 64k.

If we can use block erase, things should look better. I have a
motherboard here - intel D945PLRN, which has i945PL,ich7, and
SST25LF040A(it explains why I keep asking questions about intel
chipsets and SST). That SST spi flash chip uses 52h as block erasing
instruction instead of d6h, and the block size is 32k.

Carl-Daniel, are you working on that? If not, I would like to have a
try, only I seldom do coding and don't know whether I am capable.

yu ning