[coreboot] v3 CAR/ROM area collision on C7 and Core2Duo

[JasonZhao at viatech.com.cn]

FECC_0000 to FECC_00FF is used by VIA I/O APIC in
NB(P4M890,CN896,VX8000...) (It also use 0xFECX_YZ00,but X default =0Ch)
E000_0000_? is MMIO for PCI-E's Extended Configuration Space

SMI handler:may locate at CSEG or HSEG or TSEG (mostly use) SMI-CSEG
	A0000h-BFFFFh (128KB)
HSEG
	FEEA0000h-FEEBFFFFh
TSEG
	MEMTOP-1MB-MEMTOP (1M size)

> -----Original Message-----
> From: Carl-Daniel Hailfinger
[mailto:c-d.hailfinger.devel.2006 at gmx.net]
> Sent: Friday, November 28, 2008 12:08 AM
> To: Rudolf Marek
> Cc: coreboot at coreboot.org; Jason Zhao
> Subject: Re: [coreboot] v3 CAR/ROM area collision on C7 and Core2Duo
> 
> On 26.11.2008 23:02, Rudolf Marek wrote:
> >> 0xFEC00000 as well. That location is 20 MB below 4GB and the lowest
> >
> > 0xFEC0_0000 may be fixed location IO APIC. Other possible locations
> > are 0xFECX_YZ00 (not that 0xFEC cannot be changed)
> > 0xFEEx_xxxx are internal APIC cycles for IRQ (MSI)
> >
> > FEC0_0000 - FEC7_FFFF VIA APIC in SB (fixed)
> > (FEC8_0000 - FECB_FFFF -VIA VPXII APIC)
> >
> > FED4_4000 - FED4_FFFF trusted platform module MEM decode (fixed)
> 
> Thanks, I added this information to a wiki page. The wiki page is
> incomplete, feel free to extend it.
> http://www.coreboot.org/Memory_map
> 
> Regards,
> Carl-Daniel
> 
> --
> http://www.hailfinger.org/