From svn at coreboot.org  Wed Oct  1 08:47:52 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Oct 2008 08:47:52 +0200
Subject: [coreboot] r876 - in coreboot-v3: device include/device
	mainboard/gigabyte/m57sli southbridge/nvidia/mcp55
	superio/ite/it8716f
Message-ID: <mailman.2145.1355071389.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-10-01 08:47:51 +0200 (Wed, 01 Oct 2008)
New Revision: 876

Added:
   coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h
Modified:
   coreboot-v3/device/pnp_raw.c
   coreboot-v3/include/device/pnp.h
   coreboot-v3/mainboard/gigabyte/m57sli/Makefile
   coreboot-v3/mainboard/gigabyte/m57sli/initram.c
   coreboot-v3/mainboard/gigabyte/m57sli/stage1.c
   coreboot-v3/southbridge/nvidia/mcp55/stage1.c
   coreboot-v3/superio/ite/it8716f/it8716f.h
Log:
Bringing the m57sli to life. This includes changes to mcp55 and 
mainboard that we learned with the serengeti that we needed. New 
function in pnp that is for reading. new prototype in pnp.h. New 
constants for ite8716f. 

This board does not build yet; we are exercising code in k8 north that
the serengeti did not enable. More tomorrow. 

Now that we have two boards under way we can hopefully see our way to 
getting more put in. The 690 is the obvious next choice. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/device/pnp_raw.c
===================================================================
--- coreboot-v3/device/pnp_raw.c	2008-09-29 17:24:44 UTC (rev 875)
+++ coreboot-v3/device/pnp_raw.c	2008-10-01 06:47:51 UTC (rev 876)
@@ -52,7 +52,8 @@
  *
  * This is done by writing the register number to the port, and the value
  * into port + 1. This code assumes that the data port is always the
- * config-port plus 1, but luckily this is true for pretty much all devices.
+ * config-port plus 1, but luckily this is true for pretty much all devices, since
+ * it is part of the standard.
  *
  * @param port The device I/O port.
  * @param reg The register number.
@@ -65,6 +66,24 @@
 }
 
 /**
+ * Read an 8-bit pnp config value
+ *
+ * This is done by writing the register number to the port, and the value
+ * into port + 1. This code assumes that the data port is always the
+ * config-port plus 1, but luckily this is true for pretty much all devices, since
+ * it is part of the standard. 
+ *
+ * @param port The device I/O port.
+ * @param reg The register number.
+ * @returns value of the register
+ */
+u8 rawpnp_read_config(u16 port, u8 reg)
+{
+	outb(reg, port);
+	return inb(port + 1);
+}
+
+/**
  * Select a logical device.
  *
  * PNP has up to 16 logical devices. They are selected by writing the

Modified: coreboot-v3/include/device/pnp.h
===================================================================
--- coreboot-v3/include/device/pnp.h	2008-09-29 17:24:44 UTC (rev 875)
+++ coreboot-v3/include/device/pnp.h	2008-10-01 06:47:51 UTC (rev 876)
@@ -27,6 +27,7 @@
 void rawpnp_enter_ext_func_mode(u16 port);
 void rawpnp_exit_ext_func_mode(u16 port);
 void rawpnp_write_config(u16 port, u8 reg, u8 value);
+u8 rawpnp_read_config(u16 port, u8 reg);
 void rawpnp_set_logical_device(u16 port, u8 ldn);
 void rawpnp_set_enable(u16 port, int enable);
 void rawpnp_set_iobase(u16 port, u8 index, u16 iobase);

Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/Makefile	2008-09-29 17:24:44 UTC (rev 875)
+++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile	2008-10-01 06:47:51 UTC (rev 876)
@@ -19,17 +19,25 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
+STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
+			$(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
 			$(src)/mainboard/$(MAINBOARDDIR)/option_table.c \
+			$(src)/arch/x86/stage1_mtrr.c \
+			$(src)/arch/x86/amd/model_fxx/dualcore_id.c \
+			$(src)/arch/x86/amd/model_fxx/stage1.c \
 			$(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
 			$(src)/northbridge/amd/k8/coherent_ht.c \
 			$(src)/northbridge/amd/k8/incoherent_ht.c \
-			$(src)/lib/clog2.c
+			$(src)/northbridge/amd/k8/libstage1.c \
 
 INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 			$(src)/northbridge/amd/k8/raminit.c \
 			$(src)/northbridge/amd/k8/dqs.c \
+			$(src)/northbridge/amd/k8/reset_test.c \
 			$(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
+			$(src)/arch/x86/amd/model_fxx/dualcore.c \
+			$(src)/arch/x86/amd/model_fxx/fidvid.c \
+			$(src)/arch/x86/amd/model_fxx/init_cpus.c \
 			$(src)/lib/clog2.c
 
 

Modified: coreboot-v3/mainboard/gigabyte/m57sli/initram.c
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/initram.c	2008-09-29 17:24:44 UTC (rev 875)
+++ coreboot-v3/mainboard/gigabyte/m57sli/initram.c	2008-10-01 06:47:51 UTC (rev 876)
@@ -20,7 +20,7 @@
  */
 
 #define _MAINOBJECT
-
+#include <mainboard.h>
 #include <types.h>
 #include <lib.h>
 #include <console.h>

Added: coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h	                        (rev 0)
+++ coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h	2008-10-01 06:47:51 UTC (rev 876)
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ * Constants that are mainboard-defined and do not belong in Kconfig. 
+ * We really do not want this stuff to be visible -- it will make it appear that they can be 
+ * changed, and they can not. 
+ * 
+ * Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* we are unsure of these */
+#define DIMM_SOCKETS 4
+#define NODE_NUMS 16
+#define CPU_SOCKET_TYPE SOCKET_AM2
+/* these have been checked against v2 */
+#define MEM_TRAIN_SEQ 1
+#define HW_MEM_HOLE_SIZE_AUTO_INC 1
+#define HW_MEM_HOLE_SIZEK 0x100000
+#define HT_CHAIN_UNITID_BASE 0
+#define HT_CHAIN_END_UNITID_BASE 0x6
+#define SB_HT_CHAIN_ON_BUS0 2
+#define SB_HT_CHAIN_UNITID_OFFSET_ONLY 0
+#define ENABLE_APIC_EXT_ID 0
+#define LIFT_BSP_APIC_ID 1
+#define K8_SET_FIDVID 1
+/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, 
+ * so may don't need to do twice */
+#define K8_SET_FIDVID_CORE0_ONLY 1
+
+/* architecture stuff which ought to be set "somewhere" "SOMEHOW" */
+/* preferably by asking the CPU, not be a DEFINE! */
+#define CPU_ADDR_BITS 40

Modified: coreboot-v3/mainboard/gigabyte/m57sli/stage1.c
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/stage1.c	2008-09-29 17:24:44 UTC (rev 875)
+++ coreboot-v3/mainboard/gigabyte/m57sli/stage1.c	2008-10-01 06:47:51 UTC (rev 876)
@@ -19,22 +19,313 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <mainboard.h>
 #include <types.h>
 #include <lib.h>
 #include <console.h>
 #include <device/device.h>
+#include <device/pnp.h>
 #include <cpu.h>
-#include <amd/k8/k8.h>
-#include <amd/k8/sysconf.h>
 #include <device/pci.h>
 #include <string.h>
 #include <msr.h>
 #include <io.h>
 #include <arch/x86/msr.h>
+#include <superio/ite/it8716f/it8716f.h>
+#include <amd/k8/k8.h>
+#include <amd/k8/sysconf.h>
 
+#define SUPERIO_DEV 0x2e
+#define SERIAL_DEV  IT8716F_SP1
+#define GPIO_DEV IT8716F_GPIO
+#define SERIAL_IOBASE 0x3f8
 
+static const struct rmap register_values[] = {
+		/* Careful set limit registers before base registers which contain the enables */
+		/* DRAM Limit i Registers
+		 * F1:0x44 i = 0
+		 * F1:0x4C i = 1
+		 * F1:0x54 i = 2
+		 * F1:0x5C i = 3
+		 * F1:0x64 i = 4
+		 * F1:0x6C i = 5
+		 * F1:0x74 i = 6
+		 * F1:0x7C i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 3] Reserved
+		 * [10: 8] Interleave select
+		 *	   specifies the values of A[14:12] to use with interleave enable.
+		 * [15:11] Reserved
+		 * [31:16] DRAM Limit Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40 bit  address
+		 *	   that define the end of the DRAM region.
+		 */
+		PCM(0, 0x18, 1, 0x44 , 0x0000f8f8, 0x00000000),
+		PCM(0, 0x18, 1, 0x4C , 0x0000f8f8, 0x00000001),
+		PCM(0, 0x18, 1, 0x54 , 0x0000f8f8, 0x00000002),
+		PCM(0, 0x18, 1, 0x5C , 0x0000f8f8, 0x00000003),
+		PCM(0, 0x18, 1, 0x64 , 0x0000f8f8, 0x00000004),
+		PCM(0, 0x18, 1, 0x6C , 0x0000f8f8, 0x00000005),
+		PCM(0, 0x18, 1, 0x74 , 0x0000f8f8, 0x00000006),
+		PCM(0, 0x18, 1, 0x7C , 0x0000f8f8, 0x00000007),
+
+		/* DRAM Base i Registers
+		 * F1:0x40 i = 0
+		 * F1:0x48 i = 1
+		 * F1:0x50 i = 2
+		 * F1:0x58 i = 3
+		 * F1:0x60 i = 4
+		 * F1:0x68 i = 5
+		 * F1:0x70 i = 6
+		 * F1:0x78 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 7: 2] Reserved
+		 * [10: 8] Interleave Enable
+		 *	   000 = No interleave
+		 *	   001 = Interleave on A[12] (2 nodes)
+		 *	   010 = reserved
+		 *	   011 = Interleave on A[12] and A[14] (4 nodes)
+		 *	   100 = reserved
+		 *	   101 = reserved
+		 *	   110 = reserved
+		 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+		 * [15:11] Reserved
+		 * [13:16] DRAM Base Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40-bit address
+		 *	   that define the start of the DRAM region.
+		 */
+		PCM(0, 0x18, 1, 0x40 , 0x0000f8fc, 0x00000000),
+		PCM(0, 0x18, 1, 0x48 , 0x0000f8fc, 0x00000000),
+		PCM(0, 0x18, 1, 0x50 , 0x0000f8fc, 0x00000000),
+		PCM(0, 0x18, 1, 0x58 , 0x0000f8fc, 0x00000000),
+		PCM(0, 0x18, 1, 0x60 , 0x0000f8fc, 0x00000000),
+		PCM(0, 0x18, 1, 0x68 , 0x0000f8fc, 0x00000000),
+		PCM(0, 0x18, 1, 0x70 , 0x0000f8fc, 0x00000000),
+		PCM(0, 0x18, 1, 0x78 , 0x0000f8fc, 0x00000000),
+
+		/* Memory-Mapped I/O Limit i Registers
+		 * F1:0x84 i = 0
+		 * F1:0x8C i = 1
+		 * F1:0x94 i = 2
+		 * F1:0x9C i = 3
+		 * F1:0xA4 i = 4
+		 * F1:0xAC i = 5
+		 * F1:0xB4 i = 6
+		 * F1:0xBC i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = Reserved
+		 * [ 6: 6] Reserved
+		 * [ 7: 7] Non-Posted
+		 *	   0 = CPU writes may be posted
+		 *	   1 = CPU writes must be non-posted
+		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   defines the end of a memory-mapped I/O region n
+		 */
+		PCM(0, 0x18, 1, 0x84 , 0x00000048, 0x00000000),
+		PCM(0, 0x18, 1, 0x8C , 0x00000048, 0x00000000),
+		PCM(0, 0x18, 1, 0x94 , 0x00000048, 0x00000000),
+		PCM(0, 0x18, 1, 0x9C , 0x00000048, 0x00000000),
+		PCM(0, 0x18, 1, 0xA4 , 0x00000048, 0x00000000),
+		PCM(0, 0x18, 1, 0xAC , 0x00000048, 0x00000000),
+		PCM(0, 0x18, 1, 0xB4 , 0x00000048, 0x00000000),
+//		PCM(0, 0x18, 1, 0xBC , 0x00000048, 0x00ffff00),
+
+		/* Memory-Mapped I/O Base i Registers
+		 * F1:0x80 i = 0
+		 * F1:0x88 i = 1
+		 * F1:0x90 i = 2
+		 * F1:0x98 i = 3
+		 * F1:0xA0 i = 4
+		 * F1:0xA8 i = 5
+		 * F1:0xB0 i = 6
+		 * F1:0xB8 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Cpu Disable
+		 *	   0 = Cpu can use this I/O range
+		 *	   1 = Cpu requests do not use this I/O range
+		 * [ 3: 3] Lock
+		 *	   0 = base/limit registers i are read/write
+		 *	   1 = base/limit registers i are read-only
+		 * [ 7: 4] Reserved
+		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   that defines the start of memory-mapped I/O region i
+		 */
+		PCM(0, 0x18, 1, 0x80 , 0x000000f0, 0x00000000),
+		PCM(0, 0x18, 1, 0x88 , 0x000000f0, 0x00000000),
+		PCM(0, 0x18, 1, 0x90 , 0x000000f0, 0x00000000),
+		PCM(0, 0x18, 1, 0x98 , 0x000000f0, 0x00000000),
+		PCM(0, 0x18, 1, 0xA0 , 0x000000f0, 0x00000000),
+		PCM(0, 0x18, 1, 0xA8 , 0x000000f0, 0x00000000),
+		PCM(0, 0x18, 1, 0xB0 , 0x000000f0, 0x00000000),
+//		PCM(0, 0x18, 1, 0xB8 , 0x000000f0, 0x00fc0003),
+
+		/* PCI I/O Limit i Registers
+		 * F1:0xC4 i = 0
+		 * F1:0xCC i = 1
+		 * F1:0xD4 i = 2
+		 * F1:0xDC i = 3
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = reserved
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Limit Address i
+		 *	   This field defines the end of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCM(0, 0x18, 1, 0xC4 , 0xFE000FC8, 0x00007000),
+		PCM(0, 0x18, 1, 0xCC , 0xFE000FC8, 0x00000000), 
+		PCM(0, 0x18, 1, 0xD4 , 0xFE000FC8, 0x00000000),
+		PCM(0, 0x18, 1, 0xDC , 0xFE000FC8, 0x00000000),
+
+		/* PCI I/O Base i Registers
+		 * F1:0xC0 i = 0
+		 * F1:0xC8 i = 1
+		 * F1:0xD0 i = 2
+		 * F1:0xD8 i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 3: 2] Reserved
+		 * [ 4: 4] VGA Enable
+		 *	   0 = VGA matches Disabled
+		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+		 * [ 5: 5] ISA Enable
+		 *	   0 = ISA matches Disabled
+		 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+		 *	       from matching agains this base/limit pair
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Base i
+		 *	   This field defines the start of PCI I/O region n 
+		 * [31:25] Reserved
+		 */
+//		PCM(0, 0x18, 1, 0xC0 , 0xFE000FCC, 0x00000033),
+		PCM(0, 0x18, 1, 0xC8 , 0xFE000FCC, 0x00000000),
+		PCM(0, 0x18, 1, 0xD0 , 0xFE000FCC, 0x00000000),
+		PCM(0, 0x18, 1, 0xD8 , 0xFE000FCC, 0x00000000),
+
+		/* Config Base and Limit i Registers
+		 * F1:0xE0 i = 0
+		 * F1:0xE4 i = 1
+		 * F1:0xE8 i = 2
+		 * F1:0xEC i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Device Number Compare Enable
+		 *	   0 = The ranges are based on bus number
+		 *	   1 = The ranges are ranges of devices on bus 0
+		 * [ 3: 3] Reserved
+		 * [ 6: 4] Destination Node
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 7] Reserved
+		 * [ 9: 8] Destination Link
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 - Reserved
+		 * [15:10] Reserved
+		 * [23:16] Bus Number Base i
+		 *	   This field defines the lowest bus number in configuration region i
+		 * [31:24] Bus Number Limit i
+		 *	   This field defines the highest bus number in configuration region i
+		 */
+//		PCM(0, 0x18, 1, 0xE0 , 0x0000FC88, 0xff000003), /* link 0 of cpu 0 --> Nvidia MCP55 */
+		PCM(0, 0x18, 1, 0xE4 , 0x0000FC88, 0x00000000), 
+		PCM(0, 0x18, 1, 0xE8 , 0x0000FC88, 0x00000000),
+		PCM(0, 0x18, 1, 0xEC , 0x0000FC88, 0x00000000), 
+
+	};
+
+
 void hardware_stage1(void)
 {
+	void it8716f_enable_serial(u8 dev, u8 serial, u16 iobase);
+	void enumerate_ht_chain(void);
+	int max;
+	u8 tmp;
+
+	printk(BIOS_ERR, "Stage1: enable rom ...\n");
+	max = ARRAY_SIZE(register_values);
+	rawpnp_enter_ext_func_mode(SUPERIO_DEV);
+	/* The following line will set CLKIN to 24 MHz, external */
+	rawpnp_write_config(SUPERIO_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
+	tmp = rawpnp_read_config(SUPERIO_DEV, IT8716F_CONFIG_REG_SWSUSP);
+	/* Is serial flash enabled? Then enable writing to serial flash. */
+	if (tmp & 0x0e) {
+		rawpnp_write_config(SUPERIO_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
+		rawpnp_set_logical_device(SUPERIO_DEV, GPIO_DEV);
+		/* Set Serial Flash interface to 0x0820 */
+		rawpnp_write_config(SUPERIO_DEV, 0x64, 0x08);
+		rawpnp_write_config(SUPERIO_DEV, 0x65, 0x20);
+		/* We can get away with not resetting the logical device because
+		 * it8716f_enable_serial will do that.
+		 */
+	}
+ 	it8716f_enable_serial(SUPERIO_DEV, SERIAL_DEV, SERIAL_IOBASE);
+	rawpnp_exit_ext_func_mode(SERIAL_DEV);
+
+	setup_resource_map(register_values, max);
+	enumerate_ht_chain();
+	printk(BIOS_ERR, "Done.\n");
 	post_code(POST_START_OF_MAIN);
 
 }

Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/stage1.c	2008-09-29 17:24:44 UTC (rev 875)
+++ coreboot-v3/southbridge/nvidia/mcp55/stage1.c	2008-10-01 06:47:51 UTC (rev 876)
@@ -18,7 +18,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
-
+#include <mainboard.h>
 #include <console.h>
 #include <lib.h>
 #include <io.h>

Modified: coreboot-v3/superio/ite/it8716f/it8716f.h
===================================================================
--- coreboot-v3/superio/ite/it8716f/it8716f.h	2008-09-29 17:24:44 UTC (rev 875)
+++ coreboot-v3/superio/ite/it8716f/it8716f.h	2008-10-01 06:47:51 UTC (rev 876)
@@ -37,4 +37,12 @@
 #define IT8716F_GAME 0x09 /* GAME port */
 #define IT8716F_IR   0x0a /* Consumer IR */
 
+/* Global configuration registers. */
+#define IT8716F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
+#define IT8716F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
+#define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define IT8716F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
+#define IT8716F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
+
+
 #endif /* SUPERIO_ITE_IT8716F_IT8716F_H */




From svn at coreboot.org  Wed Oct  1 09:23:05 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Oct 2008 09:23:05 +0200
Subject: [coreboot] r877 - in coreboot-v3: arch/x86/amd/model_fxx
	mainboard/gigabyte/m57sli northbridge/amd/k8
	southbridge/nvidia/mcp55
Message-ID: <mailman.2146.1355071389.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-10-01 09:23:05 +0200 (Wed, 01 Oct 2008)
New Revision: 877

Modified:
   coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c
   coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h
   coreboot-v3/northbridge/amd/k8/dqs.c
   coreboot-v3/northbridge/amd/k8/raminit.c
   coreboot-v3/southbridge/nvidia/mcp55/ide.c
   coreboot-v3/southbridge/nvidia/mcp55/lpc.c
   coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
   coreboot-v3/southbridge/nvidia/mcp55/pci.c
   coreboot-v3/southbridge/nvidia/mcp55/pcie.c
   coreboot-v3/southbridge/nvidia/mcp55/sata.c
   coreboot-v3/southbridge/nvidia/mcp55/usb2.c
Log:
m57sli mostly builds again. The stage0 is too large at 24k. 
We need to figure out if we should just grow stage0. My inclination is 
to say 'yes'.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c
===================================================================
--- coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c	2008-10-01 06:47:51 UTC (rev 876)
+++ coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c	2008-10-01 07:23:05 UTC (rev 877)
@@ -300,9 +300,9 @@
 
 
 #if MEM_TRAIN_SEQ == 1
-static inline void train_ram_on_node(unsigned nodeid, unsigned coreid,
+void train_ram_on_node(unsigned nodeid, unsigned coreid,
 				     struct sys_info *sysinfo,
-				     unsigned retcall);
+				     void * retcall);
 #endif
 
 /**
@@ -479,7 +479,7 @@
 		/* this is not done on Serengeti. */
 #if MEM_TRAIN_SEQ == 1
 		train_ram_on_node(id.nodeid, id.coreid, sysinfo,
-				  STOP_CAR_AND_CPU);
+				  (void *)STOP_CAR_AND_CPU);
 #endif
 		/* this is inline and there is no return. */
 		STOP_CAR_AND_CPU();

Modified: coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h	2008-10-01 06:47:51 UTC (rev 876)
+++ coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h	2008-10-01 07:23:05 UTC (rev 877)
@@ -43,3 +43,6 @@
 /* architecture stuff which ought to be set "somewhere" "SOMEHOW" */
 /* preferably by asking the CPU, not be a DEFINE! */
 #define CPU_ADDR_BITS 40
+
+/* you don't want to set this in Kconfig or dts either. It's dangerous! */
+#define CONFIG_AP_CODE_IN_CAR 0

Modified: coreboot-v3/northbridge/amd/k8/dqs.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/dqs.c	2008-10-01 06:47:51 UTC (rev 876)
+++ coreboot-v3/northbridge/amd/k8/dqs.c	2008-10-01 07:23:05 UTC (rev 877)
@@ -26,6 +26,7 @@
 #include <macros.h>
 #include <spd.h>
 #include <cpu.h>
+#include <globalvars.h>
 #include <msr.h>
 #include <device/pci.h>
 #include <pci_ops.h>
@@ -1938,10 +1939,11 @@
 
 #if MEM_TRAIN_SEQ > 0 
 
-static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info *sysinfo, unsigned int v)
+void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info *sysinfo)
 {
 
         int ii;
+	int v = 1; /* used to be a parameter; consider making it one again */
 
          u64 tsc[4];
 
@@ -1972,9 +1974,8 @@
 	}
         	tsc[1] = cycles();
 	  	if (DQS_TRAIN_DEBUG) {
-	      printk(BIOS_DEBUG, "set DQS timing:DQSPos: ");
+	      printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x", i);
 	}
-	        print_debug_hex8(i);
 	}
 
         if(train_DqsPos(ctrl, sysinfo)) {
@@ -1987,9 +1988,8 @@
 	        tsc[2] = cycles();
 
 		if (DQS_TRAIN_DEBUG) {
-	        printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: ");
+	        printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i);
 	}
-	        print_debug_hex8(i);
 	}
         if(train_DqsRcvrEn(ctrl, 2,  sysinfo)){
 		sysinfo->mem_trained[i]=0x83; //
@@ -2011,7 +2011,7 @@
 
 	if(v) {
 	        for(ii=0;ii<4;ii++) {
-        	      print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii,  tsc[ii].hi, tsc[ii].lo);
+        	      printk(BIOS_ERR, "Total DQS Training : tsc %d: %llx", ii, tsc[ii]);
 	        }
 	}
 	
@@ -2025,17 +2025,21 @@
 #if MEM_TRAIN_SEQ == 1
 static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox)
 {
-	dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy
+	dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo); // keep the output tidy
 //      memcpy(&sysinfox->dqs_rcvr_dly_a[nodeid * 2 * 8],&sysinfo->dqs_rcvr_dly_a[nodeid * 2 * 8], 2*8);
 //      memcpy(&sysinfox->dqs_delay_a[nodeid * 2 * 2 * 9], &sysinfo->dqs_delay_a[nodeid * 2 * 2 * 9], 2 * 2 * 9);
 	sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid];
 
 }
 static void copy_and_run_ap_code_in_car(unsigned ret_addr);
-static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall)
+void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, void * retcall)
 {
 	if(coreid) return; // only do it on core0
-	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
+	/* this is a little weird. We're going to get the address of the global vars. But we're in CAR, so 
+	 * it's really private. We're going to copy from global memory, which is node 0 memory, which 
+	 * is working at this point. 
+	 */
+	struct sys_info *sysinfox = & global_vars()->sys_info;
 	wait_till_sysinfo_in_ram(); // use pci to get it
 
 	if(sysinfox->mem_trained[nodeid] == 0x80) {
@@ -2046,7 +2050,7 @@
 		sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid];
 		memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller));
 	#else
-		memcpy(sysinfo, sysinfox, DCACHE_RAM_GLOBAL_VAR_SIZE);
+		memcpy(sysinfo, sysinfox, sizeof(*sysinfo));
 	#endif
 		set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's
 	#if CONFIG_AP_CODE_IN_CAR == 0
@@ -2056,7 +2060,9 @@
 	#else
 		/* Can copy dqs_timing to ap cache and run from cache?
 		* we need coreboot_ap_car.rom? and treat it as coreboot_ram.rom for ap ?
+		 * not sure how we'll return. 
 		*/
+#warning resolve issues about returning from the copy_and_run_ap_code_in_car. 
 		copy_and_run_ap_code_in_car(retcall);
 		// will go back by jump
 	#endif

Modified: coreboot-v3/northbridge/amd/k8/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/raminit.c	2008-10-01 06:47:51 UTC (rev 876)
+++ coreboot-v3/northbridge/amd/k8/raminit.c	2008-10-01 07:23:05 UTC (rev 877)
@@ -2653,10 +2653,10 @@
 
 #if HW_MEM_HOLE_SIZE_AUTO_INC == 1
 	//We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some
-	u32 basek_pri;
+	u32 basek_pri = 0;
         for(i=0; i<controllers; i++) {
                         u32 base;
-                        unsigned base_k;
+                        u32 base_k;
                         base  = pci_conf1_read_config32(ctrl[0].f1, 0x40 + (i << 3));
                         if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
                                 continue;

Modified: coreboot-v3/southbridge/nvidia/mcp55/ide.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/ide.c	2008-10-01 06:47:51 UTC (rev 876)
+++ coreboot-v3/southbridge/nvidia/mcp55/ide.c	2008-10-01 07:23:05 UTC (rev 877)
@@ -41,7 +41,7 @@
 	u16 word;
 	u8 byte;
 
-	word = pci_conf1_read_config16(dev, 0x50);
+	word = pci_read_config16(dev, 0x50);
 	/* Ensure prefetch is disabled */
 	word &= ~((1 << 15) | (1 << 13));
 	if (conf->ide1_enable) {
@@ -56,15 +56,15 @@
 	word |= (1<<12);
 	word |= (1<<14);
 
-	pci_conf1_write_config16(dev, 0x50, word);
+	pci_write_config16(dev, 0x50, word);
 
 
 	byte = 0x20 ; // Latency: 64-->32
-	pci_conf1_write_config8(dev, 0xd, byte);
+	pci_write_config8(dev, 0xd, byte);
 
-	dword = pci_conf1_read_config32(dev, 0xf8);
+	dword = pci_read_config32(dev, 0xf8);
 	dword |= 12;
-	pci_conf1_write_config32(dev, 0xf8, dword);
+	pci_write_config32(dev, 0xf8, dword);
 #ifdef CONFIG_PCI_ROM_RUN
 	pci_dev_init(dev);
 #endif

Modified: coreboot-v3/southbridge/nvidia/mcp55/lpc.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/lpc.c	2008-10-01 06:47:51 UTC (rev 876)
+++ coreboot-v3/southbridge/nvidia/mcp55/lpc.c	2008-10-01 07:23:05 UTC (rev 877)
@@ -144,10 +144,10 @@
 	u32 dword;
 
 	/* IO APIC initialization */
-	byte = pci_conf1_read_config8(dev, 0x74);
+	byte = pci_read_config8(dev, 0x74);
 	byte |= (1<<0); // enable APIC
-	pci_conf1_write_config8(dev, 0x74, byte);
-	dword = pci_conf1_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
+	pci_write_config8(dev, 0x74, byte);
+	dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
 
 	setup_ioapic(dword, master);
 }
@@ -162,8 +162,8 @@
 {
 	unsigned long hpet_address;
 
-	pci_conf1_write_config32(dev,0x44, 0xfed00001);
-	hpet_address=pci_conf1_read_config32(dev,0x44)& 0xfffffffe;
+	pci_write_config32(dev,0x44, 0xfed00001);
+	hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
 	printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address);
 }
 #endif
@@ -180,20 +180,20 @@
 #warning posted memory write enable disabled in mcp55 lpc?
 #if 0
 	/* posted memory write enable */
-	byte = pci_conf1_read_config8(dev, 0x46);
-	pci_conf1_write_config8(dev, 0x46, byte | (1<<0));
+	byte = pci_read_config8(dev, 0x46);
+	pci_write_config8(dev, 0x46, byte | (1<<0));
 #endif
 	/* power after power fail */
 
 #if 1
 	on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 	get_option(&on, "power_on_after_fail");
-	byte = pci_conf1_read_config8(dev, PREVIOUS_POWER_STATE);
+	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 	byte &= ~0x40;
 	if (!on) {
 		byte |= 0x40;
 	}
-	pci_conf1_write_config8(dev, PREVIOUS_POWER_STATE, byte);
+	pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 	printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
 #endif
 	/* Throttle the CPU speed down for testing */
@@ -202,7 +202,7 @@
 	if(on) {
 		u16 pm10_bar;
 		u32 dword;
-		pm10_bar = (pci_conf1_read_config16(dev, 0x60)&0xff00);
+		pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
 		outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 		dword = inl(pm10_bar + 0x10);
 		on = 8-on;
@@ -213,16 +213,16 @@
 #if 0
 // default is enabled
 	/* Enable Port 92 fast reset */
-	byte = pci_conf1_read_config8(dev, 0xe8);
+	byte = pci_read_config8(dev, 0xe8);
 	byte |= ~(1 << 3);
-	pci_conf1_write_config8(dev, 0xe8, byte);
+	pci_write_config8(dev, 0xe8, byte);
 #endif
 
 	/* Enable Error reporting */
 	/* Set up sync flood detected */
-	byte = pci_conf1_read_config8(dev, 0x47);
+	byte = pci_read_config8(dev, 0x47);
 	byte |= (1 << 1);
-	pci_conf1_write_config8(dev, 0x47, byte);
+	pci_write_config8(dev, 0x47, byte);
 
 	/* Set up NMI on errors */
 	byte = inb(0x70); // RTC70
@@ -286,7 +286,7 @@
 	int i;
 	int var_num = 0;
 
-	reg = pci_conf1_read_config32(dev, 0xa0);
+	reg = pci_read_config32(dev, 0xa0);
 
 	for (link = 0; link < dev->links; link++) {
 		struct device *child;
@@ -324,9 +324,9 @@
 			}
 		}
 	}
-	pci_conf1_write_config32(dev, 0xa0, reg);
+	pci_write_config32(dev, 0xa0, reg);
 	for(i=0;i<var_num;i++) {
-		pci_conf1_write_config32(dev, 0xa8 + i*4, reg_var[i]);
+		pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
 	}
 
 

Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/mcp55.c	2008-10-01 06:47:51 UTC (rev 876)
+++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.c	2008-10-01 07:23:05 UTC (rev 877)
@@ -52,7 +52,7 @@
 		(lpc_dev->id.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
 		) ) {
 			u32 id;
-			id = pci_conf1_read_config32(lpc_dev, PCI_VENDOR_ID);
+			id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
 			if ( (id < (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) ||
 				(id > (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16)))
 				) {
@@ -82,7 +82,7 @@
 
 	/* sorry. Again, anonymous unions etc. would make this easier. */
 	if(dev->id.pci.device==0x0000) {
-		vendorid = pci_conf1_read_config32(dev, PCI_VENDOR_ID);
+		vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
 		deviceid = (vendorid>>16) & 0xffff;
 //		vendorid &= 0xffff;
 	} else {
@@ -180,14 +180,14 @@
 		if(!sm_dev) return;
 
 		if ( sm_dev ) {
-			reg_old = reg =  pci_conf1_read_config32(sm_dev, 0xe4);
+			reg_old = reg =  pci_read_config32(sm_dev, 0xe4);
 
 			if (!dev->enabled) { //disable it
 				reg |= (1<<index2);
 			}
 
 			if (reg != reg_old) {
-				pci_conf1_write_config32(sm_dev, 0xe4, reg);
+				pci_write_config32(sm_dev, 0xe4, reg);
 			}
 		}
 
@@ -199,14 +199,14 @@
 	if ( index == 0) {  // for LPC
 
 		// expose ioapic base
-		byte = pci_conf1_read_config8(lpc_dev, 0x74);
+		byte = pci_read_config8(lpc_dev, 0x74);
 		byte |= ((1<<1)); // expose the BAR
-		pci_conf1_write_config8(dev, 0x74, byte);
+		pci_write_config8(dev, 0x74, byte);
 
 		// expose trap base
-		byte = pci_conf1_read_config8(lpc_dev, 0xdd);
+		byte = pci_read_config8(lpc_dev, 0xdd);
 		byte |= ((1<<0)|(1<<3)); // expose the BAR and enable write
-		pci_conf1_write_config8(dev, 0xdd, byte);
+		pci_write_config8(dev, 0xdd, byte);
 
 		return;
 
@@ -216,16 +216,16 @@
 		sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
 		if(!sm_dev) return;
 
-		final_reg = pci_conf1_read_config32(sm_dev, 0xe8);
+		final_reg = pci_read_config32(sm_dev, 0xe8);
 		final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9));
-		pci_conf1_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
+		pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
 #if 0
-		reg_old = reg = pci_conf1_read_config32(sm_dev, 0xe4);
+		reg_old = reg = pci_read_config32(sm_dev, 0xe4);
 //		reg |= (1<<0);
 		reg &= ~(0x3f<<4);
 		if (reg != reg_old) {
 			printk_debug("mcp55.c pcie enabled\n");
-			pci_conf1_write_config32(sm_dev, 0xe4, reg);
+			pci_write_config32(sm_dev, 0xe4, reg);
 		}
 #endif
 	}
@@ -238,9 +238,9 @@
 	if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
 		sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
 		if(!sm_dev) return;
-		reg_old = pci_conf1_read_config32(sm_dev, 0xe8);
+		reg_old = pci_read_config32(sm_dev, 0xe8);
 		if (final_reg != reg_old) {
-			pci_conf1_write_config32(sm_dev, 0xe8, final_reg);
+			pci_write_config32(sm_dev, 0xe8, final_reg);
 		}
 
 	}
@@ -251,7 +251,7 @@
 void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
 			   unsigned int device)
 {
-	pci_conf1_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID,
+	pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID,
 		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 

Modified: coreboot-v3/southbridge/nvidia/mcp55/pci.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/pci.c	2008-10-01 06:47:51 UTC (rev 876)
+++ coreboot-v3/southbridge/nvidia/mcp55/pci.c	2008-10-01 07:23:05 UTC (rev 877)
@@ -43,23 +43,23 @@
 #endif
 
 	/* System error enable */
-	dword = pci_conf1_read_config32(dev, 0x04);
+	dword = pci_read_config32(dev, 0x04);
 	dword |= (1<<8); /* System error enable */
 	dword |= (1<<30); /* Clear possible errors */
-	pci_conf1_write_config32(dev, 0x04, dword);
+	pci_write_config32(dev, 0x04, dword);
 
 #if 1
 	//only need (a01,xx]
-	word = pci_conf1_read_config16(dev, 0x48);
+	word = pci_read_config16(dev, 0x48);
 	word |= (1<<0); /* MRL2MRM */
 	word |= (1<<2); /* MR2MRM */
-	pci_conf1_write_config16(dev, 0x48, word);
+	pci_write_config16(dev, 0x48, word);
 #endif
 
 #if 1
-	dword = pci_conf1_read_config32(dev, 0x4c);
+	dword = pci_read_config32(dev, 0x4c);
 	dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
-	pci_conf1_write_config32(dev, 0x4c, dword);
+	pci_write_config32(dev, 0x4c, dword);
 #endif
 
 #ifdef CONFIG_PCI_64BIT_PREF_MEM
@@ -84,7 +84,7 @@
 	printk(BIOS_DEBUG, "dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base);
 #endif
 	printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword);
-	pci_conf1_write_config32(dev, 0x50, dword); //TOM
+	pci_write_config32(dev, 0x50, dword); //TOM
 
 }
 

Modified: coreboot-v3/southbridge/nvidia/mcp55/pcie.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/pcie.c	2008-10-01 06:47:51 UTC (rev 876)
+++ coreboot-v3/southbridge/nvidia/mcp55/pcie.c	2008-10-01 07:23:05 UTC (rev 877)
@@ -39,10 +39,10 @@
 	u32 dword;
 
 	/* System error enable */
-	dword = pci_conf1_read_config32(dev, 0x04);
+	dword = pci_read_config32(dev, 0x04);
 	dword |= (1<<8); /* System error enable */
 	dword |= (1<<30); /* Clear possible errors */
-	pci_conf1_write_config32(dev, 0x04, dword);
+	pci_write_config32(dev, 0x04, dword);
 
 }
 

Modified: coreboot-v3/southbridge/nvidia/mcp55/sata.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/sata.c	2008-10-01 06:47:51 UTC (rev 876)
+++ coreboot-v3/southbridge/nvidia/mcp55/sata.c	2008-10-01 07:23:05 UTC (rev 877)
@@ -40,7 +40,7 @@
 	struct southbridge_nvidia_mcp55_sata_config *conf =
 	    (struct southbridge_nvidia_mcp55_sata_config *)dev->device_configuration;
 
-	dword = pci_conf1_read_config32(dev, 0x50);
+	dword = pci_read_config32(dev, 0x50);
 	/* Ensure prefetch is disabled */
 	dword &= ~((1 << 15) | (1 << 13));
 	if(conf) {
@@ -62,11 +62,11 @@
 	dword &= ~(0x1f<<24);
 	dword |= (0x15<<24);
 #endif
-	pci_conf1_write_config32(dev, 0x50, dword);
+	pci_write_config32(dev, 0x50, dword);
 
-	dword = pci_conf1_read_config32(dev, 0xf8);
+	dword = pci_read_config32(dev, 0xf8);
 	dword |= 2;
-	pci_conf1_write_config32(dev, 0xf8, dword);
+	pci_write_config32(dev, 0xf8, dword);
 }
 
 struct device_operations mcp55_sata = {

Modified: coreboot-v3/southbridge/nvidia/mcp55/usb2.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/usb2.c	2008-10-01 06:47:51 UTC (rev 876)
+++ coreboot-v3/southbridge/nvidia/mcp55/usb2.c	2008-10-01 07:23:05 UTC (rev 877)
@@ -41,9 +41,9 @@
 static void usb2_init(struct device *dev)
 {
 	u32 dword;
-	dword = pci_conf1_read_config32(dev, 0xf8);
+	dword = pci_read_config32(dev, 0xf8);
 	dword |= 40;
-	pci_conf1_write_config32(dev, 0xf8, dword);
+	pci_write_config32(dev, 0xf8, dword);
 }
 
 static void usb2_set_resources(struct device *dev)




From stepan at coresystems.de  Wed Oct  1 11:32:17 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 01 Oct 2008 11:32:17 +0200
Subject: [coreboot] r877 - in coreboot-v3:
 arch/x86/amd/model_fxx	mainboard/gigabyte/m57sli
 northbridge/amd/k8	southbridge/nvidia/mcp55
Message-ID: <48E343A1.4000003@coresystems.de>

svn at coreboot.org wrote:
> Author: rminnich
> Date: 2008-10-01 09:23:05 +0200 (Wed, 01 Oct 2008)
> New Revision: 877
>
> Modified:
>    coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c
>    coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h
>    coreboot-v3/northbridge/amd/k8/dqs.c
>    coreboot-v3/northbridge/amd/k8/raminit.c
>    coreboot-v3/southbridge/nvidia/mcp55/ide.c
>    coreboot-v3/southbridge/nvidia/mcp55/lpc.c
>    coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
>    coreboot-v3/southbridge/nvidia/mcp55/pci.c
>    coreboot-v3/southbridge/nvidia/mcp55/pcie.c
>    coreboot-v3/southbridge/nvidia/mcp55/sata.c
>    coreboot-v3/southbridge/nvidia/mcp55/usb2.c
> Log:
> m57sli mostly builds again. The stage0 is too large at 24k. 
> We need to figure out if we should just grow stage0. My inclination is 
> to say 'yes'.
>   

What's in stage0 that makes it so big? Is that part really required in
stage0?

If so, we need to grow stage0. But we should try to answer that question
first.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From svn at coreboot.org  Wed Oct  1 14:52:53 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Oct 2008 14:52:53 +0200
Subject: [coreboot] r3624 - in trunk/coreboot-v2/src: arch/i386/boot
	arch/i386/lib arch/i386/smp arch/ppc/boot cpu/amd/model_10xxx
	cpu/amd/sc520 cpu/emulation/qemu-x86 drivers/ati/ragexl
	mainboard/a-trend/atc-6220 mainboard/agami/aruma
	mainboard/amd/dbm690t mainboard/amd/serengeti_cheetah
	mainboard/amd/serengeti_cheetah_fam10 mainboard/arima/hdama
	mainboard/artecgroup/dbe61 mainboard/asus/a8n_e
	mainboard/asus/mew-vm mainboard/asus/p2b mainboard/asus/p2b-f
	mainboard/asus/p3b-f mainboard/azza/pt-6ibd
	mainboard/biostar/m6tba mainboard/broadcom/blast
	mainboard/compaq/deskpro_en_sff_p600 mainboard/dell/s1850
	mainboard/digitallogic/adl855pc mainboard/eaglelion/5bcm
	mainboard/gigabyte/ga-6bxc mainboard/gigabyte/ga_2761gxdk
	mainboard/gigabyte/m57sli mainboard/ibm/e325
	mainboard/ibm/e326 mainboard/intel/jarrell
	mainboard/intel/xe7501devkit mainboard/iwill/dk8_htx
	mainboard/iwill/dk8s2 mainboard/iwill/dk8x
	mainboard/msi/ms6178 mainboard/msi/ms7135
	mainboard/msi/ms7260 mainboard/msi/ms9185
	mainboard/msi/ms9282 mainboard/newisys/khepri
	mainboard/nvidia/l1_2pvv mainboard/sunw/ultra40
	mainboard/supermicro/h8dmr mainboard/supermicro/x6dai_g
	mainboard/supermicro/x6dhe_g mainboard/supermicro/x6dhe_g2
	mainboard/supermicro/x6dhr_ig mainboard/supermicro/x6dhr_ig2
	mainboard/tyan/s1846 mainboard/tyan/s2735
	mainboard/tyan/s2850 mainboard/tyan/s2875
	mainboard/tyan/s2880 mainboard/tyan/s2881
	mainboard/tyan/s2882 mainboard/tyan/s2885
	mainboard/tyan/s2891 mainboard/tyan/s2892
	mainboard/tyan/s2895 mainboard/tyan/s2912
	mainboard/tyan/s2912_fam10 mainboard/tyan/s4880
	mainboard/tyan/s4882 mainboard/via/epia mainboard/via/epia-m
	northbridge/amd/amdfam10 northbridge/amd/amdk8
	northbridge/amd/gx2 northbridge/intel/e7501
	northbridge/intel/e7520 northbridge/intel/e7525
	northbridge/intel/i3100 northbridge/intel/i440bx
	northbridge/intel/i855pm northbridge/via/vt8601
	northbridge/via/vt8623 southbridge/amd/amd8111
	southbridge/amd/cs5536 southbridge/amd/sb600
	southbridge/nvidia/ck804 southbridge/nvidia/mcp55
	southbridge/sis/sis966 stream/fs superio/ite/it8661f
	superio/ite/it8671f superio/ite/it8673f superio/ite/it8705f
	superio/ite/it8712f superio/ite/it8716f superio/ite/it8718f
	superio/nsc/pc8374 superio/nsc/pc87309 superio/nsc/pc87351
	superio/nsc/pc87360 superio/nsc/pc87366 superio/nsc/pc87417
	superio/nsc/pc87427 superio/nsc/pc97307 superio/nsc/pc97317
	superio/smsc/fdc37m60x superio/smsc/lpc47b272
	superio/smsc/lpc47b397 superio/smsc/lpc47m10x
	superio/smsc/lpc47n217 superio/via/vt1211
	superio/winbond/w83627ehg superio/winbond/w83627hf
	superio/winbond/w83627thf superio/winbond/w83977f
	superio/winbond/w83977tf
Message-ID: <mailman.2147.1355071389.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-10-01 14:52:52 +0200 (Wed, 01 Oct 2008)
New Revision: 3624

Modified:
   trunk/coreboot-v2/src/arch/i386/boot/acpi.c
   trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
   trunk/coreboot-v2/src/arch/i386/lib/cpu.c
   trunk/coreboot-v2/src/arch/i386/lib/exception.c
   trunk/coreboot-v2/src/arch/i386/smp/ioapic.c
   trunk/coreboot-v2/src/arch/ppc/boot/coreboot_table.c
   trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c
   trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c
   trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c
   trunk/coreboot-v2/src/drivers/ati/ragexl/xlinit.c
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c
   trunk/coreboot-v2/src/mainboard/agami/aruma/auto.c
   trunk/coreboot-v2/src/mainboard/agami/aruma/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/agami/aruma/resourcemap.c
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/resourcemap.c
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/resourcemap.c
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
   trunk/coreboot-v2/src/mainboard/arima/hdama/auto.c
   trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c
   trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c
   trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c
   trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c
   trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c
   trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c
   trunk/coreboot-v2/src/mainboard/broadcom/blast/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/broadcom/blast/resourcemap.c
   trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c
   trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c
   trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c
   trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c
   trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c
   trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/resourcemap.c
   trunk/coreboot-v2/src/mainboard/ibm/e325/auto.c
   trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/ibm/e325/resourcemap.c
   trunk/coreboot-v2/src/mainboard/ibm/e326/auto.c
   trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/ibm/e326/resourcemap.c
   trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c
   trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c
   trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/resourcemap.c
   trunk/coreboot-v2/src/mainboard/iwill/dk8s2/auto.c
   trunk/coreboot-v2/src/mainboard/iwill/dk8x/auto.c
   trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c
   trunk/coreboot-v2/src/mainboard/msi/ms7135/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/msi/ms7260/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/msi/ms7260/resourcemap.c
   trunk/coreboot-v2/src/mainboard/msi/ms9185/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/msi/ms9185/resourcemap.c
   trunk/coreboot-v2/src/mainboard/msi/ms9282/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/msi/ms9282/resourcemap.c
   trunk/coreboot-v2/src/mainboard/newisys/khepri/auto.c
   trunk/coreboot-v2/src/mainboard/newisys/khepri/resourcemap.c
   trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/resourcemap.c
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/auto.c
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/resourcemap.c
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/resourcemap.c
   trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/auto.c
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/auto.c
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.c
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.updated.c
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/auto.c
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2735/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2850/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2875/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2881/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2881/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/tyan/s2881/resourcemap.c
   trunk/coreboot-v2/src/mainboard/tyan/s2882/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2885/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2885/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/tyan/s2885/resourcemap.c
   trunk/coreboot-v2/src/mainboard/tyan/s2891/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2891/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/tyan/s2891/resourcemap.c
   trunk/coreboot-v2/src/mainboard/tyan/s2892/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2892/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/tyan/s2892/resourcemap.c
   trunk/coreboot-v2/src/mainboard/tyan/s2895/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2895/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/tyan/s2895/resourcemap.c
   trunk/coreboot-v2/src/mainboard/tyan/s2912/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/tyan/s2912/resourcemap.c
   trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/resourcemap.c
   trunk/coreboot-v2/src/mainboard/tyan/s4880/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s4880/resourcemap.c
   trunk/coreboot-v2/src/mainboard/tyan/s4882/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s4882/resourcemap.c
   trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c
   trunk/coreboot-v2/src/mainboard/via/epia/auto.c
   trunk/coreboot-v2/src/northbridge/amd/amdfam10/resourcemap.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c
   trunk/coreboot-v2/src/northbridge/amd/gx2/chipsetinit.c
   trunk/coreboot-v2/src/northbridge/intel/e7501/raminit.c
   trunk/coreboot-v2/src/northbridge/intel/e7520/raminit.c
   trunk/coreboot-v2/src/northbridge/intel/e7520/raminit_test.c
   trunk/coreboot-v2/src/northbridge/intel/e7525/raminit.c
   trunk/coreboot-v2/src/northbridge/intel/e7525/raminit_test.c
   trunk/coreboot-v2/src/northbridge/intel/i3100/raminit.c
   trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c
   trunk/coreboot-v2/src/northbridge/intel/i855pm/raminit.c
   trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c
   trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c
   trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
   trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
   trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
   trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c
   trunk/coreboot-v2/src/stream/fs/vfs.c
   trunk/coreboot-v2/src/superio/ite/it8661f/superio.c
   trunk/coreboot-v2/src/superio/ite/it8671f/superio.c
   trunk/coreboot-v2/src/superio/ite/it8673f/superio.c
   trunk/coreboot-v2/src/superio/ite/it8705f/superio.c
   trunk/coreboot-v2/src/superio/ite/it8712f/superio.c
   trunk/coreboot-v2/src/superio/ite/it8716f/superio.c
   trunk/coreboot-v2/src/superio/ite/it8718f/superio.c
   trunk/coreboot-v2/src/superio/nsc/pc8374/superio.c
   trunk/coreboot-v2/src/superio/nsc/pc87309/superio.c
   trunk/coreboot-v2/src/superio/nsc/pc87351/superio.c
   trunk/coreboot-v2/src/superio/nsc/pc87360/superio.c
   trunk/coreboot-v2/src/superio/nsc/pc87366/superio.c
   trunk/coreboot-v2/src/superio/nsc/pc87417/superio.c
   trunk/coreboot-v2/src/superio/nsc/pc87427/superio.c
   trunk/coreboot-v2/src/superio/nsc/pc97307/superio.c
   trunk/coreboot-v2/src/superio/nsc/pc97317/superio.c
   trunk/coreboot-v2/src/superio/smsc/fdc37m60x/superio.c
   trunk/coreboot-v2/src/superio/smsc/lpc47b272/superio.c
   trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c
   trunk/coreboot-v2/src/superio/smsc/lpc47m10x/superio.c
   trunk/coreboot-v2/src/superio/smsc/lpc47n217/superio.c
   trunk/coreboot-v2/src/superio/via/vt1211/vt1211.c
   trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c
   trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c
   trunk/coreboot-v2/src/superio/winbond/w83627thf/superio.c
   trunk/coreboot-v2/src/superio/winbond/w83977f/superio.c
   trunk/coreboot-v2/src/superio/winbond/w83977tf/superio.c
Log:
The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of
code to use it. That makes the code more readable and also less
error-prone.

Abuild tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/boot/acpi.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/arch/i386/boot/acpi.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -44,7 +44,7 @@
 {
 	int i;
 	
-	int entries_num = sizeof(rsdt->entry)/sizeof(rsdt->entry[0]);
+	int entries_num = ARRAY_SIZE(rsdt->entry);
 	
 	for (i=0; i<entries_num; i++) {
 		if(rsdt->entry[i]==0) {

Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -184,7 +184,7 @@
 		{ LB_TAG_ASSEMBLER,      coreboot_assembler,      },
 	};
 	unsigned int i;
-	for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) {
+	for(i = 0; i < ARRAY_SIZE(strings); i++) {
 		struct lb_string *rec;
 		size_t len;
 		rec = (struct lb_string *)lb_new_record(header);

Modified: trunk/coreboot-v2/src/arch/i386/lib/cpu.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/cpu.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/arch/i386/lib/cpu.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -123,7 +123,7 @@
 {
 	const char *name;
 	name = "<invalid cpu vendor>";
-	if ((vendor < (sizeof(x86_vendor_name)/sizeof(x86_vendor_name[0]))) &&
+	if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
 		(x86_vendor_name[vendor] != 0)) 
 	{
 		name = x86_vendor_name[vendor];
@@ -185,7 +185,7 @@
 		}
 	}
 	cpu->vendor = X86_VENDOR_UNKNOWN;
-	for(i = 0; i < sizeof(x86_vendors)/sizeof(x86_vendors[0]); i++) {
+	for(i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
 		if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
 			cpu->vendor = x86_vendors[i].vendor;
 			break;

Modified: trunk/coreboot-v2/src/arch/i386/lib/exception.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/exception.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/arch/i386/lib/exception.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -377,7 +377,7 @@
 	gdb_stub_registers[CS] = info->cs;
 	gdb_stub_registers[PS] = info->eflags;
 	signo = GDB_UNKNOWN;
-	if (info->vector < sizeof(exception_to_signal)/sizeof(exception_to_signal[0])) {
+	if (info->vector < ARRAY_SIZE(exception_to_signal)) {
 		signo = exception_to_signal[info->vector];
 	}
 	

Modified: trunk/coreboot-v2/src/arch/i386/smp/ioapic.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/smp/ioapic.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/arch/i386/smp/ioapic.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -67,7 +67,7 @@
 	l[0] = 0x03;
 	l[4] = 1;
 #endif /* i786 */
-	for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+	for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
 	     i++, a++) {
 		l[0] = (a->reg * 2) + 0x10;
 		l[4] = a->value_low;

Modified: trunk/coreboot-v2/src/arch/ppc/boot/coreboot_table.c
===================================================================
--- trunk/coreboot-v2/src/arch/ppc/boot/coreboot_table.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/arch/ppc/boot/coreboot_table.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -116,7 +116,7 @@
 		{ LB_TAG_ASSEMBLER,      coreboot_assembler,      },
 	};
 	unsigned int i;
-	for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) {
+	for(i = 0; i < ARRAY_SIZE(strings); i++) {
 		struct lb_string *rec;
 		size_t len;
 		rec = (struct lb_string *)lb_new_record(header);

Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -522,7 +522,7 @@
 	printk_debug("setup_remote_node: %02x", node);
 
 	/* copy the default resource map from node 0 */
-	for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) {
+	for(i = 0; i < ARRAY_SIZE(pci_reg); i++) {
 		u32 value;
 		u16 reg;
 		reg = pci_reg[i];
@@ -852,7 +852,7 @@
 	revision = mctGetLogicalCPUID(0xFF);
 	platform = get_platform_type();
 
-	for(i = 0; i < sizeof(fam10_msr_default)/sizeof(fam10_msr_default[0]); i++) {
+	for(i = 0; i < ARRAY_SIZE(fam10_msr_default); i++) {
 		if ((fam10_msr_default[i].revision & revision) &&
 		    (fam10_msr_default[i].platform & platform)) {
 			msr = rdmsr(fam10_msr_default[i].msr);
@@ -889,7 +889,7 @@
 
 	AMD_SetupPSIVID_d(platform, node);	/* Set PSIVID offset which is not table driven */
 
-	for(i = 0; i < sizeof(fam10_pci_default)/sizeof(fam10_pci_default[0]); i++) {
+	for(i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) {
 		if ((fam10_pci_default[i].revision & revision) &&
 		    (fam10_pci_default[i].platform & platform)) {
 			val = pci_read_config32(NODE_PCI(node,
@@ -903,7 +903,7 @@
 		}
 	}
 
-	for(i = 0; i < sizeof(fam10_htphy_default)/sizeof(fam10_htphy_default[0]); i++) {
+	for(i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) {
 		if ((fam10_htphy_default[i].revision & revision) &&
 		    (fam10_htphy_default[i].platform & platform)) {
 			/* HT Phy settings either apply to both sublinks or have

Modified: trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -151,7 +151,7 @@
 		// int i;
 		int idx;
 #if 0
-		for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
+		for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 			unsigned char reg;
 			reg = pci_read_config8(mc_dev, ramregs[i]);
 			/* these are ENDING addresses, not sizes. 

Modified: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -80,7 +80,7 @@
 		unsigned char rambits;
 		int i, idx;
 
-		for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
+		for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 			unsigned char reg;
 			reg = pci_read_config8(mc_dev, ramregs[i]);
 			/* these are ENDING addresses, not sizes. 

Modified: trunk/coreboot-v2/src/drivers/ati/ragexl/xlinit.c
===================================================================
--- trunk/coreboot-v2/src/drivers/ati/ragexl/xlinit.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/drivers/ati/ragexl/xlinit.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -281,7 +281,7 @@
 	aty_st_le32(0xEC, 0x00000000, info);
 	aty_st_le32(0xFC, 0x00000000, info);
 
-	for (i=0; i<sizeof(lcd_tbl)/sizeof(lcd_tbl_t); i++) {
+	for (i=0; i<ARRAY_SIZE(lcd_tbl); i++) {
 		aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info);
 	}
 
@@ -547,7 +547,7 @@
     	chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
     	type = chip_id & CFG_CHIP_TYPE;
     	rev = (chip_id & CFG_CHIP_REV)>>24;
-    	for (j = 0; j < (sizeof(aty_chips)/sizeof(*aty_chips)); j++)
+    	for (j = 0; j < ARRAY_SIZE(aty_chips); j++)
         	if (type == aty_chips[j].chip_type &&
             		(rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) {
             		chipname = aty_chips[j].name;

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -67,6 +68,6 @@
 	report_bist_failure(bist);
 	enable_smbus();
 	/* dump_spd_registers(&memctrl[0]); */
-	sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+	sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	/* ram_check(0, 640 * 1024); */
 }

Modified: trunk/coreboot-v2/src/mainboard/agami/aruma/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/agami/aruma/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/agami/aruma/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -6,6 +6,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -171,7 +172,7 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 #if 0
 	/* Check the first 1M */

Modified: trunk/coreboot-v2/src/mainboard/agami/aruma/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/agami/aruma/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/agami/aruma/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -3,6 +3,7 @@
 #include <device/pci_ids.h>
 #include <string.h>
 #include <stdint.h>
+#include <stdlib.h>
 #if CONFIG_LOGICAL_CPUS==1
 #include <cpu/amd/dualcore.h>
 #endif
@@ -62,7 +63,7 @@
 
 	get_bus_conf_done = 1;
 
-	hc_possible_num = sizeof(pci1234) / sizeof(pci1234[0]);
+	hc_possible_num = ARRAY_SIZE(pci1234);
 
 	get_sblk_pci1234();
 

Modified: trunk/coreboot-v2/src/mainboard/agami/aruma/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/agami/aruma/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/agami/aruma/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -265,7 +265,7 @@
 
 	};
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -22,6 +22,7 @@
 #include <device/pci_ids.h>
 #include <string.h>
 #include <stdint.h>
+#include <stdlib.h>
 #if CONFIG_LOGICAL_CPUS==1
 #include <cpu/amd/dualcore.h>
 #endif
@@ -72,7 +73,7 @@
 		return;		/* do it only once */
 	get_bus_conf_done = 1;
 
-	sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]);
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
 	for (i = 0; i < sysconf.hc_possible_num; i++) {
 		sysconf.pci1234[i] = pci1234x[i];
 		sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -273,6 +273,6 @@
 	};
 
 	int max;
-	max = sizeof(register_values) / sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -9,6 +9,7 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
+#include <stdlib.h>
 #include "mb_sysconf.h"
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
@@ -90,7 +91,7 @@
 	
 	m = sysconf.mb;
 
-	sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);	
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);	
 	for(i=0;i<sysconf.hc_possible_num; i++) {
 		sysconf.pci1234[i] = pci1234x[i];
 		sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -258,7 +258,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -28,6 +28,7 @@
 
 #include <cpu/amd/amdfam10_sysconf.h>
 
+#include <stdlib.h>
 #include "mb_sysconf.h"
 
 /* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */
@@ -111,7 +112,7 @@
 		m->bus_type[i] = 0;
 	}
 
-	sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
 	for(i=0;i<sysconf.hc_possible_num; i++) {
 		sysconf.pci1234[i] = pci1234x[i];
 		sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -275,7 +275,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -6,6 +6,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -157,11 +158,11 @@
 #endif
 	enable_smbus();
 #if 0
-	dump_spd_registers(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	dump_spd_registers(ARRAY_SIZE(cpu), cpu);
 #endif
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 	
 #if 0
 	dump_pci_devices();

Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -215,7 +216,7 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 	post_cache_as_ram();
 

Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -51,7 +52,7 @@
 	int i;
 
 	if (device == DIMM0){
-		for (i=0; i < (sizeof spd_table/sizeof spd_table[0]); i++){
+		for (i=0; i < (ARRAY_SIZE(spd_table)); i++){
 			if (spd_table[i].address == address){
 				return spd_table[i].data;
 			}

Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -31,6 +31,7 @@
 #include <cpu/amd/dualcore.h>
 #endif
 #include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
 
 /*
  * Global variables for MB layouts and these will be shared by irqtable,

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -77,7 +78,7 @@
 	/* dump_spd_registers(&memctrl[0]); */
 
 	/* sdram_initialize() runs out of registers. */
-	/* sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); */
+	/* sdram_initialize(ARRAY_SIZE(memctrl), memctrl); */
 
 	sdram_set_registers(memctrl);
 	sdram_set_spd_registers(memctrl);

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -67,6 +68,6 @@
 	report_bist_failure(bist);
 	enable_smbus();
 	/* dump_spd_registers(&memctrl[0]); */
-	sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+	sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	/* ram_check(0, 640 * 1024); */
 }

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -70,6 +71,6 @@
 	report_bist_failure(bist);
 	enable_smbus();
 	/* dump_spd_registers(&memctrl[0]); */
-	sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+	sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	/* ram_check(0, 640 * 1024); */
 }

Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -70,6 +71,6 @@
 	report_bist_failure(bist);
 	enable_smbus();
 	/* dump_spd_registers(&memctrl[0]); */
-	sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+	sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	/* ram_check(0, 640 * 1024); */
 }

Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -70,6 +71,6 @@
 	report_bist_failure(bist);
 	enable_smbus();
 	/* dump_spd_registers(&memctrl[0]); */
-	sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+	sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	/* ram_check(0, 640 * 1024); */
 }

Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -67,6 +68,6 @@
 	report_bist_failure(bist);
 	enable_smbus();
 	/* dump_spd_registers(&memctrl[0]); */
-	sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+	sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	/* ram_check(0, 640 * 1024); */
 }

Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -8,6 +8,7 @@
 #endif
 
 #include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
 
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
@@ -61,7 +62,7 @@
 
         get_bus_conf_done = 1;
 
-        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
                 sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -259,7 +259,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -70,6 +71,6 @@
 	report_bist_failure(bist);
 	enable_smbus();
 	/* dump_spd_registers(&memctrl[0]); */
-	sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+	sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	/* ram_check(0, 640 * 1024); */
 }

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -5,6 +5,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -139,7 +140,7 @@
 //	dump_ipmi_registers();
 	mainboard_set_e7520_leds();	
 //	memreset_setup();
-	sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+	sdram_initialize(ARRAY_SIZE(mch), mch);
 #if 0
 	dump_pci_devices();
 #endif

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -10,6 +10,7 @@
 #endif
 #include <arch/hlt.h>
 //#include "option_table.h"
+#include <stdlib.h>
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
@@ -100,7 +101,7 @@
 
 		memreset_setup();
 
-		sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
+		sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 
 	} 
 #if 0

Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -6,6 +6,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -48,7 +49,7 @@
 #endif
 	};
 	int i;
-	for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
+	for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
 		ram_check(check_addrs[i].lo, check_addrs[i].hi);
 	}
 #endif

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -67,6 +68,6 @@
 	report_bist_failure(bist);
 	enable_smbus();
 	/* dump_spd_registers(&memctrl[0]); */
-	sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+	sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	/* ram_check(0, 640 * 1024); */
 }

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -31,6 +31,7 @@
 #endif
 
 #include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
 
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
@@ -82,7 +83,7 @@
 
         get_bus_conf_done = 1;
 
-        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
                 sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -277,7 +277,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -1,4 +1,5 @@
 #include <arch/io.h>
+#include <stdlib.h>
 
 static void write_index(uint16_t port_base, uint8_t reg, uint8_t value)
 {
@@ -67,15 +68,13 @@
 	{ 0x13, 0x77}
 };
 
-#define ARRAYSIZE(x) sizeof x/sizeof *x
-
 /*
  * Called from superio.c
  */
 void init_ec(uint16_t base)
 {
 	int i;
-	for (i=0; i<ARRAYSIZE(sequence); i++) {
+	for (i=0; i<ARRAY_SIZE(sequence); i++) {
 		write_index(base, sequence[i].index, sequence[i].value);
 	}
 }

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -29,6 +29,7 @@
 #endif
 
 #include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
 
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
@@ -80,7 +81,7 @@
 
         get_bus_conf_done = 1;
 
-        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
                 sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -277,7 +277,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -8,6 +8,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -163,7 +164,7 @@
 #endif
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 #if 0
 	dump_pci_devices();

Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -211,7 +212,7 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 	post_cache_as_ram();
 

Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -266,6 +266,6 @@
 	PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, 
         };
         int max;
-        max = sizeof(register_values)/sizeof(register_values[0]);
+        max = ARRAY_SIZE(register_values);
         setup_resource_map(register_values, max);
 }

Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -8,6 +8,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -163,7 +164,7 @@
 #endif
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 #if 0
 	dump_pci_devices();

Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -211,7 +212,7 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 	post_cache_as_ram();
 

Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -266,6 +266,6 @@
 	PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, 
         };
         int max;
-        max = sizeof(register_values)/sizeof(register_values[0]);
+        max = ARRAY_SIZE(register_values);
         setup_resource_map(register_values, max);
 }

Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -5,6 +5,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -120,7 +121,7 @@
 	power_down_reset_check();
 //	dump_ipmi_registers();
 	mainboard_set_e7520_leds();	
-	sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+	sdram_initialize(ARRAY_SIZE(mch), mch);
 	ich5_watchdog_on();
 #if 0
 	dump_pci_devices();

Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -83,7 +84,7 @@
 //      dump_smbus_registers();
 
 //		memreset_setup();		No-op for this chipset
-		sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
+		sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	}
 	
 	// NOTE: ROMCC dies with an internal compiler error

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -9,6 +9,7 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
+#include <stdlib.h>
 #include "mb_sysconf.h"
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
@@ -90,7 +91,7 @@
 	
 	m = sysconf.mb;
 
-	sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);	
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);	
 	for(i=0;i<sysconf.hc_possible_num; i++) {
 		sysconf.pci1234[i] = pci1234x[i];
 		sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -258,7 +258,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -6,6 +6,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -149,7 +150,7 @@
 #endif
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 #if 0
 	dump_pci_devices();

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8x/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -6,6 +6,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -148,7 +149,7 @@
 #endif
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 #if 1
 	dump_pci_devices();
@@ -181,7 +182,7 @@
 #endif
 	};
 	int i;
-	for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
+	for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
 		ram_check(check_addrs[i].lo, check_addrs[i].hi);
 	}
 #endif

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -65,6 +66,6 @@
 	console_init();
 	report_bist_failure(bist);
 	/* dump_spd_registers(&memctrl[0]); */
-	sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+	sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	/* ram_check(0, 640 * 1024); */
 }

Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7135/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7135/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -32,6 +32,7 @@
 #endif
 
 #include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
 
 /* Global variables for MB layouts and these will be shared by irqtable,
  * mptable and acpi_tables.
@@ -67,8 +68,8 @@
 
 	get_bus_conf_done = 1;
 
-	sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]);
-	sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]);
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
 	for (i = 0; i < sysconf.hc_possible_num; i++) {
 		sysconf.pci1234[i] = pci1234x[i];
 		sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7260/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7260/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -28,6 +28,7 @@
 #include <cpu/amd/dualcore.h>
 #endif
 #include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
 
 /* Global variables for MB layouts (shared by irqtable/mptable/acpi_table). */
 // busnum is default.
@@ -81,7 +82,7 @@
 
 	get_bus_conf_done = 1;
 
-	sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]);
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
 	for (i = 0; i < sysconf.hc_possible_num; i++) {
 		sysconf.pci1234[i] = pci1234x[i];
 		sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7260/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7260/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -278,6 +278,6 @@
 
 	};
 
-	int max = sizeof(register_values) / sizeof(register_values[0]);
+	int max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9185/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9185/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -32,6 +32,7 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
+#include <stdlib.h>
 #include "mb_sysconf.h"
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
@@ -82,7 +83,7 @@
 
        m = sysconf.mb;
 
-        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
 
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9185/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9185/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -285,7 +285,7 @@
        };
 
        int max;
-       max = sizeof(register_values)/sizeof(register_values[0]);
+       max = ARRAY_SIZE(register_values);
        setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9282/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9282/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -33,6 +33,7 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
+#include <stdlib.h>
 #include "mb_sysconf.h"
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
@@ -110,7 +111,7 @@
        m = sysconf.mb;
        memset(m, 0, sizeof(struct mb_sysconf_t));
 
-        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
                 sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9282/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9282/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -293,7 +293,7 @@
        };
 
        int max;
-       max = sizeof(register_values)/sizeof(register_values[0]);
+       max = ARRAY_SIZE(register_values);
        setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/newisys/khepri/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/newisys/khepri/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -6,6 +6,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -138,7 +139,7 @@
 	dump_spd_registers(&cpu[0]);
 #endif
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 #if 0
 	dump_pci_devices();

Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/newisys/khepri/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/newisys/khepri/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -265,7 +265,7 @@
 	PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 	};
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -30,6 +30,7 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
+#include <stdlib.h>
 #include "mb_sysconf.h"
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
@@ -108,7 +109,7 @@
 	m = sysconf.mb;
 	memset(m, 0, sizeof(struct mb_sysconf_t));
 
-        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
 
         for (i = 0; i < sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];

Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -277,7 +277,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -191,7 +192,7 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 
 }

Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -6,6 +6,7 @@
 #if CONFIG_LOGICAL_CPUS==1
 #include <cpu/amd/dualcore.h>
 #endif
+#include <stdlib.h>
 
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
@@ -75,7 +76,7 @@
 
 	get_bus_conf_done = 1;
 
-	hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);	
+	hc_possible_num = ARRAY_SIZE(pci1234);	
 	
 	get_sblk_pci1234();
 	

Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -260,7 +260,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -29,6 +29,7 @@
 #endif
 
 #include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
 
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
@@ -81,7 +82,7 @@
 
         get_bus_conf_done = 1;
 
-        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
                 sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -277,7 +277,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -5,6 +5,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -113,7 +114,7 @@
 	}
 #endif
 	disable_watchdogs();
-	sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+	sdram_initialize(ARRAY_SIZE(mch), mch);
 #if 1
 	dump_pci_device(PCI_DEV(0, 0x00, 0));
 //	dump_bar14(PCI_DEV(0, 0x00, 0));

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -5,6 +5,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -138,7 +139,7 @@
 //	dump_ipmi_registers();
 //	mainboard_set_e7520_leds();	
 //	memreset_setup();
-	sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+	sdram_initialize(ARRAY_SIZE(mch), mch);
 #if 0
 	dump_pci_devices();
 #endif

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -5,6 +5,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -139,7 +140,7 @@
 //	dump_ipmi_registers();
 //	mainboard_set_e7520_leds();	
 //	memreset_setup();
-	sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+	sdram_initialize(ARRAY_SIZE(mch), mch);
 #if 0
 	dump_pci_devices();
 #endif

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.updated.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.updated.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/auto.updated.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -5,6 +5,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -139,7 +140,7 @@
 //	dump_ipmi_registers();
 //	mainboard_set_e7520_leds();	
 //	memreset_setup();
-	sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+	sdram_initialize(ARRAY_SIZE(mch), mch);
 #if 0
 	dump_pci_devices();
 #endif

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -5,6 +5,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -139,7 +140,7 @@
 //	dump_ipmi_registers();
 	mainboard_set_e7520_leds();	
 //	memreset_setup();
-	sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+	sdram_initialize(ARRAY_SIZE(mch), mch);
 #if 1
 	dump_pci_devices();
 #endif

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -5,6 +5,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -139,7 +140,7 @@
 //	dump_ipmi_registers();
 	mainboard_set_e7520_leds();	
 //	memreset_setup();
-	sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+	sdram_initialize(ARRAY_SIZE(mch), mch);
 #if 0
 	dump_pci_devices();
 #endif

Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -67,6 +68,6 @@
 	report_bist_failure(bist);
 	enable_smbus();
 	/* dump_spd_registers(&memctrl[0]); */
-	sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+	sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	/* ram_check(0, 640 * 1024); */
 }

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2735/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2735/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -96,7 +97,7 @@
 #endif
 
 		memreset_setup();
-		sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
+		sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	} 
 #if 0
 	else {

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2850/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2850/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -6,6 +6,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -197,6 +198,6 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 }

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -206,7 +207,7 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 	post_cache_as_ram();
 }

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -167,6 +168,6 @@
 
 	enable_smbus();
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 }

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -203,7 +204,7 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 	post_cache_as_ram();
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -205,7 +206,7 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 	post_cache_as_ram();
 }

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -172,6 +173,6 @@
 	
 	enable_smbus();
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 }

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -8,6 +8,7 @@
 #endif
 
 #include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
 
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
@@ -63,7 +64,7 @@
 
         get_bus_conf_done = 1;
 
-        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
                 sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -258,7 +258,7 @@
 	PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 	};
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2882/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2882/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -176,6 +177,6 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 }

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -208,7 +209,7 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 	post_cache_as_ram();
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2885/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2885/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -6,6 +6,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -178,7 +179,7 @@
 
 	enable_smbus();
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2885/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2885/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -8,6 +8,7 @@
 #endif
 
 #include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
 //busnum is default
@@ -65,7 +66,7 @@
 
         get_bus_conf_done = 1;
 
-        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
                 sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2885/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2885/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -259,7 +259,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -6,6 +6,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -145,6 +146,6 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 }

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -8,6 +8,7 @@
 #endif
 
 #include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
 //busnum is default
@@ -71,7 +72,7 @@
 
         get_bus_conf_done = 1;
 
-        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
                 sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -260,7 +260,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -6,6 +6,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -147,6 +148,6 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 }

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -8,6 +8,7 @@
 #endif
 
 #include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
 //busnum is default
@@ -68,7 +69,7 @@
 
         get_bus_conf_done = 1;
 
-        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
                 sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -260,7 +260,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -172,6 +173,6 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 }

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -8,6 +8,7 @@
 #endif
 
 #include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
 //busnum is default
@@ -76,7 +77,7 @@
 
         get_bus_conf_done = 1;
 
-        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
                 sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -261,7 +261,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -30,6 +30,7 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
+#include <stdlib.h>
 #include "mb_sysconf.h"
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
@@ -107,7 +108,7 @@
 	m = sysconf.mb;
 	memset(m, 0, sizeof(struct mb_sysconf_t));
 
-        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
                 sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -277,7 +277,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/get_bus_conf.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/get_bus_conf.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -30,6 +30,7 @@
 
 #include <cpu/amd/amdfam10_sysconf.h>
 
+#include <stdlib.h>
 #include "mb_sysconf.h"
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
@@ -83,7 +84,7 @@
 	m = sysconf.mb;
 	memset(m, 0, sizeof(struct mb_sysconf_t));
 
-        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
                 sysconf.hcdn[i] = hcdnx[i];

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -277,7 +277,7 @@
 	};
 
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4880/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4880/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -227,6 +228,6 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 }

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -7,6 +7,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -254,7 +255,7 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 	post_cache_as_ram();
 }

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4880/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4880/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -258,7 +258,7 @@
 	PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 	};
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4882/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4882/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -6,6 +6,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -227,6 +228,6 @@
 	enable_smbus();
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 	
 }

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4882/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4882/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -258,7 +258,7 @@
 	PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 	};
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/mainboard/via/epia/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/via/epia/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -6,6 +6,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -107,7 +108,7 @@
 
 	/*
 	  this is way more generic than we need.
-	  sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	  sdram_initialize(ARRAY_SIZE(cpu), cpu);
 	*/
 	sdram_set_registers((const struct mem_controller *) 0);
 	sdram_set_spd_registers((const struct mem_controller *) 0);
@@ -129,7 +130,7 @@
 #endif
 	};
 	int i;
-	for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
+	for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
 		ram_check(check_addrs[i].lo, check_addrs[i].hi);
 	}
 #endif

Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m/auto.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -10,6 +10,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -146,7 +147,7 @@
 #endif
 	};
 	int i;
-	for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
+	for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
 		ram_check(check_addrs[i].lo, check_addrs[i].hi);
 	}
 #endif

Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdfam10/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -281,7 +281,7 @@
 	};
 
 	u32 max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }
 

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -66,6 +66,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/hypertransport_def.h>
+#include <stdlib.h>
 #include "arch/romcc_io.h"
 
 #include "amdk8.h"
@@ -510,7 +511,7 @@
 	print_spew("setup_remote_node: ");
 
 	/* copy the default resource map from node 0 */
-	for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) {
+	for(i = 0; i < ARRAY_SIZE(pci_reg); i++) {
 		uint32_t value;
 		uint8_t reg;
 		reg = pci_reg[i];
@@ -802,7 +803,7 @@
 	};
 #endif
 
-	setup_row_indirect_group(conn4_1, sizeof(conn4_1)/sizeof(conn4_1[0]));
+	setup_row_indirect_group(conn4_1, ARRAY_SIZE(conn4_1));
 
 	setup_temp_row(0,2);
 	verify_connection(7);
@@ -893,7 +894,7 @@
                 3,0,1,1,
         };
 #endif
-        setup_remote_row_indirect_group(conn4_3, sizeof(conn4_3)/sizeof(conn4_3[0]));
+        setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3));
 
 /* ready to enable RT for Node 3 */
 	rename_temp_node(3);
@@ -909,7 +910,7 @@
                 2,1,0,1,
         };      
 #endif          
-        setup_row_indirect_group(conn4_2, sizeof(conn4_2)/sizeof(conn4_2[0]));
+        setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2));
 
 #if 0
 	/*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */
@@ -974,7 +975,7 @@
 #endif
 	}; 
 
-	setup_row_indirect_group(conn6_1, sizeof(conn6_1)/sizeof(conn6_1[0]));
+	setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1));
 	
 	for(byte=0; byte<4; byte+=2) {
 		setup_temp_row(byte,byte+2);
@@ -998,7 +999,7 @@
 #endif
 	};      
 	
-	setup_remote_row_indirect_group(conn6_2, sizeof(conn6_2)/sizeof(conn6_2[0]));
+	setup_remote_row_indirect_group(conn6_2, ARRAY_SIZE(conn6_2));
 	
 	rename_temp_node(4);
 	enable_routing(4);
@@ -1084,7 +1085,7 @@
 #endif
 	};      
 	
-	setup_remote_row_indirect_group(conn6_3, sizeof(conn6_3)/sizeof(conn6_3[0]));
+	setup_remote_row_indirect_group(conn6_3, ARRAY_SIZE(conn6_3));
 
 /* ready to enable RT for 5 */
 	rename_temp_node(5);
@@ -1110,7 +1111,7 @@
 #endif
 	};      
 	
-	setup_row_indirect_group(conn6_4, sizeof(conn6_4)/sizeof(conn6_4[0]));
+	setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4));
 
 #if 0
 	/* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5)
@@ -1202,7 +1203,7 @@
 #endif
 	};
 
-	setup_row_indirect_group(conn8_1,sizeof(conn8_1)/sizeof(conn8_1[0]));
+	setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1));
 
 	for(byte=0; byte<6; byte+=2) {
 		setup_temp_row(byte,byte+2);
@@ -1225,7 +1226,7 @@
 #endif
 	};
 
-	setup_remote_row_indirect_group(conn8_2, sizeof(conn8_2)/sizeof(conn8_2[0]));
+	setup_remote_row_indirect_group(conn8_2, ARRAY_SIZE(conn8_2));
 
 #if CROSS_BAR_47_56
 	//init 5, 6 here
@@ -1414,7 +1415,7 @@
 #endif
 	};
 
-	setup_row_indirect_group(conn8_3, sizeof(conn8_3)/sizeof(conn8_3[0]));
+	setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3));
 
 #if CROSS_BAR_47_56
         /* for 47, 56, 57, 75, 46, 64 we need to substract another link to 
@@ -1455,7 +1456,7 @@
 		7, 3, 6,
         };
 
-        opt_broadcast_rt_group(conn8_4, sizeof(conn8_4)/sizeof(conn8_4[0]));
+        opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4));
 
         static const u8 conn8_5[] = {
                 2, 7, 0, 
@@ -1463,7 +1464,7 @@
                 3, 6, 1, 
         };      
                 
-        opt_broadcast_rt_plus_group(conn8_5, sizeof(conn8_5)/sizeof(conn8_5[0]));
+        opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5));
 #endif
 
 
@@ -1770,7 +1771,7 @@
                         1,3,
                         2,3,
                 };
-                needs_reset |= optimize_connection_group(opt_conn4, sizeof(opt_conn4)/sizeof(opt_conn4[0]));
+                needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4));
         }
 #endif
 
@@ -1783,7 +1784,7 @@
                         4, 5,
         #endif
                 };
-                needs_reset |= optimize_connection_group(opt_conn6, sizeof(opt_conn6)/sizeof(opt_conn6[0]));
+                needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6));
         }
 #endif
 
@@ -1798,7 +1799,7 @@
                        5, 7,
                        6, 7,
                };
-                needs_reset |= optimize_connection_group(opt_conn8, sizeof(opt_conn8)/sizeof(opt_conn8[0]));
+                needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8));
         }
 #endif
 

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -10,6 +10,7 @@
 #include <cpu/x86/mem.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
+#include <stdlib.h>
 #include "raminit.h"
 #include "amdk8.h"
 
@@ -555,7 +556,7 @@
 	print_spew("setting up CPU");
 	print_spew_hex8(ctrl->node_id);
 	print_spew(" northbridge registers\r\n");
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	for(i = 0; i < max; i += 3) {
 		device_t dev;
 		unsigned where;
@@ -1303,7 +1304,7 @@
 		}
 		device0 = ctrl->channel0[i];
 		device1 = ctrl->channel1[i];
-		for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) {
+		for(j = 0; j < ARRAY_SIZE(addresses); j++) {
 			unsigned addr;
 			addr = addresses[j];
 			value0 = spd_read_byte(device0, addr);

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -25,6 +25,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/tsc.h>
 
+#include <stdlib.h>
 #include "raminit.h"
 #include "amdk8_f.h"
 #include "spd_ddr2.h"
@@ -715,7 +716,7 @@
 	print_spew("setting up CPU");
 	print_spew_hex8(ctrl->node_id);
 	print_spew(" northbridge registers\r\n");
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	for (i = 0; i < max; i += 3) {
 		device_t dev;
 		unsigned where;
@@ -1496,7 +1497,7 @@
 		}
 		device0 = ctrl->channel0[i];
 		device1 = ctrl->channel1[i];
-		for (j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) {
+		for (j = 0; j < ARRAY_SIZE(addresses); j++) {
 			unsigned addr;
 			addr = addresses[j];
 			value0 = spd_read_byte(device0, addr);

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -4,6 +4,7 @@
 #include <string.h>
 #include <setjmp.h>
 #include <device/pci_def.h>
+#include <stdlib.h>
 #include "amdk8.h"
 
 jmp_buf end_buf;
@@ -341,7 +342,7 @@
 	};
 	console_init();
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 }
 

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -253,6 +253,6 @@
 	PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 	};
 	int max;
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	setup_resource_map(register_values, max);
 }

Modified: trunk/coreboot-v2/src/northbridge/amd/gx2/chipsetinit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/gx2/chipsetinit.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/amd/gx2/chipsetinit.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -177,7 +177,7 @@
 	{ FLASH_TYPE_NONE, 0, 0 },	/* CS3, or Flash Device 3 */
 };
 
-#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0]))
+#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))
 
 uint32_t FlashPort[] = {
 	MDD_LBAR_FLSH0,

Modified: trunk/coreboot-v2/src/northbridge/intel/e7501/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/e7501/raminit.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/intel/e7501/raminit.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -14,6 +14,7 @@
 #include <assert.h>
 #include <spd.h>
 #include <sdram_mode.h>
+#include <stdlib.h>
 #include "e7501.h"
 
 // Uncomment this to enable run-time checking of DIMM parameters 
@@ -1631,7 +1632,7 @@
 static void ram_set_d0f0_regs(const struct mem_controller *ctrl) 
 {
 	int i;
-	int num_values = sizeof(constant_register_values)/sizeof(constant_register_values[0]);
+	int num_values = ARRAY_SIZE(constant_register_values);
 
 	ASSERT((num_values % 3) == 0);		// Bad table?
 

Modified: trunk/coreboot-v2/src/northbridge/intel/e7520/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/e7520/raminit.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/intel/e7520/raminit.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -21,6 +21,7 @@
 #include <cpu/x86/mem.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <stdlib.h>
 #include "raminit.h"
 #include "e7520.h"
 
@@ -62,7 +63,7 @@
 	int i;
 	int max;
 
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	for(i = 0; i < max; i += 3) {
 		device_t dev;
 		unsigned where;

Modified: trunk/coreboot-v2/src/northbridge/intel/e7520/raminit_test.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/e7520/raminit_test.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/intel/e7520/raminit_test.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -4,6 +4,7 @@
 #include <string.h>
 #include <setjmp.h>
 #include <device/pci_def.h>
+#include <stdlib.h>
 #include "e7520.h"
 
 jmp_buf end_buf;
@@ -341,7 +342,7 @@
 	};
 	console_init();
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 }
 

Modified: trunk/coreboot-v2/src/northbridge/intel/e7525/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/e7525/raminit.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/intel/e7525/raminit.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -21,6 +21,7 @@
 #include <cpu/x86/mem.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <stdlib.h>
 #include "raminit.h"
 #include "e7525.h"
 
@@ -62,7 +63,7 @@
 	int i;
 	int max;
 
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	for(i = 0; i < max; i += 3) {
 		device_t dev;
 		unsigned where;

Modified: trunk/coreboot-v2/src/northbridge/intel/e7525/raminit_test.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/e7525/raminit_test.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/intel/e7525/raminit_test.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -4,6 +4,7 @@
 #include <string.h>
 #include <setjmp.h>
 #include <device/pci_def.h>
+#include <stdlib.h>
 #include "e7525.h"
 
 jmp_buf end_buf;
@@ -313,7 +314,7 @@
 	};
 	console_init();
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 }
 #endif

Modified: trunk/coreboot-v2/src/northbridge/intel/i3100/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i3100/raminit.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/intel/i3100/raminit.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -22,6 +22,7 @@
 #include <cpu/x86/mem.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <stdlib.h>
 #include "raminit.h"
 #include "i3100.h"
 
@@ -64,7 +65,7 @@
 	int i;
 	int max;
 
-	max = sizeof(register_values)/sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 	for(i = 0; i < max; i += 3) {
 		device_t dev;
 		u32 where;

Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -21,6 +21,7 @@
 #include <spd.h>
 #include <sdram_mode.h>
 #include <delay.h>
+#include <stdlib.h>
 #include "i440bx.h"
 
 /*-----------------------------------------------------------------------------
@@ -430,7 +431,7 @@
 	PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n");
 	DUMPNORTH();
 
-	max = sizeof(register_values) / sizeof(register_values[0]);
+	max = ARRAY_SIZE(register_values);
 
 	/* Set registers as specified in the register_values[] array. */
 	for (i = 0; i < max; i += 3) {

Modified: trunk/coreboot-v2/src/northbridge/intel/i855pm/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i855pm/raminit.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/intel/i855pm/raminit.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -384,7 +384,7 @@
 #endif
 	int i;
 	int max;
-        max = sizeof(register_values)/sizeof(register_values[0]);
+        max = ARRAY_SIZE(register_values);
         for(i = 0; i < max; i += 3) {
                 uint32_t reg;
 #if DEBUG_RAM_CONFIG >=2

Modified: trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -115,7 +115,7 @@
 		unsigned char rambits;
 		int i, idx;
 
-		for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
+		for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 			unsigned char reg;
 			reg = pci_read_config8(mc_dev, ramregs[i]);
 			/* these are ENDING addresses, not sizes. 

Modified: trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -287,7 +287,7 @@
 		unsigned char rambits;
 		int i, idx;
 
-		for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
+		for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 			unsigned char reg;
 			reg = pci_read_config8(mc_dev, ramregs[i]);
 			/* these are ENDING addresses, not sizes. 

Modified: trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -10,6 +10,7 @@
 #include <pc80/mc146818rtc.h>
 #include <pc80/isa-dma.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "amd8111.h"
 
 #define NMI_OFF 0
@@ -77,7 +78,7 @@
 	ioapicregvalues[0].value_high = bsp_apicid<<(56-32);
 	printk_debug("amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid); 
 	
-	for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+	for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
 	     i++, a++) {
 		l[0] = (a->reg * 2) + 0x10;
 		l[4] = a->value_low;

Modified: trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -29,6 +29,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/vr.h>
 #include <cpu/amd/geode_post_code.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "cs5536.h"
 
@@ -93,7 +94,7 @@
 	{FLASH_TYPE_NONE, 0, 0},	/* CS3, or Flash Device 3 */
 };
 
-#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0]))
+#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))
 
 uint32_t FlashPort[] = {
 	MDD_LBAR_FLSH0,

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -27,6 +27,7 @@
 #include <bitops.h>
 #include <arch/io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "sb600.h"
 #include "sb600_smbus.c"
 
@@ -101,7 +102,7 @@
 
 	l = (unsigned long *)ioapic_base;
 
-	for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+	for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
 	     i++, a++) {
 		l[0] = (a->reg * 2) + 0x10;
 		l[4] = a->value_low;

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -102,7 +102,7 @@
 #endif
 	};
 
-	setup_resource_map(ctrl_devport_conf, sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]));
+	setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf));
 
 }
 
@@ -121,7 +121,7 @@
 #endif
 	};
 
-	setup_resource_map(ctrl_devport_conf_clear, sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]));
+	setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear));
 
 }
 
@@ -324,7 +324,7 @@
 
 
 
-	setup_resource_map_x(ctrl_conf, sizeof(ctrl_conf)/sizeof(ctrl_conf[0]));
+	setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf));
 
 	setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
 	setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -105,12 +105,12 @@
 	for(j = 0; j < ck804_num; j++ ) {
 		if(busn[j]==0) { //sb chain
 			setup_resource_map_offset(ctrl_devport_conf,
-				 sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
+				ARRAY_SIZE(ctrl_devport_conf),
 				PCI_DEV(busn[j], 0, 0) , io_base[j]);
 			continue;
 		}
 		setup_resource_map_offset(ctrl_devport_conf_b,
-			sizeof(ctrl_devport_conf_b)/sizeof(ctrl_devport_conf_b[0]),
+			ARRAY_SIZE(ctrl_devport_conf_b),
 			PCI_DEV(busn[j], 0, 0) , io_base[j]);
 	}
 }
@@ -132,12 +132,12 @@
 	for(j = 0; j < ck804_num; j++ ) {
 		if(busn[j]==0) { //sb chain
 			setup_resource_map_offset(ctrl_devport_conf_clear,
-				sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
+				ARRAY_SIZE(ctrl_devport_conf_clear),
 				PCI_DEV(busn[j], 0, 0) , io_base[j]);
 			continue;
 		}
 		setup_resource_map_offset(ctrl_devport_conf_clear_b,
-			sizeof(ctrl_devport_conf_clear_b)/sizeof(ctrl_devport_conf_clear_b[0]),
+			ARRAY_SIZE(ctrl_devport_conf_clear_b),
 			PCI_DEV(busn[j], 0, 0) , io_base[j]);
 	}
 
@@ -327,13 +327,13 @@
 
 	for(j=0; j<ck804_num; j++) {
 		if(busn[j] == 0) {
-			setup_resource_map_x_offset(ctrl_conf_master, sizeof(ctrl_conf_master)/sizeof(ctrl_conf_master[0]),
+			setup_resource_map_x_offset(ctrl_conf_master, ARRAY_SIZE(ctrl_conf_master),
 				PCI_DEV(busn[0],0,0), io_base[0]);
 			continue;
 		}
 
 
-		setup_resource_map_x_offset(ctrl_conf_slave, sizeof(ctrl_conf_slave)/sizeof(ctrl_conf_slave[0]),
+		setup_resource_map_x_offset(ctrl_conf_slave, ARRAY_SIZE(ctrl_conf_slave),
 			PCI_DEV(busn[j],0,0), io_base[j]);
 	}
 

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -15,6 +15,7 @@
 #include <bitops.h>
 #include <arch/io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "ck804.h"
 
 #define CK804_CHIP_REV 2
@@ -82,7 +83,7 @@
 
 	l = (unsigned long *) ioapic_base;
 
-	for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+	for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
 	     i++, a++) {
 		l[0] = (a->reg * 2) + 0x10;
 		l[4] = a->value_low;

Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -106,7 +106,7 @@
 	int j;
 	for(j = 0; j < mcp55_num; j++ ) {
 		setup_resource_map_offset(ctrl_devport_conf,
-			sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
+			ARRAY_SIZE(ctrl_devport_conf),
 			PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
 	}
 }
@@ -123,7 +123,7 @@
 	int j;
 	for(j = 0; j < mcp55_num; j++ ) {
 		setup_resource_map_offset(ctrl_devport_conf_clear,
-			sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
+			ARRAY_SIZE(ctrl_devport_conf_clear),
 			PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
 	}
 
@@ -327,23 +327,23 @@
 	for(j=0; j<mcp55_num; j++) {
 		mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
 
-		setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]),
+		setup_resource_map_x_offset(ctrl_conf_1, ARRAY_SIZE(ctrl_conf_1),
 				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
 		for(i=0; i<3; i++) { // three SATA
-			setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]),
+			setup_resource_map_x_offset(ctrl_conf_1_1, ARRAY_SIZE(ctrl_conf_1_1),
 				PCI_DEV(busn[j], devn[j], i), io_base[j]);
 		}
 		if(busn[j] == 0) {
-			setup_resource_map_x_offset(ctrl_conf_mcp55_only, sizeof(ctrl_conf_mcp55_only)/sizeof(ctrl_conf_mcp55_only[0]),
+			setup_resource_map_x_offset(ctrl_conf_mcp55_only, ARRAY_SIZE(ctrl_conf_mcp55_only),
 				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
 		}
 
 		if( (busn[j] == 0) && (mcp55_num>1) ) {
-			setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]),
+			setup_resource_map_x_offset(ctrl_conf_master_only, ARRAY_SIZE(ctrl_conf_master_only),
 				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
 		}
 
-		setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]),
+		setup_resource_map_x_offset(ctrl_conf_2, ARRAY_SIZE(ctrl_conf_2),
 				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
 
 	}

Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -34,6 +34,7 @@
 #include <bitops.h>
 #include <arch/io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "mcp55.h"
 
 #define NMI_OFF	0
@@ -106,7 +107,7 @@
 
 	l = (unsigned long *) ioapic_base;
 
-	for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+	for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
 	     i++, a++) {
 		l[0] = (a->reg * 2) + 0x10;
 		l[4] = a->value_low;

Modified: trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -36,6 +36,7 @@
 #include <bitops.h>
 #include <arch/io.h>
 #include <cpu/x86/lapic.h>
+#include <stdlib.h>
 #include "sis966.h"
 #include <pc80/keyboard.h>
 
@@ -102,7 +103,7 @@
 
 	l = (unsigned long *) ioapic_base;
 
-	for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+	for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
 	     i++, a++) {
 		l[0] = (a->reg * 2) + 0x10;
 		l[4] = a->value_low;

Modified: trunk/coreboot-v2/src/stream/fs/vfs.c
===================================================================
--- trunk/coreboot-v2/src/stream/fs/vfs.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/stream/fs/vfs.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -70,7 +70,7 @@
 {
     int i;
 
-    for (i = 0; i < sizeof(fsys_table)/sizeof(fsys_table[0]); i++) {
+    for (i = 0; i < ARRAY_SIZE(fsys_table); i++) {
 	if (fsys_table[i].mount_func()) {
 	    fsys = &fsys_table[i];
 	    printk_info("Mounted %s\n", fsys->name);

Modified: trunk/coreboot-v2/src/superio/ite/it8661f/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8661f/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/ite/it8661f/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -23,6 +23,7 @@
 #include <device/device.h>
 #include <device/pnp.h>
 #include <uart8250.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "it8661f.h"
 
@@ -72,7 +73,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &pnp_ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_ite_it8661f_ops = {

Modified: trunk/coreboot-v2/src/superio/ite/it8671f/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8671f/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/ite/it8671f/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -22,6 +22,7 @@
 #include <device/pnp.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "it8671f.h"
 
@@ -77,7 +78,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &pnp_ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_ite_it8671f_ops = {

Modified: trunk/coreboot-v2/src/superio/ite/it8673f/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8673f/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/ite/it8673f/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -22,6 +22,7 @@
 #include <device/pnp.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "it8673f.h"
 
@@ -79,7 +80,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &pnp_ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_ite_it8673f_ops = {

Modified: trunk/coreboot-v2/src/superio/ite/it8705f/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8705f/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/ite/it8705f/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -23,6 +23,7 @@
 #include <device/device.h>
 #include <device/pnp.h>
 #include <uart8250.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "it8705f.h"
 
@@ -80,7 +81,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &pnp_ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_ite_it8705f_ops = {

Modified: trunk/coreboot-v2/src/superio/ite/it8712f/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8712f/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/ite/it8712f/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -24,6 +24,7 @@
 #include <uart8250.h>
 #include <pc80/keyboard.h>
 #include <arch/io.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "it8712f.h"
 
@@ -134,7 +135,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &pnp_ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_ite_it8712f_ops = {

Modified: trunk/coreboot-v2/src/superio/ite/it8716f/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8716f/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/ite/it8716f/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -27,6 +27,7 @@
 #include <uart8250.h>
 #include <pc80/keyboard.h>
 #include <arch/io.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "it8716f.h"
 
@@ -165,7 +166,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &ops,
-		sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_ite_it8716f_ops = {

Modified: trunk/coreboot-v2/src/superio/ite/it8718f/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8718f/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/ite/it8718f/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -22,6 +22,7 @@
 #include <device/pnp.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "it8718f.h"
 
@@ -81,7 +82,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &pnp_ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_ite_it8718f_ops = {

Modified: trunk/coreboot-v2/src/superio/nsc/pc8374/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc8374/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/nsc/pc8374/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -10,6 +10,7 @@
 #include <bitops.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "pc8374.h"
 
@@ -64,7 +65,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_nsc_pc8374_ops = {

Modified: trunk/coreboot-v2/src/superio/nsc/pc87309/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc87309/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/nsc/pc87309/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -23,6 +23,7 @@
 #include <device/pnp.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "pc87309.h"
 
@@ -73,7 +74,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &pnp_ops,
-		sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_nsc_pc87309_ops = {

Modified: trunk/coreboot-v2/src/superio/nsc/pc87351/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc87351/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/nsc/pc87351/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -16,6 +16,7 @@
 #include <bitops.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "pc87351.h"
 
@@ -71,7 +72,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &pnp_ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_nsc_pc87351_ops = {

Modified: trunk/coreboot-v2/src/superio/nsc/pc87360/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc87360/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/nsc/pc87360/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -10,6 +10,7 @@
 #include <bitops.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "pc87360.h"
 
@@ -67,7 +68,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_nsc_pc87360_ops = {

Modified: trunk/coreboot-v2/src/superio/nsc/pc87366/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc87366/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/nsc/pc87366/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -10,6 +10,7 @@
 #include <bitops.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "pc87366.h"
 
@@ -67,7 +68,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &pnp_ops, 
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_nsc_pc87366_ops = {

Modified: trunk/coreboot-v2/src/superio/nsc/pc87417/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc87417/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/nsc/pc87417/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -12,6 +12,7 @@
 #include <bitops.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "pc87417.h"
 
@@ -68,7 +69,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &pnp_ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_nsc_pc87417_ops = {

Modified: trunk/coreboot-v2/src/superio/nsc/pc87427/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc87427/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/nsc/pc87427/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -8,6 +8,7 @@
 #include <console/console.h>
 #include <string.h>
 #include <bitops.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "pc87427.h"
 
@@ -68,7 +69,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); 
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info); 
 }
 
 struct chip_operations superio_nsc_pc87427_ops = {

Modified: trunk/coreboot-v2/src/superio/nsc/pc97307/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc97307/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/nsc/pc97307/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -5,6 +5,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pnp.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "pc97307.h"
 
@@ -79,7 +80,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_nsc_pc97307_ops = {

Modified: trunk/coreboot-v2/src/superio/nsc/pc97317/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc97317/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/nsc/pc97317/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -5,6 +5,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pnp.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "pc97317.h"
 
@@ -81,7 +82,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_nsc_pc97317_ops = {

Modified: trunk/coreboot-v2/src/superio/smsc/fdc37m60x/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/fdc37m60x/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/smsc/fdc37m60x/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -22,6 +22,7 @@
 #include <device/pnp.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "fdc37m60x.h"
 
@@ -77,7 +78,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &pnp_ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_smsc_fdc37m60x_ops = {

Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b272/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47b272/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47b272/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -32,6 +32,7 @@
 #include <bitops.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "lpc47b272.h"
 
@@ -84,7 +85,7 @@
 static void enable_dev(device_t dev)
 {
 	pnp_enable_devices(dev, &pnp_ops, 
-					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
+					   ARRAY_SIZE(pnp_dev_info), 
 					   pnp_dev_info);
 }
 

Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -14,6 +14,7 @@
 #include <bitops.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "lpc47b397.h"
 
@@ -207,7 +208,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &pnp_ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_smsc_lpc47b397_ops = {

Modified: trunk/coreboot-v2/src/superio/smsc/lpc47m10x/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47m10x/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47m10x/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -31,6 +31,7 @@
 #include <bitops.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "lpc47m10x.h"
 
@@ -82,7 +83,7 @@
 static void enable_dev(device_t dev)
 {
 	pnp_enable_devices(dev, &pnp_ops, 
-					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
+					   ARRAY_SIZE(pnp_dev_info), 
 					   pnp_dev_info);
 }
 

Modified: trunk/coreboot-v2/src/superio/smsc/lpc47n217/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47n217/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47n217/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -33,6 +33,7 @@
 #include <bitops.h>
 #include <uart8250.h>
 #include <assert.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "lpc47n217.h"
 
@@ -86,7 +87,7 @@
 static void enable_dev(device_t dev)
 {
 	pnp_enable_devices(dev, &pnp_ops, 
-					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
+					   ARRAY_SIZE(pnp_dev_info), 
 					   pnp_dev_info);
 }
 

Modified: trunk/coreboot-v2/src/superio/via/vt1211/vt1211.c
===================================================================
--- trunk/coreboot-v2/src/superio/via/vt1211/vt1211.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/via/vt1211/vt1211.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -26,6 +26,7 @@
 #include <device/device.h>
 #include <device/pnp.h>
 #include <uart8250.h>
+#include <stdlib.h>
 
 #include "vt1211.h"
 #include "chip.h"
@@ -212,7 +213,7 @@
 	printk_debug("vt1211 enabling PNP devices.\n");
 	pnp_enable_devices(dev,
 			&ops,
-			sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]),
+			ARRAY_SIZE(pnp_dev_info),
 			pnp_dev_info);
 }
 

Modified: trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -30,6 +30,7 @@
 #include <uart8250.h>
 #include <pc80/keyboard.h>
 #include <pc80/mc146818rtc.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "w83627ehg.h"
 
@@ -93,7 +94,7 @@
 		0x48, 0x7f, 0x2a, /* Set SMBus base to 0x54 >> 1. */
 	};
 
-	for(i = 0; i < sizeof(hwm_reg_values)/sizeof(hwm_reg_values[0]); i += 3) {
+	for(i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
 		reg = hwm_reg_values[i];
 		value = pnp_read_index(base, reg);
 		value &= 0xff & (~(hwm_reg_values[i + 1]));
@@ -200,7 +201,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_winbond_w83627ehg_ops = {

Modified: trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -13,6 +13,7 @@
 #include <uart8250.h>
 #include <pc80/keyboard.h>
 #include <pc80/mc146818rtc.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "w83627hf.h"
 
@@ -83,7 +84,7 @@
                                                                             
 	};
 
-	for(i = 0; i<  sizeof(hwm_reg_values)/sizeof(hwm_reg_values[0]); i+=3 ) { 
+	for(i = 0; i<  ARRAY_SIZE(hwm_reg_values); i+=3 ) { 
 		reg = hwm_reg_values[i];	
 	 	value = pnp_read_index(base, reg);		
 		value &= 0xff & hwm_reg_values[i+1];
@@ -189,7 +190,7 @@
 static void enable_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_winbond_w83627hf_ops = {

Modified: trunk/coreboot-v2/src/superio/winbond/w83627thf/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627thf/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/winbond/w83627thf/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -12,6 +12,7 @@
 #include <bitops.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "w83627thf.h"
 
@@ -101,7 +102,7 @@
 static void enable_dev(device_t dev)
 {
 	pnp_enable_devices(dev, &ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_winbond_w83627thf_ops = {

Modified: trunk/coreboot-v2/src/superio/winbond/w83977f/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83977f/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/winbond/w83977f/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -26,6 +26,7 @@
 #include <bitops.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "w83977f.h"
 
@@ -109,7 +110,7 @@
 static void enable_dev(device_t dev)
 {
 	pnp_enable_devices(dev, &ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_winbond_w83977f_ops = {

Modified: trunk/coreboot-v2/src/superio/winbond/w83977tf/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83977tf/superio.c	2008-09-30 17:09:44 UTC (rev 3623)
+++ trunk/coreboot-v2/src/superio/winbond/w83977tf/superio.c	2008-10-01 12:52:52 UTC (rev 3624)
@@ -19,6 +19,7 @@
 #include <bitops.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <stdlib.h>
 #include "chip.h"
 #include "w83977tf.h"
 
@@ -105,7 +106,7 @@
 static void enable_dev(device_t dev)
 {
 	pnp_enable_devices(dev, &ops,
-		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_winbond_w83977tf_ops = {




From svn at coreboot.org  Wed Oct  1 15:10:39 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Oct 2008 15:10:39 +0200
Subject: [coreboot] r3625 - trunk/coreboot-v2/src/mainboard/asus/a8n_e
Message-ID: <mailman.2148.1355071389.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-10-01 15:10:39 +0200 (Wed, 01 Oct 2008)
New Revision: 3625

Modified:
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb
Log:
Enable all available devices on the ASUS A8N-E (trivial).

This is in preparation for actually making the devices work (which needs
some extra code). Also, fix the incorrect mainboard subsystem IDs.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb	2008-10-01 12:52:52 UTC (rev 3624)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb	2008-10-01 13:10:39 UTC (rev 3625)
@@ -165,7 +165,7 @@
           device pci 0.0 on end			# HT
           device pci 1.0 on			# LPC
             chip superio/ite/it8712f		# Super I/O
-              device pnp 2e.0 off		# Floppy
+              device pnp 2e.0 on		# Floppy
                 io 0x60 = 0x3f0
                 irq 0x70 = 6
                 drq 0x74 = 2
@@ -174,13 +174,14 @@
                 io 0x60 = 0x3f8
                 irq 0x70 = 4
               end
-              device pnp 2e.2 off		# Com2
+              device pnp 2e.2 off		# Com2 (N/A on this board)
                 io 0x60 = 0x2f8
                 irq 0x70 = 3
               end
               device pnp 2e.3 on		# Parallel port
                 io 0x60 = 0x378
                 irq 0x70 = 7
+                drq 0x74 = 3
               end
               device pnp 2e.4 on		# Environment controller
                 io 0x60 = 0x290
@@ -198,6 +199,7 @@
                 irq 0x71 = 2
               end
               device pnp 2e.7 on		# GPIO config
+                io 0x60 = 0x0800
                 # Set GPIO 1 & 2
                 io 0x25 = 0x0000
                 # Set GPIO 3 & 4
@@ -212,9 +214,17 @@
                 io 0xc8 = 0x0000
                 io 0xca = 0x0500
               end
-              device pnp 2e.8 off end		# Midi port
-              device pnp 2e.9 off end		# Game port
-              device pnp 2e.a off end		# IR
+              device pnp 2e.8 on		# Midi port
+                io 0x60 = 0x300
+                irq 0x70 = 10
+              end
+              device pnp 2e.9 on		# Game port
+                io 0x60 = 0x201
+              end
+              device pnp 2e.a off		# IR (N/A on this board)
+                io 0x60 = 0x310
+                irq 0x70 = 11
+              end
             end
           end
           device pci 1.1 on			# SM 0
@@ -245,8 +255,8 @@
           end
           device pci 2.0 on end			# USB 1.1
           device pci 2.1 on end			# USB 2
-          device pci 4.0 off end		# Onboard audio (ACI)
-          device pci 4.1 off end		# Onboard modem (MCI)
+          device pci 4.0 on end			# Onboard audio (ACI)
+          device pci 4.1 off end		# Onboard modem (MCI), N/A
           device pci 6.0 on end			# IDE
           device pci 7.0 on end			# SATA 1
           device pci 8.0 on end			# SATA 0

Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb	2008-10-01 12:52:52 UTC (rev 3624)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb	2008-10-01 13:10:39 UTC (rev 3625)
@@ -146,8 +146,8 @@
 default CONFIG_IOAPIC = 1
 default MAINBOARD_PART_NUMBER = "A8N-E"
 default MAINBOARD_VENDOR = "ASUS"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x10f1
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x2891
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a
 default STACK_SIZE = 8 * 1024
 default HEAP_SIZE = 16 * 1024
 # Only use the option table in a normal image.




From info at coresystems.de  Wed Oct  1 15:32:36 2008
From: info at coresystems.de (coreboot information)
Date: Wed, 01 Oct 2008 15:32:36 +0200
Subject: [coreboot] r3624 build service
Message-ID: <E1Kl1oi-0000XU-Tr@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "hailfinger" checked in revision 3624 to
the coreboot source repository and caused the following 
changes:

Change Log:
The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of
code to use it. That makes the code more readable and also less
error-prone.

Abuild tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>


Build Log:
Compilation of asus:m2v-mx_se is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3624&device=m2v-mx_se&vendor=asus
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3624&device=j7f24&vendor=jetway
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3624&device=epia-cn&vendor=via


If something broke during this checkin please be a pain 
in hailfinger's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Wed Oct  1 16:19:56 2008
From: info at coresystems.de (coreboot information)
Date: Wed, 01 Oct 2008 16:19:56 +0200
Subject: [coreboot] r3625 build service
Message-ID: <E1Kl2YW-0004Bn-RK@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "uwe" checked in revision 3625 to
the coreboot source repository and caused the following 
changes:

Change Log:
Enable all available devices on the ASUS A8N-E (trivial).

This is in preparation for actually making the devices work (which needs
some extra code). Also, fix the incorrect mainboard subsystem IDs.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of asus:m2v-mx_se is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3625&device=m2v-mx_se&vendor=asus
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3625&device=j7f24&vendor=jetway
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3625&device=epia-cn&vendor=via


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From c-d.hailfinger.devel.2006 at gmx.net  Wed Oct  1 15:23:49 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 01 Oct 2008 15:23:49 +0200
Subject: [coreboot] [PATCH v2] AMD DBM690T IRQ cleanup
Message-ID: <48E379E5.4080706@gmx.net>

Hi,

I decided to prepare a patch for the stuff I mentioned in the DBM690T
review.

Use easily readable macros to setup interrupt routing.
Change a few PCI bus/dev/fn to use hexadecimal numbers.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c
===================================================================
--- LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c	(Revision 3624)
+++ LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c	(Arbeitskopie)
@@ -122,94 +122,72 @@
 	smp_write_intsrc(mc, mp_ExtINT,
 			 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa,
 			 0x0, apicid_sb600, 0x0);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x1, apicid_sb600, 0x1);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x0, apicid_sb600, 0x2);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x3, apicid_sb600, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x4, apicid_sb600, 0x4);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x6, apicid_sb600, 0x6);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x7, apicid_sb600, 0x7);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0xc, apicid_sb600, 0xc);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0xd, apicid_sb600, 0xd);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0xe, apicid_sb600, 0xe);
 
+	/* ISA ints are edge-triggered, and usually originate from the ISA bus,
+	 * or its remainings.
+	 */
+#define ISA_INT(intr, pin) \
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, (intr), apicid_sb600, (pin))
+
+	ISA_INT(0x1, 0x1);
+	ISA_INT(0x0, 0x2);
+	ISA_INT(0x3, 0x3);
+	ISA_INT(0x4, 0x4);
+	ISA_INT(0x6, 0x6);
+	ISA_INT(0x7, 0x7);
+	ISA_INT(0xc, 0xc);
+	ISA_INT(0xd, 0xd);
+	ISA_INT(0xe, 0xe);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
+#define PCI_INT(bus, dev, fn, pin) \
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
+
 	/* usb */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 19 << 2 | 0, apicid_sb600, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 19 << 2 | 1, apicid_sb600, 0x11);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 19 << 2 | 2, apicid_sb600, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 19 << 2 | 3, apicid_sb600, 0x13);
+	PCI_INT(0, 0x13, 2, 0);
+	PCI_INT(0, 0x13, 2, 1);
+	PCI_INT(0, 0x13, 2, 2);
+	PCI_INT(0, 0x13, 2, 3);
 
 	/* sata */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 18 << 2 | 0, apicid_sb600, 22);
+	PCI_INT(0, 0x12, 2, 0);
 
 	/* HD Audio: b0:d20:f1:reg63 should be 0. */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 20 << 2 | 0, apicid_sb600, 16);
+	PCI_INT(0, 0x14, 2, 0);
 
 	/* on board NIC & Slot PCIE.  */
 	i = 2;
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[1], 0x5 << 2 | 0, apicid_sb600, 18);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[1], 0x5 << 2 | 1, apicid_sb600, 19);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[2], 0x0 << 2 | 0, apicid_sb600, 18);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[3], 0x0 << 2 | 0, apicid_sb600, 19);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[4], 0x0 << 2 | 0, apicid_sb600, 16);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[5], 0x0 << 2 | 0, apicid_sb600, 17);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[6], 0x0 << 2 | 0, apicid_sb600, 18);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[7], 0x0 << 2 | 0, apicid_sb600, 19);
+	PCI_INT(bus_rs690[1], 0x5, 2, 0);
+	PCI_INT(bus_rs690[1], 0x5, 2, 1);
+	PCI_INT(bus_rs690[2], 0x0, 2, 0);
+	PCI_INT(bus_rs690[3], 0x0, 2, 0);
+	PCI_INT(bus_rs690[4], 0x0, 2, 0);
+	PCI_INT(bus_rs690[5], 0x0, 2, 0);
+	PCI_INT(bus_rs690[6], 0x0, 2, 0);
+	PCI_INT(bus_rs690[7], 0x0, 2, 0);
 
 	/* PCI slots */
 	i += 6;
 	j = 5;
 	/* PCI_SLOT 0. */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 5 << 2 | 0, apicid_sb600, 20);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 5 << 2 | 1, apicid_sb600, 21);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 5 << 2 | 2, apicid_sb600, 22);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 5 << 2 | 3, apicid_sb600, 23);
+	PCI_INT(bus_sb600[1], 5, 2, 0);
+	PCI_INT(bus_sb600[1], 5, 2, 1);
+	PCI_INT(bus_sb600[1], 5, 2, 2);
+	PCI_INT(bus_sb600[1], 5, 2, 3);
 
 	/* PCI_SLOT 1. */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 6 << 2 | 0, apicid_sb600, 21);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 6 << 2 | 1, apicid_sb600, 22);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 6 << 2 | 2, apicid_sb600, 23);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 6 << 2 | 3, apicid_sb600, 20);
+	PCI_INT(bus_sb600[1], 6, 2, 0);
+	PCI_INT(bus_sb600[1], 6, 2, 1);
+	PCI_INT(bus_sb600[1], 6, 2, 2);
+	PCI_INT(bus_sb600[1], 6, 2, 3);
 
 	/* PCI_SLOT 2. */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 7 << 2 | 0, apicid_sb600, 22);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 7 << 2 | 1, apicid_sb600, 23);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 7 << 2 | 2, apicid_sb600, 20);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 7 << 2 | 3, apicid_sb600, 21);
+	PCI_INT(bus_sb600[1], 7, 2, 0);
+	PCI_INT(bus_sb600[1], 7, 2, 1);
+	PCI_INT(bus_sb600[1], 7, 2, 2);
+	PCI_INT(bus_sb600[1], 7, 2, 3);
 
 	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 	smp_write_intsrc(mc, mp_ExtINT,


-- 
http://www.hailfinger.org/




From tiagomnm at gmail.com  Wed Oct  1 15:35:19 2008
From: tiagomnm at gmail.com (Tiago Marques)
Date: Wed, 1 Oct 2008 14:35:19 +0100
Subject: [coreboot] Master degree student wanting to give some help.
In-Reply-To: <20080930144953.26824.qmail@stuge.se>
References: <5450d0b40809300420x46eca371s6705799e1e87cd4@mail.gmail.com>
	<20080930144953.26824.qmail@stuge.se>
Message-ID: <b1335fe90810010635jc25fe7euda301ca46581e325@mail.gmail.com>

Hi.

On Tue, Sep 30, 2008 at 3:49 PM, Peter Stuge <peter at stuge.se> wrote:

> Hi Cedric,
>
> Cedric RIVERA wrote:
> > I'm a french master degree student in Free Software ingeneering,
> > looking for a year project to join and I really love to be involved
> > in Coreboot community to :
> >
> >    improve AMD690G chipset support, or
> >    port coreboot-v3 to Gigabyte M57SLI-S4, I've got one to develop.
>
> I think these two are both great candidates. m57sli in v3 has already
> been started, so it is likely to be the simplest task. It would also
> be a good way to get familiar with the code and structure.
>
>
> >    Openmoko coreboot port or
>
> Probably not so useful. Is there a PCI bus in the Openmoko?
>
Why is this important? Supposedly, the next iteration of Intel's Atom
platform won't feature a PCI bus, coreboot won't work with it?


>
> > I just need that someone supervise my work and do, monthly, a
> > feedback to my teacher at the university to have a note.
> >
> > Son is someone interested ?
>
> You already have some offers but I'll add myself too. :) I'm
> interested in both 690 and m57sli in v3, but even more in K8/Fam10 in
> v3 in general because I think we need to make some (relatively) small
> design changes to make sure we get the most out of v3.
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From mats.andersson at gisladisker.se  Wed Oct  1 18:18:44 2008
From: mats.andersson at gisladisker.se (Mats Erik Andersson)
Date: Wed, 01 Oct 2008 18:18:44 +0200
Subject: [coreboot] flashrom: [PATCH] Support for AM29F002(N)B[BT]
Message-ID: <E1Kl4PU-0000fO-Fc@aun.bellman.mea>

Support for AM29F002(N)B[BT]. Fully tested on AM29F002NBT.
Probing, reading, and erasing use the Jedec-routines,
whereas writing resort to the recent write_en29f002a(),
since also these chips use a byte wise algorithm.

Signed-off-by: Mats Erik Andersson <mats.andersson at gisladisker.se>

---


Index: flashrom/flash.h
===================================================================
--- flashrom/flash.h	(revision 3624)
+++ flashrom/flash.h	(arbetskopia)
@@ -112,6 +112,8 @@
 #define ALLIANCE_ID		0x52	/* Alliance Semiconductor */
 
 #define AMD_ID			0x01	/* AMD */
+#define AM_29F002BT		0xB0
+#define AM_29F002BB		0x34
 #define AM_29F040B		0xA4
 #define AM_29LV040B		0x4F
 #define AM_29F016D		0xAD
Index: flashrom/flashchips.c
===================================================================
--- flashrom/flashchips.c	(revision 3624)
+++ flashrom/flashchips.c	(arbetskopia)
@@ -32,6 +32,8 @@
 	/**********************************************************************************************************************************************************************************************************************/
 	/* Vendor	Chip			Vendor ID	Chip ID			TODO	TODO		Test status	Probe function		Erase function			Write function		Read function */
 	/**********************************************************************************************************************************************************************************************************************/
+	{"AMD",	"Am29F002(N)BB",		AMD_ID,		AM_29F002BB,		256,	256,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_en29f002a},
+	{"AMD",	"Am29F002(N)BT",		AMD_ID,		AM_29F002BT,		256,	256,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_en29f002a},
 	{"AMD",		"Am29F016D",		AMD_ID,		AM_29F016D,		2048,	64 * 1024,	TEST_UNTESTED,	probe_29f040b,		erase_29f040b,			write_29f040b},
 	{"AMD",		"Am29F040B",		AMD_ID,		AM_29F040B,		512,	64 * 1024,	TEST_OK_PREW,	probe_29f040b,		erase_29f040b,			write_29f040b},
 	{"AMD",		"Am29LV040B",		AMD_ID,		AM_29LV040B,		512,	64 * 1024,	TEST_UNTESTED,	probe_29f040b,		erase_29f040b,			write_29f040b},



From mats.andersson at gisladisker.se  Wed Oct  1 18:04:18 2008
From: mats.andersson at gisladisker.se (Mats Erik Andersson)
Date: Wed, 01 Oct 2008 18:04:18 +0200
Subject: [coreboot] Is Coreboot selfmodifying? Award legacy Bios is!
Message-ID: <E1Kl4BW-0000eP-QL@aun.bellman.mea>

Hello all,

the cryptic subject of this message is due to my efforts
to verify that Flashrom is producing correct images.

After much practical testing I have been able to conclude
positively that the Award Bios 4.51 of a FIC mainboard
is rewriting the blocks

   0x0003800 - 0x00038fff     cleartext on system characteristica,
   0x0003a00 - 0x0003afff     pci-table.

at each reboot. Now I wonder if also Coreboot is using this opportunity
under some circumstances. It is not that I think it is a commendable
thing to do, instead it is a rather hazardous endeavour in my eyes.

Best regards,

Mats Erik Andersson



From jordan.crouse at amd.com  Wed Oct  1 01:31:28 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Tue, 30 Sep 2008 17:31:28 -0600
Subject: [coreboot] Bayou
Message-ID: <20080930233128.GA16731@cosmic.amd.com>

By demand, attached is a .gz of a patch of the most recent bayou
code.  This has been sitting about in its current format for about 3 months
now, and unfortunately we haven't been able to overcome the issues that
are preventing it from moving forward.  I feel strongly about what needs
to be done to improve both Bayou and coreboot, and those points have
been covered extensively in both e-mail and in IRC, so there is no point
in rehashing them here.

They say that the squeaky wheel gets the grease, and nowhere is that more
true then in open source software development. Right now Bayou isn't really
squeaking, and probably for good reason - there are much more
interesting fruits in coreboot land.

I give the community the bayou patch in the hope that some day one of us
will find a good use for it, and that when that time comes, somebody can
take this and make it work for them.

Thanks,
Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.
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From uwe at hermann-uwe.de  Wed Oct  1 17:12:12 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 1 Oct 2008 17:12:12 +0200
Subject: [coreboot] typo (was: Re: r3552 - in	trunk/payloads/libpayload:
	i386 include)
In-Reply-To: <1220011463.3700.1.camel@mattotaupa.wohnung.familie-menzel.net>
References: <E1KYqfJ-0000lF-Oj@mail.sourceforge.net>
	<1219994856.10225.23.camel@mattotaupa.wohnung.familie-menzel.net>
	<1220011463.3700.1.camel@mattotaupa.wohnung.familie-menzel.net>
Message-ID: <20081001151211.GF22678@greenwood>

On Fri, Aug 29, 2008 at 02:04:23PM +0200, Paul Menzel wrote:
> Am Freitag, den 29.08.2008, 09:27 +0200 schrieb Paul Menzel:
> > Am Freitag, den 29.08.2008, 01:12 +0200 schrieb svn at coreboot.org:
> > 
> 
> > Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
> 
> Thanks, r3552.

r3554, I think.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From rminnich at gmail.com  Wed Oct  1 18:02:07 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 09:02:07 -0700
Subject: [coreboot] current k8 diff
Message-ID: <13426df10810010902x3cdac8daw319516b5e651c8c6@mail.gmail.com>

This actually builds an m57sli but this time there is real dram init inside.

Please, I know that formatting is not always great, that is for
another day. You should see what I am starting from :-)
romcc, as wonderful as it is, got us into some really bad habits!

ron
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From mats.andersson at gisladisker.se  Wed Oct  1 11:21:19 2008
From: mats.andersson at gisladisker.se (Mats Erik Andersson)
Date: Wed, 01 Oct 2008 11:21:19 +0200
Subject: [coreboot] Tinycurses depends on active video console.
Message-ID: <E1KkxtX-0000Xd-AN@aun.bellman.mea>

Hello all,

may I point out that the flags "-Wall -Werror" prevents tinycurses
to compile in case only a serial console has been configured, but
no video output. The culprit is an unused but defined variable "c".
The naive solution is to condition the creation of "c" by the flag
CONFIG_VIDEO_CONSOLE.

Signed-off-by: Mats Erik Andersson <mats.andersson at gisladisker.se>



Index: libpayload/curses/tinycurses.c
===================================================================
--- libpayload/curses/tinycurses.c	(revision 3623)
+++ libpayload/curses/tinycurses.c	(arbetskopia)
@@ -736,8 +736,10 @@
 		for (x = win->_line[y].firstchar; x <= win->_line[y].lastchar; x++) {
 			attr_t attr = win->_line[y].text[x].attr;
 
+#ifdef CONFIG_VIDEO_CONSOLE
 			unsigned int c =
 				((int)color_pairs[PAIR_NUMBER(attr)]) << 8;
+#endif
 
 #ifdef CONFIG_SERIAL_CONSOLE
 			if (curses_flags & F_ENABLE_SERIAL) {



From patrick at georgi-clan.de  Wed Oct  1 18:34:00 2008
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 01 Oct 2008 18:34:00 +0200
Subject: [coreboot] Tinycurses depends on active video console.
In-Reply-To: <E1KkxtX-0000Xd-AN@aun.bellman.mea>
References: <E1KkxtX-0000Xd-AN@aun.bellman.mea>
Message-ID: <48E3A678.8010605@georgi-clan.de>

Mats Erik Andersson schrieb:
> Index: libpayload/curses/tinycurses.c
> ===================================================================
> --- libpayload/curses/tinycurses.c	(revision 3623)
> +++ libpayload/curses/tinycurses.c	(arbetskopia)
> @@ -736,8 +736,10 @@
>  		for (x = win->_line[y].firstchar; x <= win->_line[y].lastchar; x++) {
>  			attr_t attr = win->_line[y].text[x].attr;
>  
> +#ifdef CONFIG_VIDEO_CONSOLE
>  			unsigned int c =
>  				((int)color_pairs[PAIR_NUMBER(attr)]) << 8;
> +#endif
>  
>  #ifdef CONFIG_SERIAL_CONSOLE
>  			if (curses_flags & F_ENABLE_SERIAL) {
>   
how about just moving that variable down to the #ifdef block that uses 
it? color_pairs[] or attr aren't changed inbetween, afaics.




From avg at icyb.net.ua  Wed Oct  1 18:07:18 2008
From: avg at icyb.net.ua (Andriy Gapon)
Date: Wed, 01 Oct 2008 19:07:18 +0300
Subject: [coreboot] qemu emulation quirks: legacy memory attributes
Message-ID: <48E3A036.5090108@icyb.net.ua>


Guys,

I have an impression that qemu is used quite extensively for coreboot
code testing. But I've encountered some problems with its emulation of
essential hardware that I didn't have with bochs. This is with
non-coreboot code.

What do you think about the following:
http://thread.gmane.org/gmane.comp.emulators.qemu/30106
["register 20h" there should be changed to "register 59h"]

P.S.
bochs is really good, BTW, but qemu's speed is fascinating.

-- 
Andriy Gapon



From c-d.hailfinger.devel.2006 at gmx.net  Wed Oct  1 14:54:21 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 01 Oct 2008 14:54:21 +0200
Subject: [coreboot] [PATCH] v2: Use ARRAY_SIZE everywhere
In-Reply-To: <20080930021902.4297.qmail@stuge.se>
References: <48AECAA1.7030505@gmx.net> <20080930021902.4297.qmail@stuge.se>
Message-ID: <48E372FD.30107@gmx.net>

On 30.09.2008 04:19, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> -	for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
>> +	for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
>>  	     i++, a++) {
>>     
>
> Maybe lines like this should be folded? Maybe not? Dunno..
>   

I'll leave that for a separate patch.

> Acked-by: Peter Stuge <peter at stuge.se>
>   

Thanks! Committed in r3624.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From techie at whiterocker.com  Wed Oct  1 06:05:04 2008
From: techie at whiterocker.com (Chris Kilgour)
Date: Tue, 30 Sep 2008 21:05:04 -0700
Subject: [coreboot] coreboot gpxe
In-Reply-To: <13426df10809301043w6a7c6517t597be04c90244f8@mail.gmail.com>
References: <13426df10809300857k54d57c80p97ff4716f99612ea@mail.gmail.com>	<20080930172428.2011.qmail@stuge.se>
	<13426df10809301043w6a7c6517t597be04c90244f8@mail.gmail.com>
Message-ID: <48E2F6F0.8030405@whiterocker.com>


>> http://www.whiterocker.com/gpxe/
>>
>>     

FYI - libpayload-lplconsole.patch was put together against libpayload r
3345.  I'm pretty sure the patch doesn't apply cleanly to the latest
libpayload.

Chris.



From uwe at hermann-uwe.de  Wed Oct  1 15:24:54 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 1 Oct 2008 15:24:54 +0200
Subject: [coreboot] [PATCH] Fix ITE IT8712F pnp_dev_info[] items
Message-ID: <20081001132453.GE22678@greenwood>

See patch. The pnp_dev_info[] was incomplete and partly wrong, due to
me doing blind copy-paste. After checking with the datasheet I _think_
the contents are correct now, but it would be nice if someone could
double-check that.

Various other superios have the same problem I'm afraid, I'll post more
patches later...


For parallel port there are _two_ base addresses (0x60/0x61 and 0x62/0x63),
but most other superios/boards only use the first one (I assume the
second set is only needed for some non-standard parallel port modes?)

Also, I left IT8712F_GPIO "empty" like this

  {&ops, IT8712F_GPIO, },

even though it does have 0x60/0x61, 0x62/0x63, and 0x64/0x65 base address
registers, but those are "SMI# Normal Run Access Base Address" and
"Simple I/O Base Address" and "Panel Button De-bounce Base Address",
which I guess we don't need (?)


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From rminnich at gmail.com  Wed Oct  1 16:13:49 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 07:13:49 -0700
Subject: [coreboot] r877 - in coreboot-v3: arch/x86/amd/model_fxx
	mainboard/gigabyte/m57sli northbridge/amd/k8
	southbridge/nvidia/mcp55
In-Reply-To: <13426df10810010702n1633fff3kb764852c6eedbd23@mail.gmail.com>
References: <48E343A1.4000003@coresystems.de>
	<13426df10810010702n1633fff3kb764852c6eedbd23@mail.gmail.com>
Message-ID: <13426df10810010713p2ea8b04eme5886b717813acd8@mail.gmail.com>

On Wed, Oct 1, 2008 at 7:02 AM, ron minnich <rminnich at gmail.com> wrote:

>> What's in stage0 that makes it so big? Is that part really required in
>> stage0?
>
> hyptertransport setup has to be in stage0. I can't see a way around it.
>

The issue is that the mcp55 needs this function:
set_ht_link_buffer_counts_chain and that in turn brings in all of
incoherent_ht. I will see if I can seperate these out.

ron



From hawke at hawkesnest.net  Wed Oct  1 17:42:04 2008
From: hawke at hawkesnest.net (Alex Mauer)
Date: Wed, 01 Oct 2008 10:42:04 -0500
Subject: [coreboot] FILO patch: color command: Report correct error
Message-ID: <gc05oc$2iv$2@ger.gmane.org>

Attached please find a patch which does:
*Make the FILO 'color' command set a more helpful errnum rather than
using the one from the integer parser.

Signed-off-by: Alex Mauer <hawke at hawkensest.net>

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From hawke at hawkesnest.net  Wed Oct  1 00:09:16 2008
From: hawke at hawkesnest.net (Alex Mauer)
Date: Tue, 30 Sep 2008 17:09:16 -0500
Subject: [coreboot] FILO patch: color command: make color byte like VGA.
Message-ID: <gbu82d$n3g$1@ger.gmane.org>

Attached please find a patch for FILO which:

* Swaps the order of the nybbles in the color setting byte to make it
the same as the traditional VGA BIOS color byte.

Signed-off-by: Alex Mauer <hawke at hawkesnest.net>

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From hawke at hawkesnest.net  Wed Oct  1 00:55:40 2008
From: hawke at hawkesnest.net (Alex Mauer)
Date: Tue, 30 Sep 2008 17:55:40 -0500
Subject: [coreboot] FILO patch: color command: Report correct error
Message-ID: <gbuapc$u50$1@ger.gmane.org>

Attached please find a patch which does:
*Make the FILO 'color' command set a more helpful errnum rather than 
using the one from the integer parser.

Signed-off-by: Alex Mauer <hawke at hawkensest.net>
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From hawke at hawkesnest.net  Wed Oct  1 17:41:53 2008
From: hawke at hawkesnest.net (Alex Mauer)
Date: Wed, 01 Oct 2008 10:41:53 -0500
Subject: [coreboot] FILO patch: color command: make color byte like VGA.
Message-ID: <gc05o1$2iv$1@ger.gmane.org>

Attached please find a patch for FILO which:

* Swaps the order of the nybbles in the color setting byte to make it
the same as the traditional VGA BIOS color byte.

Signed-off-by: Alex Mauer <hawke at hawkesnest.net>


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From rminnich at gmail.com  Wed Oct  1 16:02:18 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 07:02:18 -0700
Subject: [coreboot] r877 - in coreboot-v3: arch/x86/amd/model_fxx
	mainboard/gigabyte/m57sli northbridge/amd/k8
	southbridge/nvidia/mcp55
In-Reply-To: <48E343A1.4000003@coresystems.de>
References: <48E343A1.4000003@coresystems.de>
Message-ID: <13426df10810010702n1633fff3kb764852c6eedbd23@mail.gmail.com>

On Wed, Oct 1, 2008 at 2:32 AM, Stefan Reinauer <stepan at coresystems.de> wrote:
> svn at coreboot.org wrote:
>> Author: rminnich
>> Date: 2008-10-01 09:23:05 +0200 (Wed, 01 Oct 2008)
>> New Revision: 877
>>
>> Modified:
>>    coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c
>>    coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h
>>    coreboot-v3/northbridge/amd/k8/dqs.c
>>    coreboot-v3/northbridge/amd/k8/raminit.c
>>    coreboot-v3/southbridge/nvidia/mcp55/ide.c
>>    coreboot-v3/southbridge/nvidia/mcp55/lpc.c
>>    coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
>>    coreboot-v3/southbridge/nvidia/mcp55/pci.c
>>    coreboot-v3/southbridge/nvidia/mcp55/pcie.c
>>    coreboot-v3/southbridge/nvidia/mcp55/sata.c
>>    coreboot-v3/southbridge/nvidia/mcp55/usb2.c
>> Log:
>> m57sli mostly builds again. The stage0 is too large at 24k.
>> We need to figure out if we should just grow stage0. My inclination is
>> to say 'yes'.
>>
>
> What's in stage0 that makes it so big? Is that part really required in
> stage0?

hyptertransport setup has to be in stage0. I can't see a way around it.

>
> If so, we need to grow stage0. But we should try to answer that question
> first.


yes, I was able to hold the line on serengeti but m57sli needs more.

ron



From rminnich at gmail.com  Wed Oct  1 19:40:57 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 10:40:57 -0700
Subject: [coreboot] Is Coreboot selfmodifying? Award legacy Bios is!
In-Reply-To: <E1Kl4BW-0000eP-QL@aun.bellman.mea>
References: <E1Kl4BW-0000eP-QL@aun.bellman.mea>
Message-ID: <13426df10810011040tfc0d0d3mce580442f52a8794@mail.gmail.com>

we don't rewrite flash. Yes, this is hazardous I think as well.

ron



From rminnich at gmail.com  Wed Oct  1 16:41:52 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 07:41:52 -0700
Subject: [coreboot] r877 - in coreboot-v3: arch/x86/amd/model_fxx
	mainboard/gigabyte/m57sli northbridge/amd/k8
	southbridge/nvidia/mcp55
In-Reply-To: <13426df10810010713p2ea8b04eme5886b717813acd8@mail.gmail.com>
References: <48E343A1.4000003@coresystems.de>
	<13426df10810010702n1633fff3kb764852c6eedbd23@mail.gmail.com>
	<13426df10810010713p2ea8b04eme5886b717813acd8@mail.gmail.com>
Message-ID: <13426df10810010741x63eceec0xe7c985c7dbb34b59@mail.gmail.com>

here's a possible resolution.

ron
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From Marc.Jones at amd.com  Wed Oct  1 19:53:14 2008
From: Marc.Jones at amd.com (Marc Jones)
Date: Wed, 1 Oct 2008 11:53:14 -0600
Subject: [coreboot] [PATCH v2] AMD DBM690T IRQ cleanup
In-Reply-To: <48E379E5.4080706@gmx.net>
References: <48E379E5.4080706@gmx.net>
Message-ID: <48E3B90A.2030304@amd.com>

Carl-Daniel Hailfinger wrote:
> Hi,
> 
> I decided to prepare a patch for the stuff I mentioned in the DBM690T
> review.
> 
> Use easily readable macros to setup interrupt routing.
> Change a few PCI bus/dev/fn to use hexadecimal numbers.
> 
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

The cleanup is nice but you didn't translate correctly. See below.



> 
> Index: LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c
> ===================================================================
> --- LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c	(Revision 3624)
> +++ LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c	(Arbeitskopie)
> @@ -122,94 +122,72 @@
>  	smp_write_intsrc(mc, mp_ExtINT,
>  			 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa,
>  			 0x0, apicid_sb600, 0x0);
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
> -			 bus_isa, 0x1, apicid_sb600, 0x1);
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
> -			 bus_isa, 0x0, apicid_sb600, 0x2);
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
> -			 bus_isa, 0x3, apicid_sb600, 0x3);
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
> -			 bus_isa, 0x4, apicid_sb600, 0x4);
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
> -			 bus_isa, 0x6, apicid_sb600, 0x6);
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
> -			 bus_isa, 0x7, apicid_sb600, 0x7);
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
> -			 bus_isa, 0xc, apicid_sb600, 0xc);
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
> -			 bus_isa, 0xd, apicid_sb600, 0xd);
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
> -			 bus_isa, 0xe, apicid_sb600, 0xe);
>  
> +	/* ISA ints are edge-triggered, and usually originate from the ISA bus,
> +	 * or its remainings.
> +	 */
> +#define ISA_INT(intr, pin) \
> +	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, (intr), apicid_sb600, (pin))
> +
> +	ISA_INT(0x1, 0x1);
> +	ISA_INT(0x0, 0x2);
> +	ISA_INT(0x3, 0x3);
> +	ISA_INT(0x4, 0x4);
> +	ISA_INT(0x6, 0x6);
> +	ISA_INT(0x7, 0x7);
> +	ISA_INT(0xc, 0xc);
> +	ISA_INT(0xd, 0xd);
> +	ISA_INT(0xe, 0xe);
> +
> +	/* PCI interrupts are level triggered, and are
> +	 * associated with a specific bus/device/function tuple.
> +	 */
> +#define PCI_INT(bus, dev, fn, pin) \
> +        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
> +
>  	/* usb */
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
> -			 0, 19 << 2 | 0, apicid_sb600, 0x10);
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
> -			 0, 19 << 2 | 1, apicid_sb600, 0x11);
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
> -			 0, 19 << 2 | 2, apicid_sb600, 0x12);
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
> -			 0, 19 << 2 | 3, apicid_sb600, 0x13);
> +	PCI_INT(0, 0x13, 2, 0);
> +	PCI_INT(0, 0x13, 2, 1);
> +	PCI_INT(0, 0x13, 2, 2);
> +	PCI_INT(0, 0x13, 2, 3);

This should be:
	PCI_INT(0, 0x13, 0, 0x10);
	PCI_INT(0, 0x13, 1, 0x11);
	PCI_INT(0, 0x13, 2, 0x12);
	PCI_INT(0, 0x13, 3, 0x13);

I think you put the << 2 in the fn throughout the patch.


Marc


-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors




From svn at coreboot.org  Wed Oct  1 19:54:56 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Oct 2008 19:54:56 +0200
Subject: [coreboot] r878 - in coreboot-v3/mainboard/amp: . tinygx
Message-ID: <mailman.2149.1355071390.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-10-01 19:54:56 +0200 (Wed, 01 Oct 2008)
New Revision: 878

Modified:
   coreboot-v3/mainboard/amp/Kconfig
   coreboot-v3/mainboard/amp/tinygx/dts
   coreboot-v3/mainboard/amp/tinygx/initram.c
   coreboot-v3/mainboard/amp/tinygx/irq_tables.h
   coreboot-v3/mainboard/amp/tinygx/stage1.c
Log:
Coding style and documentation fixes for AMP TinyGX (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: coreboot-v3/mainboard/amp/Kconfig
===================================================================
--- coreboot-v3/mainboard/amp/Kconfig	2008-10-01 07:23:05 UTC (rev 877)
+++ coreboot-v3/mainboard/amp/Kconfig	2008-10-01 17:54:56 UTC (rev 878)
@@ -33,7 +33,7 @@
 	select SUPERIO_ITE_IT8716F
 	select PIRQ_TABLE
 	help
-	  SMP TinyGX
+	  AMP TinyGX
 
 endchoice
 

Modified: coreboot-v3/mainboard/amp/tinygx/dts
===================================================================
--- coreboot-v3/mainboard/amp/tinygx/dts	2008-10-01 07:23:05 UTC (rev 877)
+++ coreboot-v3/mainboard/amp/tinygx/dts	2008-10-01 17:54:56 UTC (rev 878)
@@ -37,7 +37,7 @@
 		pci at f,0 {
 			/config/("southbridge/amd/cs5536/dts");
 			/* Interrupt enables for LPC bus.
-			 *  Each bit is an IRQ 0-15. */
+			 * Each bit is an IRQ 0-15. */
 			lpc_serirq_enable = "0x000010da";
 			/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
 			lpc_serirq_polarity = "0x0000EF25";

Modified: coreboot-v3/mainboard/amp/tinygx/initram.c
===================================================================
--- coreboot-v3/mainboard/amp/tinygx/initram.c	2008-10-01 07:23:05 UTC (rev 877)
+++ coreboot-v3/mainboard/amp/tinygx/initram.c	2008-10-01 17:54:56 UTC (rev 878)
@@ -37,7 +37,7 @@
 extern int smbus_read_byte(u16 device, u8 address);
 
 #define MANUALCONF 0		/* Do automatic strapped PLL config */
-#define PLLMSRHI 0x00001490	/* manual settings for the PLL */
+#define PLLMSRHI 0x00001490	/* Manual settings for the PLL */
 #define PLLMSRLO 0x02000030
 #define DIMM0 ((u8) 0xA0)
 #define DIMM1 ((u8) 0xA2)
@@ -59,31 +59,28 @@
 	u8 spdbyte;
 
 	printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device);
-
 	spdbyte = smbus_read_byte(device, address);
-
 	printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbyte);
 
 	return spdbyte;
 }
 
 /**
-  * Placeholder in case we ever need it. Since this file is a
-  * template for other motherboards, we want this here and we want the
-  * call in the right place.
-  */
-
+ * Placeholder in case we ever need it. Since this file is a template for
+ * other boards, we want this here and we want the call in the right place.
+ */
 static void mb_gpio_init(void)
 {
 	/* Early mainboard specific GPIO setup */
 }
 
 /**
-  * main for initram for the AMD DB800 development platform.
-  * It might seem that you could somehow do these functions in, e.g., the cpu
-  * code, but the order of operations and what those operations are is VERY
-  * strongly mainboard dependent. It's best to leave it in the mainboard code.
-  */
+ * main() for initram.
+ *
+ * It might seem that you could somehow do these functions in, e.g., the CPU
+ * code, but the order of operations and what those operations are is VERY
+ * strongly mainboard dependent. It's best to leave it in the mainboard code.
+ */
 int main(void)
 {
 	printk(BIOS_DEBUG, "Hi there from initram (stage1) main!\n");
@@ -110,8 +107,8 @@
 	sdram_enable(DIMM0, DIMM1);
 	printk(BIOS_DEBUG, "done sdram enable\n");
 
-	/* Check low memory */
-	/*ram_check(0x00000000, 640*1024); */
+	/* Check low memory. */
+	/* ram_check(0x00000000, 640 * 1024); */
 
 	printk(BIOS_DEBUG, "stage1 returns\n");
 	return 0;

Modified: coreboot-v3/mainboard/amp/tinygx/irq_tables.h
===================================================================
--- coreboot-v3/mainboard/amp/tinygx/irq_tables.h	2008-10-01 07:23:05 UTC (rev 877)
+++ coreboot-v3/mainboard/amp/tinygx/irq_tables.h	2008-10-01 17:54:56 UTC (rev 878)
@@ -41,14 +41,10 @@
 #define L_PIRQD 4		/* Means Slot INTx# Connects To Chipset INTD# */
 
 /*
- * AMD DB800 interrupt wiring.
+ * AMP TinyGX interrupt wiring.
  *
- * Devices are:
- *
- * FIXME
- *
+ * Devices are: FIXME
  */
-
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
@@ -62,7 +58,7 @@
 	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
 	0x00,			/* Checksum */
 	{
-		/* If you change the number of entries, change IRQ_SLOT_COUNT above! */
+		/* If you change the number of entries, change SLOT_COUNT above! */
 
 		/* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
 

Modified: coreboot-v3/mainboard/amp/tinygx/stage1.c
===================================================================
--- coreboot-v3/mainboard/amp/tinygx/stage1.c	2008-10-01 07:23:05 UTC (rev 877)
+++ coreboot-v3/mainboard/amp/tinygx/stage1.c	2008-10-01 17:54:56 UTC (rev 878)
@@ -36,18 +36,18 @@
 void hardware_stage1(void)
 {
  	void it8716f_enable_serial(u8 dev, u8 serial, u16 iobase);
+
 	post_code(POST_START_OF_MAIN);
 	geodelx_msr_init();
-
 	cs5536_stage1();
 
-	/* NOTE: must do this AFTER the early_setup!
-	 * it is counting on some early MSR setup
-	 * for cs5536.
+	/*
+	 * Note: Must do this AFTER the early_setup! It is counting on some
+	 * early MSR setup for CS5536.
 	 */
 	cs5536_disable_internal_uart();
+
  	it8716f_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
-
 }
 
 void mainboard_pre_payload(void)




From rminnich at gmail.com  Wed Oct  1 20:02:56 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 11:02:56 -0700
Subject: [coreboot] splash screen
In-Reply-To: <13426df10809230447r7395364ay36ee8dacf1fba0f8@mail.gmail.com>
References: <13426df10809230447r7395364ay36ee8dacf1fba0f8@mail.gmail.com>
Message-ID: <13426df10810011102q161792cdy56f6c6a537a9349a@mail.gmail.com>

here is the current version of the splash screen. Now, I *know* there
are others of you out there who have helped. If you want your logo on
here, please send it to me -- .svg is preferred.

What is a good mode for int 10 4f02 to use for this?

thanks

ron



From rminnich at gmail.com  Wed Oct  1 20:03:34 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 11:03:34 -0700
Subject: [coreboot] splash screen
In-Reply-To: <Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
References: <13426df10809230447r7395364ay36ee8dacf1fba0f8@mail.gmail.com>
	<20080923140452.GB26027@cosmic.amd.com>
	<20080923172805.12279.qmail@stuge.se>
	<20080923173708.GB30198@cosmic.amd.com>
	<20080923174449.17274.qmail@stuge.se>
	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
Message-ID: <13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>

OK I should read my mail more ... mode 3 it is.

ron



From rminnich at gmail.com  Wed Oct  1 20:04:35 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 11:04:35 -0700
Subject: [coreboot] splash screen
In-Reply-To: <13426df10809230447r7395364ay36ee8dacf1fba0f8@mail.gmail.com>
References: <13426df10809230447r7395364ay36ee8dacf1fba0f8@mail.gmail.com>
Message-ID: <13426df10810011104k3ac4d5e5y1fdefb4201027262@mail.gmail.com>

forgot the attach, sorry.

ron
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From svn at coreboot.org  Wed Oct  1 20:29:22 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Oct 2008 20:29:22 +0200
Subject: [coreboot] r879 - in coreboot-v3: . arch/x86 device lib mainboard
	mainboard/amd mainboard/amp mainboard/gigabyte mainboard/pcengines
Message-ID: <mailman.2150.1355071390.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-10-01 20:29:22 +0200 (Wed, 01 Oct 2008)
New Revision: 879

Modified:
   coreboot-v3/Kconfig
   coreboot-v3/arch/x86/Kconfig
   coreboot-v3/device/Kconfig
   coreboot-v3/lib/Kconfig
   coreboot-v3/lib/console.c
   coreboot-v3/mainboard/Kconfig
   coreboot-v3/mainboard/amd/Kconfig
   coreboot-v3/mainboard/amp/Kconfig
   coreboot-v3/mainboard/gigabyte/Kconfig
   coreboot-v3/mainboard/pcengines/Kconfig
Log:
Minor fixes and improvements for v3, mostly for Kconfig files (trivial).

 - Coding style and whitespace fixes.
 - Remove obsolete comments, fix incorrect ones.
 - Use the full/canonical name of mainboards/vendors everywhere.
 - Update the list of USB Debug capable chipsets from
   http://www.coreboot.org/EHCI_Debug_Port.
 - s/LB/CB/ for the CONSOLE_PREFIX kconfig option.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: coreboot-v3/Kconfig
===================================================================
--- coreboot-v3/Kconfig	2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/Kconfig	2008-10-01 18:29:22 UTC (rev 879)
@@ -64,7 +64,7 @@
 	bool "Enable whole-program optimizations (DANGEROUS)"
 	depends EXPERT && EXPERIMENTAL
 	help
-	  Enable gcc -fwhole-program -combine for select code.
+	  Enable 'gcc -fwhole-program -combine' for select code.
 	  Needs lots of annotation in stage1 and stage2.
 	  Works for initram only.
 	  This increases compile time (no parallel compilation possible
@@ -111,8 +111,6 @@
 config SUPERIO_ITE_IT8716F
 	boolean
 
-# Source all northbridge/southbridge/superio Kconfig files:
-
 menu "Payload"
 
 config PAYLOAD_ELF_LOADER
@@ -122,8 +120,8 @@
 	  This option allows an unparsed ELF paylaod to be added and loaded.
 
 choice
-        prompt "Payload type"
-        default PAYLOAD_NONE
+	prompt "Payload type"
+	default PAYLOAD_NONE
 
 config PAYLOAD_ELF
 	bool "An ELF executable payload file"

Modified: coreboot-v3/arch/x86/Kconfig
===================================================================
--- coreboot-v3/arch/x86/Kconfig	2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/arch/x86/Kconfig	2008-10-01 18:29:22 UTC (rev 879)
@@ -60,62 +60,62 @@
 	boolean
 	depends CPU_AMD_K8
 	help
-	  Whether to configure a High Precision Event Timer. Note that HPETs are 
-		known to be bug-prone. 
+	  Whether to configure a High Precision Event Timer (HPET). Note that
+	  HPETs are known to be bug-prone.
 
 config K8_REV_F_SUPPORT
 	hex
 	default 0 if CPU_AMD_K8
 	help
-		Whether to include rev F support
+	  Whether to include rev F support.
 
 config K8_SCAN_PCI_BUS
 	hex
 	default 0 if CPU_AMD_K8
 	help
-		Whether to scan the PCI bus in stage1
+	  Whether to scan the PCI bus in stage1.
 
 config K8_ALLOCATE_IO_RANGE
 	hex
 	default 0 if CPU_AMD_K8
 	help
-		Whether to allocate IO space in stage1
-	
+	  Whether to allocate I/O space in stage1.
+
 config K8_ALLOCATE_MMIO_RANGE
 	hex
 	default 0 if CPU_AMD_K8
 	help
-		Whether to allocate MMIO space in stage1. 
-		Comment from code:  
-		Do we need allocate MMIO? Currently we direct 
-		last 64M to southbridge link (sblink) only,  
-		We can not lose access to last 4M range to ROM. 
-	
+	  Whether to allocate MMIO space in stage1.
+
+	  Comment from code: Do we need allocate MMIO? Currently we direct
+	  last 64M to southbridge link (sblink) only. We can not lose access
+	  to last 4M range to ROM.
+
 config LOGICAL_CPUS
 	hex
 	depends CPU_AMD_K8
 	default 1
 	help
-		How many logical CPUs there are. Fix me.
+	  How many logical CPUs there are. FIXME.
 
 config MAX_PHYSICAL_CPUS
 	hex
 	depends CPU_AMD_K8
 	default 1
 	help
-		Max number of physical CPUs (sockets)
+	  Maximum number of physical CPUs (sockets).
 
 config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
 	hex
 	default 0 if CPU_AMD_K8
 	help
-		Config with 4 CPUs even if more are installed
+	  Config with 4 CPUs even if more are installed.
 
 config CROSS_BAR_47_56
 	hex
 	default 0 if CPU_AMD_K8
 	help
-		Configure for the type of crossbar on the mainboard. 
+	  Configure for the type of crossbar on the mainboard.
 
 config OPTION_TABLE
 	boolean
@@ -128,14 +128,14 @@
 	boolean
 	help
 	  This option is used to determine whether the mainboard has
-	  a PIRQ table, which is the old way to set up interrupt routing. 
+	  a PIRQ table, which is the old way to set up interrupt routing.
 	  It is usually set in mainboard/*/Kconfig.
 
 config ACPI_TABLE
 	boolean
 	help
 	  This option is used to determine whether the mainboard has
-	  an ACPI table. 
+	  an ACPI table.
 	  It is usually set in mainboard/*/Kconfig.
 
 config SMP
@@ -143,9 +143,8 @@
 	depends CPU_I586 || CPU_AMD_K8
 	default 0
 	help
-	  This option is used to enable certain functions to make 
-	  coreboot work correctly on symmetric multi processor
-	  systems.
+	  This option is used to enable certain functions to make coreboot
+	  work correctly on symmetric multi processor systems.
 	  It is usually set in mainboard/*/Kconfig.
 
 config IOAPIC
@@ -153,7 +152,7 @@
 	depends ARCH_X86 && CPU_AMD_K8
 	default 0
 	help
-	  If you want to configure an IOAPIC, set this. 
+	  If you want to configure an IOAPIC, set this.
 
 config CARBASE
 	hex
@@ -177,36 +176,37 @@
 	default 0x1000 if CPU_AMD_GEODELX
 	default 0x2000 if CPU_AMD_K8
 	help
-	  This option sets the top of the memory area, in KiB, 
+	  This option sets the top of the memory area, in KiB,
 	  used for coreboot.
 
 config K8_HT_FREQ_1G_SUPPORT
 	hex
 	default 1 if CPU_AMD_K8
 	help
-		1 Ghz. support. Opteron E0 or later can support 
-		1G HT, but still depends on the mainboard
+	  1 GHz support. Opteron E0 or later can support 1G HT,
+	  but still depends on the mainboard.
 
 config HT_FREQ_800MHZ
 	hex
 	default 1 if CPU_AMD_K8
 	help
-		Can we run HT at 800 Mhz
+	  Can we run HT at 800 MHz.
 
 config USBDEBUG_DIRECT
 	boolean
 	depends SOUTHBRIDGE_NVIDIA_MCP55
 	default 0
 	help
-		Determines if we enable USB Direct debugging. If you don't have a dongle, 
-		this is probably of no value to you.
+	  Determines if we enable USB Direct debugging. If you don't have
+	  a dongle, this is probably of no value to you.
 
 config APIC_ID_OFFSET
 	hex "APIC ID offset"
 	default 0x10
 	depends IOAPIC
 	help
-		This is entirely mainboard dependent. 0x10 is a *typical* setting but not always a good setting. 
+	  This is entirely mainboard dependent. 0x10 is a *typical* setting
+	  but not always a good setting.
 
 menu "Debugging"
 
@@ -214,6 +214,6 @@
 	bool "Test CAR area"
 	default n
 	help
-		Test the CAR area after it has been set up.
+	  Test the CAR area after it has been set up.
 
 endmenu

Modified: coreboot-v3/device/Kconfig
===================================================================
--- coreboot-v3/device/Kconfig	2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/device/Kconfig	2008-10-01 18:29:22 UTC (rev 879)
@@ -36,7 +36,6 @@
 	  execute PCI option ROMs natively (32bit x86 system required),
 	  in an emulator (x86emu), or ignore option ROM execution.
 
-
 config PCI_OPTION_ROM_RUN_X86EMU
 	bool "x86emu"
 	select PCI_OPTION_ROM_RUN
@@ -47,7 +46,6 @@
 	  x86emu is slow, big and safe. All 16bit x86 code is executed
 	  in an encapsulated environment where it can not break out.
 
-
 config PCI_OPTION_ROM_RUN_VM86
 	bool "vm86"
 	select PCI_OPTION_ROM_RUN
@@ -64,7 +62,6 @@
 	bool "Disabled"
 	help
 	  Do not execute PCI option ROMs at all.
-
 	  If you choose this option, VGA plugin cards will not be initialized.
 
 endchoice
@@ -74,7 +71,7 @@
 	bool "Initialize all VGA cards"
 	depends PCI_OPTION_ROM_RUN
 	help
-	  If you enable this option, all VGA cards will be initialized
+	  If you enable this option, all VGA cards will be initialized.
 	  If you disable this option, only the first VGA card will be
 	  initialized.
 
@@ -82,7 +79,7 @@
 	bool "Initialize onboard VGA first"
 	depends PCI_OPTION_ROM_RUN
 	help
-	  Initialize onboard VGA chips before any plugin VGA cards 
+	  Initialize onboard VGA chips before any plugin VGA cards
 	  are initialized.
 
 endmenu
@@ -99,17 +96,17 @@
 	bool "64 bit prefetchable memory addresses"
 	depends CPU_AMD_K8
 	help
-		Enable support for 64-bit prefetchable memory addresses in PCI. 
+	  Enable support for 64-bit prefetchable memory addresses in PCI.
 
 config HW_MEM_HOLE_SIZEK
 	hex "HW memory hole size in KB"
 	depends CPU_AMD_K8
 	default 0x1000
 	help
-		Some chipsets support setting up a "hole" at the top of memory. It is essentially 
-		a hole torn in the physical address space so that you can fit non-memory resources
-		(e.g. flash) at the top of the 4G address space. Given that this only happens on machines
-		with lots of memory, the default 4 MB is a very reasonable value. 
-		
+	  Some chipsets support setting up a "hole" at the top of memory.
+	  It is essentially a hole torn in the physical address space so that
+	  you can fit non-memory resources (e.g. flash) at the top of the 4G
+	  address space. Given that this only happens on machines with lots
+	  of memory, the default 4 MB is a very reasonable value.
 
 endmenu

Modified: coreboot-v3/lib/Kconfig
===================================================================
--- coreboot-v3/lib/Kconfig	2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/lib/Kconfig	2008-10-01 18:29:22 UTC (rev 879)
@@ -200,15 +200,21 @@
 	  Debug Port capability. Controllers which are known to work:
 
 	    * 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)
-	    * 10de:0088 NVIDIA MCP2A
-	    * 10de:005b NVIDIA CK804
-	    * 10de:036d NVIDIA MCP55
+	    * 8086:24cd Intel ICH4/ICH4-M
 	    * 8086:24dd Intel ICH5
 	    * 8086:265c Intel ICH6
 	    * 8086:268c Intel 631xESB/632xESB/3100
 	    * 8086:27cc Intel ICH7
 	    * 8086:2836 Intel ICH8
 	    * 8086:283a Intel ICH8
+	    * 8086:293a Intel ICH9
+	    * 10de:0088 NVIDIA MCP2A
+	    * 10de:005b NVIDIA CK804
+	    * 10de:026e NVIDIA MCP51
+	    * 10de:036d NVIDIA MCP55
+	    * 10de:03f2 NVIDIA MCP61
+	    * 1002:4386 ATI/AMD SB600
+	    * 1106:3104 VIA VX800
 
 	  See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list.
 
@@ -216,12 +222,12 @@
 	depends EXPERT && (CONSOLE_SERIAL || CONSOLE_USB)
 
 config CONSOLE_PREFIX
-	bool "Prefix all console output with '(LB)'"
+	bool "Prefix all console output with '(CB)'"
 	depends EXPERT && (CONSOLE_SERIAL || CONSOLE_USB)
 	default n
 	help
 	  When you enable this option, coreboot will prefix each line of
-	  console output with '(LB)'.
+	  console output with '(CB)'.
 
 config CONSOLE_BUFFER
 	boolean "Console memory buffer support"

Modified: coreboot-v3/lib/console.c
===================================================================
--- coreboot-v3/lib/console.c	2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/lib/console.c	2008-10-01 18:29:22 UTC (rev 879)
@@ -116,7 +116,7 @@
 #ifdef CONFIG_CONSOLE_PREFIX
 		uart8250_tx_byte(TTYSx_BASE, '\n');
 		uart8250_tx_byte(TTYSx_BASE, '(');
-		uart8250_tx_byte(TTYSx_BASE, 'L');
+		uart8250_tx_byte(TTYSx_BASE, 'C');
 		uart8250_tx_byte(TTYSx_BASE, 'B');
 		uart8250_tx_byte(TTYSx_BASE, ')');
 		uart8250_tx_byte(TTYSx_BASE, ' ');

Modified: coreboot-v3/mainboard/Kconfig
===================================================================
--- coreboot-v3/mainboard/Kconfig	2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/mainboard/Kconfig	2008-10-01 18:29:22 UTC (rev 879)
@@ -40,8 +40,7 @@
 config VENDOR_AMP
 	bool "AMP"
 	help
-	  Select this option for various systems from 
-	  Advanced Micro Devices, Inc.
+	  Select this option for various systems from AMP.
 
 config VENDOR_ARTECGROUP
 	bool "Artec Group"
@@ -49,9 +48,9 @@
 	  Select this option for various systems from the Artec Group.
 
 config VENDOR_GIGABYTE
-	bool "Gigabyte"
+	bool "GIGABYTE"
 	help
-	  Select this option for various systems from Gigabyte
+	  Select this option for various systems from GIGABYTE.
 
 config VENDOR_EMULATION
 	bool "Emulated systems"

Modified: coreboot-v3/mainboard/amd/Kconfig
===================================================================
--- coreboot-v3/mainboard/amd/Kconfig	2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/mainboard/amd/Kconfig	2008-10-01 18:29:22 UTC (rev 879)
@@ -56,7 +56,7 @@
 	select SUPERIO_WINBOND_W83627HF
 	select IOAPIC
 	help
-	  AMD Serengeti
+	  AMD Serengeti development board.
 
 endchoice
 

Modified: coreboot-v3/mainboard/amp/Kconfig
===================================================================
--- coreboot-v3/mainboard/amp/Kconfig	2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/mainboard/amp/Kconfig	2008-10-01 18:29:22 UTC (rev 879)
@@ -33,7 +33,7 @@
 	select SUPERIO_ITE_IT8716F
 	select PIRQ_TABLE
 	help
-	  AMP TinyGX
+	  AMP TinyGX board.
 
 endchoice
 

Modified: coreboot-v3/mainboard/gigabyte/Kconfig
===================================================================
--- coreboot-v3/mainboard/gigabyte/Kconfig	2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/mainboard/gigabyte/Kconfig	2008-10-01 18:29:22 UTC (rev 879)
@@ -24,7 +24,7 @@
 	depends on VENDOR_GIGABYTE
 
 config BOARD_GIGABYTE_M57SLI
-	bool "M57SLI"
+	bool "GA-M57SLI-S4"
 	select ARCH_X86
 	select OPTION_TABLE
 	select CPU_AMD_K8
@@ -33,7 +33,7 @@
 	select SUPERIO_ITE_IT8716F
 	select IOAPIC
 	help
-	  Gigabyte M57SLI
+	  GIGABYTE GA-M57SLI-S4.
 
 endchoice
 

Modified: coreboot-v3/mainboard/pcengines/Kconfig
===================================================================
--- coreboot-v3/mainboard/pcengines/Kconfig	2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/mainboard/pcengines/Kconfig	2008-10-01 18:29:22 UTC (rev 879)
@@ -24,7 +24,7 @@
 	depends on VENDOR_PCENGINES
 
 config BOARD_PCENGINES_ALIX1C
-	bool "ALIX1.C"
+	bool "ALIX.1C"
 	select ARCH_X86
 	select CPU_AMD_GEODELX
 	select OPTION_TABLE
@@ -33,7 +33,7 @@
 	select SUPERIO_WINBOND_W83627HF
 	select PIRQ_TABLE
 	help
-	  PC Engines ALIX1.C.
+	  PC Engines ALIX.1C.
 
 config BOARD_PCENGINES_ALIX2C3
 	bool "ALIX.2C3"




From joe at settoplinux.org  Wed Oct  1 20:41:36 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Wed, 01 Oct 2008 14:41:36 -0400
Subject: [coreboot] splash screen
In-Reply-To: <13426df10810011104k3ac4d5e5y1fdefb4201027262@mail.gmail.com>
References: <13426df10809230447r7395364ay36ee8dacf1fba0f8@mail.gmail.com>
	<13426df10810011104k3ac4d5e5y1fdefb4201027262@mail.gmail.com>
Message-ID: <f2b2fed4cbdb3d0f3d61e3a6f96a341f@imap.1and1.com>


Sweet, I like it :-) 
Jordan, are you going to be able to make this a reality for libpayload?

On Wed, 1 Oct 2008 11:04:35 -0700, "ron minnich" <rminnich at gmail.com>
wrote:
> forgot the attach, sorry.
> 
> ron
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From jordan.crouse at amd.com  Wed Oct  1 20:47:13 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 1 Oct 2008 12:47:13 -0600
Subject: [coreboot] splash screen
In-Reply-To: <13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>
References: <13426df10809230447r7395364ay36ee8dacf1fba0f8@mail.gmail.com>
	<20080923140452.GB26027@cosmic.amd.com>
	<20080923172805.12279.qmail@stuge.se>
	<20080923173708.GB30198@cosmic.amd.com>
	<20080923174449.17274.qmail@stuge.se>
	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>
Message-ID: <20081001184713.GD22980@cosmic.amd.com>

On 01/10/08 11:03 -0700, ron minnich wrote:
> OK I should read my mail more ... mode 3 it is.

No - not mode 3.  You'll want to kick into a VESA mode of suitable
size so you can draw directly to the framebuffer.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From jordan.crouse at amd.com  Wed Oct  1 20:48:11 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 1 Oct 2008 12:48:11 -0600
Subject: [coreboot] splash screen
In-Reply-To: <f2b2fed4cbdb3d0f3d61e3a6f96a341f@imap.1and1.com>
References: <13426df10809230447r7395364ay36ee8dacf1fba0f8@mail.gmail.com>
	<13426df10810011104k3ac4d5e5y1fdefb4201027262@mail.gmail.com>
	<f2b2fed4cbdb3d0f3d61e3a6f96a341f@imap.1and1.com>
Message-ID: <20081001184811.GE22980@cosmic.amd.com>

On 01/10/08 14:41 -0400, Joseph Smith wrote:
> 
> Sweet, I like it :-) 
> Jordan, are you going to be able to make this a reality for libpayload?

I help those who help themselves - I already said that somebody else
would need to implement the VESA driver.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From rminnich at gmail.com  Wed Oct  1 20:49:21 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 11:49:21 -0700
Subject: [coreboot] splash screen
In-Reply-To: <20081001184713.GD22980@cosmic.amd.com>
References: <13426df10809230447r7395364ay36ee8dacf1fba0f8@mail.gmail.com>
	<20080923140452.GB26027@cosmic.amd.com>
	<20080923172805.12279.qmail@stuge.se>
	<20080923173708.GB30198@cosmic.amd.com>
	<20080923174449.17274.qmail@stuge.se>
	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>
	<20081001184713.GD22980@cosmic.amd.com>
Message-ID: <13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>

On Wed, Oct 1, 2008 at 11:47 AM, Jordan Crouse <jordan.crouse at amd.com> wrote:
> On 01/10/08 11:03 -0700, ron minnich wrote:
>> OK I should read my mail more ... mode 3 it is.
>
> No - not mode 3.  You'll want to kick into a VESA mode of suitable
> size so you can draw directly to the framebuffer.
>
I'm trying x117 now?

ron



From mats.andersson at gisladisker.se  Wed Oct  1 20:51:53 2008
From: mats.andersson at gisladisker.se (Mats Erik Andersson)
Date: Wed, 01 Oct 2008 20:51:53 +0200
Subject: [coreboot] coreboot gpxe
Message-ID: <E1Kl6nh-0000iy-Vz@aun.bellman.mea>

Chris Kilgour <techie at whiterocker.com> wrote
> >> http://www.whiterocker.com/gpxe/
> >>
> >>     
> 
> FYI - libpayload-lplconsole.patch was put together against libpayload r
> 3345.  I'm pretty sure the patch doesn't apply cleanly to the latest
> libpayload.
> 
> Chris.
> 

I can provide an almost complete aliment in that direction.
The patch provided below is constructed against todays trunk,
and it solves everything except the build step

    build/lib/lplconsole.o(.text+0x9c3): I funktionen "cb_parse_header":
    : undefined reference to `strncmp'

arising at the very last "ls -N -T ....." command. I had no really good
idea as to the best inclusion path to "strncmp()", and therefore I had
to leave the patchwork at that point. Most of you are more clever than
me in this respect.

Please forgive me for intruding,

Mats Erik Andersson

----


Index: libpayload/curses/tinycurses.c
===================================================================
--- libpayload/curses/tinycurses.c	(revision 3623)
+++ libpayload/curses/tinycurses.c	(arbetskopia)
@@ -736,8 +736,10 @@
 		for (x = win->_line[y].firstchar; x <= win->_line[y].lastchar; x++) {
 			attr_t attr = win->_line[y].text[x].attr;
 
+#ifdef CONFIG_VIDEO_CONSOLE
 			unsigned int c =
 				((int)color_pairs[PAIR_NUMBER(attr)]) << 8;
+#endif
 
 #ifdef CONFIG_SERIAL_CONSOLE
 			if (curses_flags & F_ENABLE_SERIAL) {
Index: libpayload/Makefile
===================================================================
--- libpayload/Makefile	(revision 3623)
+++ libpayload/Makefile	(arbetskopia)
@@ -95,12 +95,45 @@
 STACKPROTECT += $(call cc-option, -fno-stack-protector,)
 
 # TODO: Re-add -Os as soon as we find out why it caused problems.
-CFLAGS := -Wall -Werror $(STACKPROTECT) -nostdinc $(INCLUDES) -ffreestanding
+CFLAGS := -Wall -Werror $(STACKPROTECT) -ggdb -nostdinc $(INCLUDES) -ffreestanding
 
 all: lib
 
-lib: prepare $(obj)/lib/libpayload.a copystuff
+lib: prepare $(obj)/lib/libpayload.a copystuff $(obj)/lib/lplconsole.o
 
+LPL_CONSOLE_OBJS = $(obj)/libc/console.o $(obj)/drivers/pci.o \
+	$(obj)/i386/timer.o $(obj)/i386/sysinfo.o $(obj)/i386/coreboot.o \
+	$(obj)/libc/ipchecksum.o $(obj)/i386/virtual.o
+
+ifeq ($(CONFIG_SERIAL_CONSOLE),y)
+LPL_CONSOLE_OBJS += $(obj)/drivers/serial.o
+endif
+
+ifeq ($(CONFIG_PC_KEYBOARD),y)
+LPL_CONSOLE_OBJS += $(obj)/drivers/keyboard.o
+endif
+
+ifeq ($(CONFIG_VIDEO_CONSOLE),y)
+LPL_CONSOLE_OBJS += $(obj)/drivers/video/font8x16.o \
+	$(obj)/drivers/video/video.o 
+endif
+
+ifeq ($(CONFIG_VGA_VIDEO_CONSOLE),y)
+LPL_CONSOLE_OBJS += $(obj)/drivers/video/vga.o
+endif
+
+ifeq ($(CONFIG_GEODE_VIDEO_CONSOLE),y)
+LPL_CONSOLE_OBJS += $(obj)/drivers/video/geode.o
+endif
+
+$(obj)/lib/lplconsole.o: $(LPL_CONSOLE_OBJS)
+	$(LD) -r -o $@.tmp $(LPL_CONSOLE_OBJS)
+	objcopy --redefine-sym putchar=lpl_putchar --redefine-sym getchar=lpl_getchar \
+		--redefine-sym havekey=lpl_havekey --redefine-sym console_init=lpl_console_init \
+		--redefine-sym udelay=lpl_udelay --redefine-sym mdelay=lpl_mdelay \
+		--redefine-sym ndelay=lpl_ndelay \
+		$@.tmp $@
+
 # Copy libpayload.a and head.o into $(src)/lib where lpgcc et al expect them.
 copystuff: $(obj)/$(ARCHDIR-y)/head.S.o $(obj)/lib/libpayload.a
 	$(Q)cp $(obj)/$(ARCHDIR-y)/head.S.o $(src)/lib/$(ARCHDIR-y)/head.o



From joe at settoplinux.org  Wed Oct  1 21:01:43 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Wed, 01 Oct 2008 15:01:43 -0400
Subject: [coreboot] splash screen
In-Reply-To: <20081001184811.GE22980@cosmic.amd.com>
References: <13426df10809230447r7395364ay36ee8dacf1fba0f8@mail.gmail.com>
	<13426df10810011104k3ac4d5e5y1fdefb4201027262@mail.gmail.com>
	<f2b2fed4cbdb3d0f3d61e3a6f96a341f@imap.1and1.com>
	<20081001184811.GE22980@cosmic.amd.com>
Message-ID: <fec8d8ba8dafac65dd2e17f0f65e110b@imap.1and1.com>




On Wed, 1 Oct 2008 12:48:11 -0600, Jordan Crouse <jordan.crouse at amd.com>
wrote:
> On 01/10/08 14:41 -0400, Joseph Smith wrote:
>>
>> Sweet, I like it :-)
>> Jordan, are you going to be able to make this a reality for libpayload?
> 
> I help those who help themselves - I already said that somebody else
> would need to implement the VESA driver.
> 
I'm not sure what you mean by that???


-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From peter at stuge.se  Wed Oct  1 21:05:43 2008
From: peter at stuge.se (Peter Stuge)
Date: Wed, 1 Oct 2008 21:05:43 +0200
Subject: [coreboot] qemu emulation quirks: legacy memory attributes
In-Reply-To: <48E3A036.5090108@icyb.net.ua>
References: <48E3A036.5090108@icyb.net.ua>
Message-ID: <20081001190543.8591.qmail@stuge.se>

Andriy Gapon wrote:
> I have an impression that qemu is used quite extensively for
> coreboot code testing.

I think that's exaggerating. qemu is handy, but in general testing is
not our strong suit. Also, qemu is only useful for testing coreboot
code that is not board-specific, and that code is often already
better understood/easier than board-specific code. To test
board-specific tricky stuff we need actual hardware or a simulator
like SimNow.


> What do you think about the following:
> http://thread.gmane.org/gmane.comp.emulators.qemu/30106
> ["register 20h" there should be changed to "register 59h"]

Interesting. It's possible that we've never been bit by this. I'm
also not a big qemu user so I hope others can comment too.


//Peter



From peter at stuge.se  Wed Oct  1 21:44:24 2008
From: peter at stuge.se (Peter Stuge)
Date: Wed, 1 Oct 2008 21:44:24 +0200
Subject: [coreboot] Some v3 Kconfig options into dts?
Message-ID: <20081001194424.18100.qmail@stuge.se>

Thanks for the cleanup Uwe! Reading it through I saw several options
that I think should be in dts files instead. Please comment.


svn at coreboot.org wrote:
>  config K8_SCAN_PCI_BUS
> +	  Whether to scan the PCI bus in stage1.
>  
>  config K8_ALLOCATE_IO_RANGE
> +	  Whether to allocate I/O space in stage1.
>  
>  config K8_ALLOCATE_MMIO_RANGE
> +	  Whether to allocate MMIO space in stage1.

We'll have to add some text about when any of these should be enabled
too. Later.


>  config LOGICAL_CPUS
> +	  How many logical CPUs there are. FIXME.
>  
>  config MAX_PHYSICAL_CPUS
> +	  Maximum number of physical CPUs (sockets).

dts?


>  config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
> +	  Config with 4 CPUs even if more are installed.

But I think this should stay in Kconfig.


>  config CROSS_BAR_47_56
> +	  Configure for the type of crossbar on the mainboard.

dts?


>  	help
>  	  This option is used to determine whether the mainboard has
> +	  a PIRQ table, which is the old way to set up interrupt routing.
>  	  It is usually set in mainboard/*/Kconfig.
>  
>  config ACPI_TABLE
>  	boolean
>  	help
>  	  This option is used to determine whether the mainboard has
> +	  an ACPI table.
>  	  It is usually set in mainboard/*/Kconfig.

dts?


>  config SMP

>  	depends CPU_I586 || CPU_AMD_K8
>  	default 0
>  	help
> +	  This option is used to enable certain functions to make coreboot
> +	  work correctly on symmetric multi processor systems.
>  	  It is usually set in mainboard/*/Kconfig.

Could this be derived from the number of logical CPUs?


>  config IOAPIC
> @@ -153,7 +152,7 @@
>  	depends ARCH_X86 && CPU_AMD_K8
>  	default 0
>  	help
> +	  If you want to configure an IOAPIC, set this.

Will the builder really have an opinion on this? Isn't it chip
dependent? (ie -> dts?)


>  config K8_HT_FREQ_1G_SUPPORT
> +	  1 GHz support. Opteron E0 or later can support 1G HT,
> +	  but still depends on the mainboard.

dts?


>  config HT_FREQ_800MHZ
> +	  Can we run HT at 800 MHz.

dts?


>  config USBDEBUG_DIRECT
>  	depends SOUTHBRIDGE_NVIDIA_MCP55

Chip specific and board specific so a chip dts setting that is
filtered through the board dts and can make a Kconfig option visible
that the builder can use to disabled USB debug output?


>  config APIC_ID_OFFSET
> +	  This is entirely mainboard dependent.

dts?


//Peter



From cirdec.arevir at gmail.com  Wed Oct  1 10:40:24 2008
From: cirdec.arevir at gmail.com (Cedric RIVERA)
Date: Wed, 1 Oct 2008 10:40:24 +0200
Subject: [coreboot] Master degree student wanting to give some help.
In-Reply-To: <20080930144953.26824.qmail@stuge.se>
References: <5450d0b40809300420x46eca371s6705799e1e87cd4@mail.gmail.com>
	<20080930144953.26824.qmail@stuge.se>
Message-ID: <5450d0b40810010140l2ac3e6c3na08c7d0a2442889e@mail.gmail.com>

  Hi Peter,

  Thank you for your positive answer and your welcome.

  Well I start with m57sli, soldering first ;-) and then flashing eeprom to
become free. I need some time to understand the coreboot structure and so
there is some risk that I ask you, all you, for very stupid things but I'm
sure you will be happy to kidding me well ...
  I appreciate your offer to supervise my work on this project and so I'll
accept it too, it could be many supervisor !

Thank you, one more time, I'm so happy with this project !

Have a good day Coreboot people !

Cedric.


2008/9/30 Peter Stuge <peter at stuge.se>

> Hi Cedric,
>
> Cedric RIVERA wrote:
> > I'm a french master degree student in Free Software ingeneering,
> > looking for a year project to join and I really love to be involved
> > in Coreboot community to :
> >
> >    improve AMD690G chipset support, or
> >    port coreboot-v3 to Gigabyte M57SLI-S4, I've got one to develop.
>
> I think these two are both great candidates. m57sli in v3 has already
> been started, so it is likely to be the simplest task. It would also
> be a good way to get familiar with the code and structure.
>
>
> >    Openmoko coreboot port or
>
> Probably not so useful. Is there a PCI bus in the Openmoko?
>
>
> > I just need that someone supervise my work and do, monthly, a
> > feedback to my teacher at the university to have a note.
> >
> > Son is someone interested ?
>
> You already have some offers but I'll add myself too. :) I'm
> interested in both 690 and m57sli in v3, but even more in K8/Fam10 in
> v3 in general because I think we need to make some (relatively) small
> design changes to make sure we get the most out of v3.
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From jordan.crouse at amd.com  Wed Oct  1 22:00:17 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 1 Oct 2008 14:00:17 -0600
Subject: [coreboot] splash screen
In-Reply-To: <13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
References: <13426df10809230447r7395364ay36ee8dacf1fba0f8@mail.gmail.com>
	<20080923140452.GB26027@cosmic.amd.com>
	<20080923172805.12279.qmail@stuge.se>
	<20080923173708.GB30198@cosmic.amd.com>
	<20080923174449.17274.qmail@stuge.se>
	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>
	<20081001184713.GD22980@cosmic.amd.com>
	<13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
Message-ID: <20081001200017.GF22980@cosmic.amd.com>

On 01/10/08 11:49 -0700, ron minnich wrote:
> On Wed, Oct 1, 2008 at 11:47 AM, Jordan Crouse <jordan.crouse at amd.com> wrote:
> > On 01/10/08 11:03 -0700, ron minnich wrote:
> >> OK I should read my mail more ... mode 3 it is.
> >
> > No - not mode 3.  You'll want to kick into a VESA mode of suitable
> > size so you can draw directly to the framebuffer.
> >
> I'm trying x117 now?

I think 117 is reasonable.  Just recall that our font is 8x16(ish), so
we don't want too big a screen that we can't read the text.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From jordan.crouse at amd.com  Wed Oct  1 22:02:48 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 1 Oct 2008 14:02:48 -0600
Subject: [coreboot] coreboot gpxe
In-Reply-To: <E1Kl6nh-0000iy-Vz@aun.bellman.mea>
References: <E1Kl6nh-0000iy-Vz@aun.bellman.mea>
Message-ID: <20081001200248.GG22980@cosmic.amd.com>

On 01/10/08 20:51 +0200, Mats Erik Andersson wrote:
> Chris Kilgour <techie at whiterocker.com> wrote
> > >> http://www.whiterocker.com/gpxe/
> > >>
> > >>     
> > 
> > FYI - libpayload-lplconsole.patch was put together against libpayload r
> > 3345.  I'm pretty sure the patch doesn't apply cleanly to the latest
> > libpayload.
> > 
> > Chris.
> > 
> 
> I can provide an almost complete aliment in that direction.
> The patch provided below is constructed against todays trunk,
> and it solves everything except the build step
> 
>     build/lib/lplconsole.o(.text+0x9c3): I funktionen "cb_parse_header":
>     : undefined reference to `strncmp'
> 
> arising at the very last "ls -N -T ....." command. I had no really good
> idea as to the best inclusion path to "strncmp()", and therefore I had
> to leave the patchwork at that point. Most of you are more clever than
> me in this respect.
 
Hmmm - strncmp() should be in there - are you sure you are pointing
at the libpayload.a library?

Jordan




From svn at coreboot.org  Wed Oct  1 22:16:58 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Oct 2008 22:16:58 +0200
Subject: [coreboot] r3626 - trunk/util/superiotool
Message-ID: <mailman.2151.1355071390.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-10-01 22:16:58 +0200 (Wed, 01 Oct 2008)
New Revision: 3626

Modified:
   trunk/util/superiotool/fintek.c
   trunk/util/superiotool/ite.c
   trunk/util/superiotool/smsc.c
Log:
Add some more Super I/O IDs/names (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/util/superiotool/fintek.c
===================================================================
--- trunk/util/superiotool/fintek.c	2008-10-01 13:10:39 UTC (rev 3625)
+++ trunk/util/superiotool/fintek.c	2008-10-01 20:16:58 UTC (rev 3626)
@@ -67,6 +67,8 @@
 			{0x30,0xf0,0xf1,EOT},
 			{0x00,0x00,0x00,EOT}},
 		{EOT}}},
+	{0x0581, "F8000", {	/* Fintek/ASUS F8000 */
+		{EOT}}},
 	{EOT}
 };
 

Modified: trunk/util/superiotool/ite.c
===================================================================
--- trunk/util/superiotool/ite.c	2008-10-01 13:10:39 UTC (rev 3625)
+++ trunk/util/superiotool/ite.c	2008-10-01 20:16:58 UTC (rev 3626)
@@ -318,6 +318,8 @@
 			{0x30,0x60,0x61,0x70,0xf0,EOT},
 			{0x00,0x03,0x10,0x0b,0x00,EOT}},
 		{EOT}}},
+	{0x8720, "IT8720F", {	/* From sensors-detect */
+		{EOT}}},
 	{0x8726, "IT8726F", {
 		/* Datasheet wrongly says that the ID is 0x8716. */
 		{EOT}}},

Modified: trunk/util/superiotool/smsc.c
===================================================================
--- trunk/util/superiotool/smsc.c	2008-10-01 13:10:39 UTC (rev 3625)
+++ trunk/util/superiotool/smsc.c	2008-10-01 20:16:58 UTC (rev 3626)
@@ -426,6 +426,8 @@
 		{EOT}}},
 	{0x62, "LPC47S45x", {
 		{EOT}}},
+	{0x67, "EMC2700LPC", {	/* From sensors-detect */
+		{EOT}}},
 	{0x6b, "LPC47M292", {	/* From sensors-detect */
 		{EOT}}},
 	{0x6e, "LPC47B387", {	/* TODO: Not yet in sensors-detect */
@@ -507,10 +509,18 @@
 		{EOT}}},
 	{0x81, "SCH5307", {
 		{EOT}}},
+	{0x83, "SCH5514D", {	/* From sensors-detect */
+		{EOT}}},
 	{0x85, "SCH5317", {	/* From sensors-detect */
+		/* The SCH5317 can have either 0x85 or 0x8c as device ID. */
 		{EOT}}},
+	{0x86, "SCH5127", {	/* From sensors-detect */
+		{EOT}}},
 	{0x89, "SCH5027", {	/* From sensors-detect (no public datasheet) */
 		{EOT}}},
+	{0x8c, "SCH5317", {	/* From sensors-detect */
+		/* The SCH5317 can have either 0x85 or 0x8c as device ID. */
+		{EOT}}},
 	{0x90, "SCH4307", {	/* From sensors-detect */
 		{EOT}}},
 




From jordan at chalmers.se  Wed Oct  1 22:37:16 2008
From: jordan at chalmers.se (Ulf Jordan)
Date: Wed, 1 Oct 2008 22:37:16 +0200 (CEST)
Subject: [coreboot] Tinycurses depends on active video console.
In-Reply-To: <48E3A678.8010605@georgi-clan.de>
References: <E1KkxtX-0000Xd-AN@aun.bellman.mea>
	<48E3A678.8010605@georgi-clan.de>
Message-ID: <Pine.LNX.4.63.0810012231230.28225@elfpc10.elmagn.chalmers.se>

On Wed, 1 Oct 2008, Patrick Georgi wrote:

> Mats Erik Andersson schrieb:
>> Index: libpayload/curses/tinycurses.c
>> ===================================================================
>> --- libpayload/curses/tinycurses.c	(revision 3623)
>> +++ libpayload/curses/tinycurses.c	(arbetskopia)
>> @@ -736,8 +736,10 @@
>>  		for (x = win->_line[y].firstchar; x <= 
>> win->_line[y].lastchar; x++) {
>>  			attr_t attr = win->_line[y].text[x].attr;
>>  +#ifdef CONFIG_VIDEO_CONSOLE
>>  			unsigned int c =
>>  				((int)color_pairs[PAIR_NUMBER(attr)]) << 8;
>> +#endif
>>   #ifdef CONFIG_SERIAL_CONSOLE
>>  			if (curses_flags & F_ENABLE_SERIAL) {
>> 
> how about just moving that variable down to the #ifdef block that uses it? 
> color_pairs[] or attr aren't changed inbetween, afaics.

I agree, it seems better to move it down to the video console block where 
it is actually used. The attached patch does exactly that, and is compile 
and runtime tested with coreinfo+libpayload+coreboot-v3 under QEMU.

/ulf
-------------- next part --------------
Fix tinycurses compilation when only serial console is enabled (unused variable
c caught by -Wall -Werror). Thanks to Mats Erik Andersson for spotting this.

Signed-off-by: Ulf Jordan <jordan at chalmers.se>

Index: libpayload/curses/tinycurses.c
===================================================================
--- libpayload/curses/tinycurses.c	(revision 3625)
+++ libpayload/curses/tinycurses.c	(working copy)
@@ -736,9 +736,6 @@
 		for (x = win->_line[y].firstchar; x <= win->_line[y].lastchar; x++) {
 			attr_t attr = win->_line[y].text[x].attr;
 
-			unsigned int c =
-				((int)color_pairs[PAIR_NUMBER(attr)]) << 8;
-
 #ifdef CONFIG_SERIAL_CONSOLE
 			if (curses_flags & F_ENABLE_SERIAL) {
 				ch = win->_line[y].text[x].chars[0];
@@ -806,6 +803,9 @@
 			}
 #endif
 #ifdef CONFIG_VIDEO_CONSOLE
+			unsigned int c =
+				((int)color_pairs[PAIR_NUMBER(attr)]) << 8;
+
 			c = SWAP_RED_BLUE(c);
 
 			if (curses_flags & F_ENABLE_CONSOLE) {

From info at coresystems.de  Wed Oct  1 22:53:42 2008
From: info at coresystems.de (coreboot information)
Date: Wed, 01 Oct 2008 22:53:42 +0200
Subject: [coreboot] r3626 build service
Message-ID: <E1Kl8ha-000610-Kb@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "uwe" checked in revision 3626 to
the coreboot source repository and caused the following 
changes:

Change Log:
Add some more Super I/O IDs/names (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of asus:m2v-mx_se is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3626&device=m2v-mx_se&vendor=asus
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3626&device=j7f24&vendor=jetway
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3626&device=epia-cn&vendor=via


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From Marc.Jones at amd.com  Wed Oct  1 22:57:03 2008
From: Marc.Jones at amd.com (Marc Jones)
Date: Wed, 1 Oct 2008 14:57:03 -0600
Subject: [coreboot] [v2][patch] update k8 fid/vid setup
In-Reply-To: <48E2471D.5030905@amd.com>
References: <48AF20BE.1040609@amd.com> <20080930051342.8336.qmail@stuge.se>
	<48E2471D.5030905@amd.com>
Message-ID: <48E3E41F.4000603@amd.com>

Marc Jones wrote:
> Peter Stuge wrote:
>> Marc Jones wrote:
>>> Update K8 FID/VID setup. Add support for 100MHz FIDs (revG).
>>>
>>> Signed-off-by: Marc Jones <marc.jones at amd.com>
>>
>> Looks good.
>>
>> Acked-by: Peter Stuge <peter at stuge.se>
>>
> 
> Thanks Peter, I was going to repost this with some changes. I think that 
> there is a corner case I didn't correctly account for. :)
> 


Resubmitting this patch. I think I worked out all the corner cases and 
made it a little easier to understand.

Thanks,
Marc



-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors
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From rminnich at gmail.com  Wed Oct  1 23:09:31 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 14:09:31 -0700
Subject: [coreboot] Master degree student wanting to give some help.
In-Reply-To: <5450d0b40810010140l2ac3e6c3na08c7d0a2442889e@mail.gmail.com>
References: <5450d0b40809300420x46eca371s6705799e1e87cd4@mail.gmail.com>
	<20080930144953.26824.qmail@stuge.se>
	<5450d0b40810010140l2ac3e6c3na08c7d0a2442889e@mail.gmail.com>
Message-ID: <13426df10810011409n41b616f7v5149149872dea0ca@mail.gmail.com>

Cedric this is good news. You'll be working on v3 right :-)

ron



From rminnich at gmail.com  Wed Oct  1 23:18:49 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 14:18:49 -0700
Subject: [coreboot] Some v3 Kconfig options into dts?
In-Reply-To: <20081001194424.18100.qmail@stuge.se>
References: <20081001194424.18100.qmail@stuge.se>
Message-ID: <13426df10810011418m483427b4k55835bf4f41de6c0@mail.gmail.com>

On Wed, Oct 1, 2008 at 12:44 PM, Peter Stuge <peter at stuge.se> wrote:

> svn at coreboot.org wrote:
>>  config K8_SCAN_PCI_BUS
>> +       Whether to scan the PCI bus in stage1.
>>

I adopted this from v2 but it would only be a mainboard issue; it
should never be in dts since it's not an option anyone should ever
set.
>>  config K8_ALLOCATE_IO_RANGE
>> +       Whether to allocate I/O space in stage1.
>>
>>  config K8_ALLOCATE_MMIO_RANGE
>> +       Whether to allocate MMIO space in stage1.
>

same.

>>  config LOGICAL_CPUS
>> +       How many logical CPUs there are. FIXME.
>>

should always be determined dynamically by what cpus are installed.

>>  config MAX_PHYSICAL_CPUS
>> +       Maximum number of physical CPUs (sockets).
>
> dts?
>

This comes down to wires. I don't see it in the dts.

>
>>  config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
>> +       Config with 4 CPUs even if more are installed.
>
> But I think this should stay in Kconfig.
>

yes. It's a bizarre variable which I hope to remove some day.

>
>>  config CROSS_BAR_47_56
>> +       Configure for the type of crossbar on the mainboard.
>
> dts?

no. It's wires.

>
>
>>       help
>>         This option is used to determine whether the mainboard has
>> +       a PIRQ table, which is the old way to set up interrupt routing.
>>         It is usually set in mainboard/*/Kconfig.
>>
>>  config ACPI_TABLE
>>       boolean
>>       help
>>         This option is used to determine whether the mainboard has
>> +       an ACPI table.
>>         It is usually set in mainboard/*/Kconfig.
>
> dts?

no. it's a build option.

>
>
>>  config SMP
>
>>       depends CPU_I586 || CPU_AMD_K8
>>       default 0
>>       help
>> +       This option is used to enable certain functions to make coreboot
>> +       work correctly on symmetric multi processor systems.
>>         It is usually set in mainboard/*/Kconfig.
>
> Could this be derived from the number of logical CPUs?

Yes. this is not an OS, it's a BIOS, and SMP should always be enabled.
>
>
>>  config IOAPIC
>> @@ -153,7 +152,7 @@
>>       depends ARCH_X86 && CPU_AMD_K8
>>       default 0
>>       help
>> +       If you want to configure an IOAPIC, set this.
>
> Will the builder really have an opinion on this? Isn't it chip
> dependent? (ie -> dts?)

it's something they should never want to see or change. Not even dts.

>
>
>>  config K8_HT_FREQ_1G_SUPPORT
>> +       1 GHz support. Opteron E0 or later can support 1G HT,
>> +       but still depends on the mainboard.
>
> dts?

no, it's a mainboard issue.
>
>
>>  config HT_FREQ_800MHZ
>> +       Can we run HT at 800 MHz.
>
> dts?

same.

>
>
>>  config USBDEBUG_DIRECT
>>       depends SOUTHBRIDGE_NVIDIA_MCP55
>
> Chip specific and board specific so a chip dts setting that is
> filtered through the board dts and can make a Kconfig option visible
> that the builder can use to disabled USB debug output?

Here's the big issue. There are things that can be set in Kconfig AND
in dts; there are things that are settings that should not be in
Kconfig OR dts, because setting them could cause Bad Things To Happen.

For that latter type of variable, I just created mainboard.h. For the
Kconfig/dts issue, it's a judgement call. Possibly the best thing to
do is have the dts able to use Kconfig variables in some settings:
baud = "CONFIG_TTYS0_BAUD";

>
>
>>  config APIC_ID_OFFSET
>> +       This is entirely mainboard dependent.
>
> dts?

no, I don't ever want a person building a bios to think this is a
variable they should touch.

But it really gets down to the role of the dts. I think of it as
something people can change. Things that can never change don't belong
in dts or Kconfig I think.

ron



From peter at stuge.se  Wed Oct  1 23:29:33 2008
From: peter at stuge.se (Peter Stuge)
Date: Wed, 1 Oct 2008 23:29:33 +0200
Subject: [coreboot] Master degree student wanting to give some help.
In-Reply-To: <b1335fe90810010635jc25fe7euda301ca46581e325@mail.gmail.com>
References: <5450d0b40809300420x46eca371s6705799e1e87cd4@mail.gmail.com>
	<20080930144953.26824.qmail@stuge.se>
	<b1335fe90810010635jc25fe7euda301ca46581e325@mail.gmail.com>
Message-ID: <20081001212933.10147.qmail@stuge.se>

Hi Tiago,

Tiago Marques wrote:
> > >    Openmoko coreboot port or
> >
> > Probably not so useful. Is there a PCI bus in the Openmoko?
> 
> Why is this important?

coreboot really does just two things; RAM init and bus init.

The buses coreboot knows so far are V-Link, HT and PCI(e).
(Did I miss some?)


> Supposedly, the next iteration of Intel's Atom platform won't
> feature a PCI bus, coreboot won't work with it?

coreboot already does not work with much of Intel's hardware, I don't
think a new Atom will have much effect on that.

That aside, of course coreboot could be made to support Atom. If
there's no PCI then maybe something else needs initialization,
complex or simple.

The point is that RAM and bus init is often pretty tricky, and on
smaller systems with simpler buses there isn't as much for coreboot
to do.

But of course, coreboot should run everywhere! :p


//Peter



From uwe at hermann-uwe.de  Wed Oct  1 23:33:48 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 1 Oct 2008 23:33:48 +0200
Subject: [coreboot] [PATCH] buildrom: Add support for the ASUS A8N-E
Message-ID: <20081001213347.GG22678@greenwood>

See patch.

Doesn't seem to build with LZMA enabled, only if you disable it. The
same seems to happen to all boards which don't have a Config-lab.lb
which should probably be fixed. IIRC LZMA should work regardless of
whether you have LAB as payload or not(?)


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From jordan.crouse at amd.com  Wed Oct  1 23:48:24 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 1 Oct 2008 15:48:24 -0600
Subject: [coreboot] splash screen
In-Reply-To: <13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
References: <13426df10809230447r7395364ay36ee8dacf1fba0f8@mail.gmail.com>
	<20080923140452.GB26027@cosmic.amd.com>
	<20080923172805.12279.qmail@stuge.se>
	<20080923173708.GB30198@cosmic.amd.com>
	<20080923174449.17274.qmail@stuge.se>
	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>
	<20081001184713.GD22980@cosmic.amd.com>
	<13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
Message-ID: <20081001214824.GA25831@cosmic.amd.com>

On 01/10/08 11:49 -0700, ron minnich wrote:
> On Wed, Oct 1, 2008 at 11:47 AM, Jordan Crouse <jordan.crouse at amd.com> wrote:
> > On 01/10/08 11:03 -0700, ron minnich wrote:
> >> OK I should read my mail more ... mode 3 it is.
> >
> > No - not mode 3.  You'll want to kick into a VESA mode of suitable
> > size so you can draw directly to the framebuffer.
> >
> I'm trying x117 now?

Okay, since Ron is clearly serious about this, we have some matters to
attend to.  The most important is how we are going to format the image
in the payload.  I think we need to use a format that is
already familiar to the bootloader community - two that come to mind are
the lss16 format from Syslinux [1] and the xpm.gz format from Grub.

The first has the advantage of being simpler to implement and draw (we
can draw it from a stream), but we are limited to 16 colors.   The second
is in xpm format, which is well known and can also be drawn from a
stream, but the .gz throws us for a loop, since we don't have a 
zlib implementation in libpayload.

I personally vote for the lSS16 (RLE) format.  It will be familiar to
the syslinux crowd, and it will be darn easy to implement, and copying
to the screen will be as easy as:

video_console_putrle(0, 0, ptrtorle);

But as always, I'm open for suggestions to the contrary.  What do 
you think?

Jordan

[1] http://www.google.com/search?&q=ppmtolss16&sourceid=firefox


> ron
> 

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From jordan.crouse at amd.com  Wed Oct  1 23:58:59 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 1 Oct 2008 15:58:59 -0600
Subject: [coreboot] buildrom: Add support for the ASUS A8N-E
In-Reply-To: <20081001213347.GG22678@greenwood>
References: <20081001213347.GG22678@greenwood>
Message-ID: <20081001215859.GB25831@cosmic.amd.com>

On 01/10/08 23:33 +0200, Uwe Hermann wrote:
> See patch.
> 
> Doesn't seem to build with LZMA enabled, only if you disable it. The
> same seems to happen to all boards which don't have a Config-lab.lb
> which should probably be fixed. IIRC LZMA should work regardless of
> whether you have LAB as payload or not(?)

LZMA in v2 needs options set in the Config.lb that happen to
be set in Config-lab.lb, so we sort of made the arbitrary decision to
just use that .lb if LZMA is enabled.  I dislike this solution immensely,
but I can't think of a good way to work around it unless we generate the
Config.lb at runtime, which has its own bug-a-bears.  Yet another
situation where v3 will save us all... :(

If you want to rename Config-lab.lb to something more descriptive, then
be my guest. You have my ack for that.

Jordan

> Add buildrom support for the ASUS A8N-E.
> 
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

Acked-by: Jordan Crouse <jordan.crouse at amd.com>




From rminnich at gmail.com  Thu Oct  2 00:05:26 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 15:05:26 -0700
Subject: [coreboot] splash screen
In-Reply-To: <20081001214824.GA25831@cosmic.amd.com>
References: <13426df10809230447r7395364ay36ee8dacf1fba0f8@mail.gmail.com>
	<20080923140452.GB26027@cosmic.amd.com>
	<20080923172805.12279.qmail@stuge.se>
	<20080923173708.GB30198@cosmic.amd.com>
	<20080923174449.17274.qmail@stuge.se>
	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>
	<20081001184713.GD22980@cosmic.amd.com>
	<13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
	<20081001214824.GA25831@cosmic.amd.com>
Message-ID: <13426df10810011505i7d5cddfewde911e857faa13b9@mail.gmail.com>

On Wed, Oct 1, 2008 at 2:48 PM, Jordan Crouse <jordan.crouse at amd.com> wrote:

> But as always, I'm open for suggestions to the contrary.  What do
> you think?
>

I think you're always right. [I'm serious!] Let's do it. We'll use
that standard.

I realize this seems like a silly project. I don't much like
splashscreens myself. But I've found the hard way that Purty Pictures
often win over substance. It's almost as if politics were a beauty
contest or something. I think the splash screen is going to have
impact -- I think very positive impact.

ron



From svn at coreboot.org  Thu Oct  2 00:15:20 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Oct 2008 00:15:20 +0200
Subject: [coreboot] r3627 - trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se
Message-ID: <mailman.2152.1355071390.16123.coreboot@coreboot.org>

Author: mjones
Date: 2008-10-02 00:15:20 +0200 (Thu, 02 Oct 2008)
New Revision: 3627

Modified:
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb
Log:
Missed a CONFIG_USE_PRINTK_IN_CAR define for the Asus m2v-mx_se.
This fixes that build error. (trivial)

Signed-off-by: Marc Jones <marc.jones at amd.com>
Acked-by: Marc Jones <marc.jones at amd.com>



Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb	2008-10-01 20:16:58 UTC (rev 3626)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb	2008-10-01 22:15:20 UTC (rev 3627)
@@ -91,6 +91,7 @@
 uses SB_HT_CHAIN_ON_BUS0
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_USE_PRINTK_IN_CAR
 
 default ROM_SIZE = 512 * 1024
 default FALLBACK_SIZE = 256 * 1024
@@ -158,6 +159,7 @@
 default CC = "$(CROSS_COMPILE)gcc -m32"
 default HOSTCC = "gcc"
 default CONFIG_GDB_STUB = 0
+default CONFIG_USE_PRINTK_IN_CAR=1
 default CONFIG_CONSOLE_SERIAL8250 = 1
 default TTYS0_BAUD = 115200
 default TTYS0_BASE = 0x3f8




From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  2 00:21:13 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 02 Oct 2008 00:21:13 +0200
Subject: [coreboot] Is Coreboot selfmodifying? Award legacy Bios is!
In-Reply-To: <13426df10810011040tfc0d0d3mce580442f52a8794@mail.gmail.com>
References: <E1Kl4BW-0000eP-QL@aun.bellman.mea>
	<13426df10810011040tfc0d0d3mce580442f52a8794@mail.gmail.com>
Message-ID: <48E3F7D9.8030605@gmx.net>

On 01.10.2008 19:40, ron minnich wrote:
> we don't rewrite flash. Yes, this is hazardous I think as well.
>   

We may do that soon, but I promise it will be done in the most careful
way possible. That means regardless of when the write to a flash chip
fails, you can still boot and still have your configuration data.
Why? NVRAM is not really unlimited storage. Expect a proposal and
skeleton code in the next few days.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  2 00:23:48 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 02 Oct 2008 00:23:48 +0200
Subject: [coreboot] [PATCH v2] AMD DBM690T IRQ cleanup
In-Reply-To: <48E3B90A.2030304@amd.com>
References: <48E379E5.4080706@gmx.net> <48E3B90A.2030304@amd.com>
Message-ID: <48E3F874.2090600@gmx.net>

On 01.10.2008 19:53, Marc Jones wrote:
> Carl-Daniel Hailfinger wrote:
>> Hi,
>>
>> I decided to prepare a patch for the stuff I mentioned in the DBM690T
>> review.
>>
>> Use easily readable macros to setup interrupt routing.
>> Change a few PCI bus/dev/fn to use hexadecimal numbers.
>>
>> Signed-off-by: Carl-Daniel Hailfinger
>> <c-d.hailfinger.devel.2006 at gmx.net>
>
> The cleanup is nice but you didn't translate correctly. See below.

Thanks for checking! It seems I mistyped the regular expression for
search and replace.


>> Index: LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c
>> ===================================================================
>> --- LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c   
>> (Revision 3624)
>> +++ LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c   
>> (Arbeitskopie)
>> @@ -122,94 +122,72 @@
>>      smp_write_intsrc(mc, mp_ExtINT,
>>               MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa,
>>               0x0, apicid_sb600, 0x0);
>> -    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |
>> MP_IRQ_POLARITY_HIGH,
>> -             bus_isa, 0x1, apicid_sb600, 0x1);
>> -    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |
>> MP_IRQ_POLARITY_HIGH,
>> -             bus_isa, 0x0, apicid_sb600, 0x2);
>> -    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |
>> MP_IRQ_POLARITY_HIGH,
>> -             bus_isa, 0x3, apicid_sb600, 0x3);
>> -    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |
>> MP_IRQ_POLARITY_HIGH,
>> -             bus_isa, 0x4, apicid_sb600, 0x4);
>> -    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |
>> MP_IRQ_POLARITY_HIGH,
>> -             bus_isa, 0x6, apicid_sb600, 0x6);
>> -    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |
>> MP_IRQ_POLARITY_HIGH,
>> -             bus_isa, 0x7, apicid_sb600, 0x7);
>> -    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |
>> MP_IRQ_POLARITY_HIGH,
>> -             bus_isa, 0xc, apicid_sb600, 0xc);
>> -    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |
>> MP_IRQ_POLARITY_HIGH,
>> -             bus_isa, 0xd, apicid_sb600, 0xd);
>> -    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |
>> MP_IRQ_POLARITY_HIGH,
>> -             bus_isa, 0xe, apicid_sb600, 0xe);
>>  
>> +    /* ISA ints are edge-triggered, and usually originate from the
>> ISA bus,
>> +     * or its remainings.
>> +     */
>> +#define ISA_INT(intr, pin) \
>> +    smp_write_intsrc(mc, mp_INT,
>> MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, (intr),
>> apicid_sb600, (pin))
>> +
>> +    ISA_INT(0x1, 0x1);
>> +    ISA_INT(0x0, 0x2);
>> +    ISA_INT(0x3, 0x3);
>> +    ISA_INT(0x4, 0x4);
>> +    ISA_INT(0x6, 0x6);
>> +    ISA_INT(0x7, 0x7);
>> +    ISA_INT(0xc, 0xc);
>> +    ISA_INT(0xd, 0xd);
>> +    ISA_INT(0xe, 0xe);
>> +
>> +    /* PCI interrupts are level triggered, and are
>> +     * associated with a specific bus/device/function tuple.
>> +     */
>> +#define PCI_INT(bus, dev, fn, pin) \
>> +        smp_write_intsrc(mc, mp_INT,
>> MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)),
>> apicid_sb600, (pin))
>> +
>>      /* usb */
>> -    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL |
>> MP_IRQ_POLARITY_LOW,
>> -             0, 19 << 2 | 0, apicid_sb600, 0x10);
>> -    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL |
>> MP_IRQ_POLARITY_LOW,
>> -             0, 19 << 2 | 1, apicid_sb600, 0x11);
>> -    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL |
>> MP_IRQ_POLARITY_LOW,
>> -             0, 19 << 2 | 2, apicid_sb600, 0x12);
>> -    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL |
>> MP_IRQ_POLARITY_LOW,
>> -             0, 19 << 2 | 3, apicid_sb600, 0x13);
>> +    PCI_INT(0, 0x13, 2, 0);
>> +    PCI_INT(0, 0x13, 2, 1);
>> +    PCI_INT(0, 0x13, 2, 2);
>> +    PCI_INT(0, 0x13, 2, 3);
>
> This should be:
>     PCI_INT(0, 0x13, 0, 0x10);
>     PCI_INT(0, 0x13, 1, 0x11);
>     PCI_INT(0, 0x13, 2, 0x12);
>     PCI_INT(0, 0x13, 3, 0x13);
>
> I think you put the << 2 in the fn throughout the patch.

The regexp grabbed the wrong parts of the code. I'll fix and resend.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  2 00:40:29 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 02 Oct 2008 00:40:29 +0200
Subject: [coreboot] Some v3 Kconfig options into dts?
In-Reply-To: <13426df10810011418m483427b4k55835bf4f41de6c0@mail.gmail.com>
References: <20081001194424.18100.qmail@stuge.se>
	<13426df10810011418m483427b4k55835bf4f41de6c0@mail.gmail.com>
Message-ID: <48E3FC5D.1000403@gmx.net>

On 01.10.2008 23:18, ron minnich wrote:
> On Wed, Oct 1, 2008 at 12:44 PM, Peter Stuge <peter at stuge.se> wrote:
>   

Forgive me for joining this discussion, but this is an area where I have
tried to make the design more consistent. That doesn't mean that svn
HEAD is perfect, but I have some patches on disk which I'll send real
soon now.

My idea was that dts are pure hardware description and Kconfig should be
pure feature and board selection.


>> svn at coreboot.org wrote:
>>     
>>>  config K8_SCAN_PCI_BUS
>>> +       Whether to scan the PCI bus in stage1.
>>>
>>>       
>
> I adopted this from v2 but it would only be a mainboard issue; it
> should never be in dts since it's not an option anyone should ever
> set.
>   

I'm not sure I understand this completely. Do you suggest to keep
mainboard settings nobody should ever touch out of the dts?


>>>  config K8_ALLOCATE_IO_RANGE
>>> +       Whether to allocate I/O space in stage1.
>>>
>>>  config K8_ALLOCATE_MMIO_RANGE
>>> +       Whether to allocate MMIO space in stage1.
>>>       
>
> same.
>   

Are there any boards which need the option?


>>>  config LOGICAL_CPUS
>>> +       How many logical CPUs there are. FIXME.
>>>
>>>       
>
> should always be determined dynamically by what cpus are installed.
>   

Agreed.


>>>  config MAX_PHYSICAL_CPUS
>>> +       Maximum number of physical CPUs (sockets).
>>>       
>> dts?
>>
>>     
>
> This comes down to wires. I don't see it in the dts.
>   

So it's a hardware description. In theory, we could derive the number of
sockets from the dts if we ever place complete HT tree info there.


>>>  config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
>>> +       Config with 4 CPUs even if more are installed.
>>>       
>> But I think this should stay in Kconfig.
>>
>>     
>
> yes. It's a bizarre variable which I hope to remove some day.
>   

Should it really be user-selectable? If so, would NVRAM be a better place?


>>>  config CROSS_BAR_47_56
>>> +       Configure for the type of crossbar on the mainboard.
>>>       
>> dts?
>>     
>
> no. It's wires.
>   

Hardware description -> dts.


>>>  config SMP
>>>       
>>>       depends CPU_I586 || CPU_AMD_K8
>>>       default 0
>>>       help
>>> +       This option is used to enable certain functions to make coreboot
>>> +       work correctly on symmetric multi processor systems.
>>>         It is usually set in mainboard/*/Kconfig.
>>>       
>> Could this be derived from the number of logical CPUs?
>>     
>
> Yes. this is not an OS, it's a BIOS, and SMP should always be enabled.
>   

OK.


>>>  config IOAPIC
>>> @@ -153,7 +152,7 @@
>>>       depends ARCH_X86 && CPU_AMD_K8
>>>       default 0
>>>       help
>>> +       If you want to configure an IOAPIC, set this.
>>>       
>> Will the builder really have an opinion on this? Isn't it chip
>> dependent? (ie -> dts?)
>>     
>
> it's something they should never want to see or change. Not even dts.
>   

If it is mainboard-hardware-specific and should not be changed, we
should place it in the dts.


>>>  config K8_HT_FREQ_1G_SUPPORT
>>> +       1 GHz support. Opteron E0 or later can support 1G HT,
>>> +       but still depends on the mainboard.
>>>       
>> dts?
>>     
>
> no, it's a mainboard issue.
>   

dito.


>>>  config HT_FREQ_800MHZ
>>> +       Can we run HT at 800 MHz.
>>>       
>> dts?
>>     
>
> same.
>   

dito.


>>>  config USBDEBUG_DIRECT
>>>       depends SOUTHBRIDGE_NVIDIA_MCP55
>>>       
>> Chip specific and board specific so a chip dts setting that is
>> filtered through the board dts and can make a Kconfig option visible
>> that the builder can use to disabled USB debug output?
>>     
>
> Here's the big issue. There are things that can be set in Kconfig AND
> in dts; there are things that are settings that should not be in
> Kconfig OR dts, because setting them could cause Bad Things To Happen.
>   

I'd like to treat the dts as "don't touch" for normal users anyway. It's
hardware description and users are extremely unlikely to change the
board wiring.


> For that latter type of variable, I just created mainboard.h. For the
> Kconfig/dts issue, it's a judgement call. Possibly the best thing to
> do is have the dts able to use Kconfig variables in some settings:
> baud = "CONFIG_TTYS0_BAUD";
>   

Hm. That's an interesting idea. Maybe we could couple it with my "dts
from stage1" idea.


>>>  config APIC_ID_OFFSET
>>> +       This is entirely mainboard dependent.
>>>       
>> dts?
>>     
>
> no, I don't ever want a person building a bios to think this is a
> variable they should touch.
>
> But it really gets down to the role of the dts. I think of it as
> something people can change. Things that can never change don't belong
> in dts or Kconfig I think.
>   

That's where our understanding about the role of the dts differs. IMO
there should not be any reason why anybody would touch the dts (except
maybe for configurations like a FPGA in an Opteron socket).


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Thu Oct  2 00:48:24 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 15:48:24 -0700
Subject: [coreboot] Some v3 Kconfig options into dts?
In-Reply-To: <48E3FC5D.1000403@gmx.net>
References: <20081001194424.18100.qmail@stuge.se>
	<13426df10810011418m483427b4k55835bf4f41de6c0@mail.gmail.com>
	<48E3FC5D.1000403@gmx.net>
Message-ID: <13426df10810011548wa4a2b90i3dd61b1eb2de3dc3@mail.gmail.com>

On Wed, Oct 1, 2008 at 3:40 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

> My idea was that dts are pure hardware description and Kconfig should be
> pure feature and board selection.

That's a good point and I think Peter was making it as well.


>
>
>>> svn at coreboot.org wrote:
>>>
>>>>  config K8_SCAN_PCI_BUS
>>>> +       Whether to scan the PCI bus in stage1.
>>>>
>>>>
>>
>> I adopted this from v2 but it would only be a mainboard issue; it
>> should never be in dts since it's not an option anyone should ever
>> set.
>>
>
> I'm not sure I understand this completely. Do you suggest to keep
> mainboard settings nobody should ever touch out of the dts?

on re-reading this I am no longer so sure.

BUT: remember that some of this stuff is stage1 and dts is not there
in stage1. This is arguably a design problem. But after two years I am
tired of designing and want to get this thing running :-)
>
>
>>>>  config K8_ALLOCATE_IO_RANGE
>>>> +       Whether to allocate I/O space in stage1.
>>>>
>>>>  config K8_ALLOCATE_MMIO_RANGE
>>>> +       Whether to allocate MMIO space in stage1.
>>>>
>>
>> same.
>>
>
> Are there any boards which need the option?

There probably are else it would not be in there :-)


>
>>>>  config MAX_PHYSICAL_CPUS
>>>> +       Maximum number of physical CPUs (sockets).
>>>>
>>> dts?
>>>
>>>
>>
>> This comes down to wires. I don't see it in the dts.
>>
>
> So it's a hardware description. In theory, we could derive the number of
> sockets from the dts if we ever place complete HT tree info there.

yeah, good point. But the HT tree is even deeper in startup. You
can't, for example, expand FLASH decoding to large size until you've
wired up hypertransport, There is always going to be a chicken-and-egg
issue with these early bits.

>
>
>>>>  config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
>>>> +       Config with 4 CPUs even if more are installed.
>>>>
>>> But I think this should stay in Kconfig.
>>>
>>>
>>
>> yes. It's a bizarre variable which I hope to remove some day.
>>
>
> Should it really be user-selectable? If so, would NVRAM be a better place?

I am not sure.

>
>
>>>>  config CROSS_BAR_47_56
>>>> +       Configure for the type of crossbar on the mainboard.
>>>>
>>> dts?
>>>
>>
>> no. It's wires.
>>
>
> Hardware description -> dts.

You win. (You too peter!)

>
>>>>  config IOAPIC
>>>> @@ -153,7 +152,7 @@
>>>>       depends ARCH_X86 && CPU_AMD_K8
>>>>       default 0
>>>>       help
>>>> +       If you want to configure an IOAPIC, set this.
>>>>
>>> Will the builder really have an opinion on this? Isn't it chip
>>> dependent? (ie -> dts?)
>>>
>>
>> it's something they should never want to see or change. Not even dts.
>>
>
> If it is mainboard-hardware-specific and should not be changed, we
> should place it in the dts.

you win again! I am losing bonus points!

>
>
>>>>  config K8_HT_FREQ_1G_SUPPORT
>>>> +       1 GHz support. Opteron E0 or later can support 1G HT,
>>>> +       but still depends on the mainboard.
>>>>
>>> dts?
>>>
>>
>> no, it's a mainboard issue.
>>
>
> dito.

yeah. Except we need to see if this comes up in stage 1.

>
> I'd like to treat the dts as "don't touch" for normal users anyway. It's
> hardware description and users are extremely unlikely to change the
> board wiring.

which is fine but there are going to be some variables set in kconfig
which might need to change variables in dts.

>
>
>> For that latter type of variable, I just created mainboard.h. For the
>> Kconfig/dts issue, it's a judgement call. Possibly the best thing to
>> do is have the dts able to use Kconfig variables in some settings:
>> baud = "CONFIG_TTYS0_BAUD";
>>
>
> Hm. That's an interesting idea. Maybe we could couple it with my "dts
> from stage1" idea.

mainboard.h is a stopgap, I bet, until we get your idea.


>
> That's where our understanding about the role of the dts differs. IMO
> there should not be any reason why anybody would touch the dts (except
> maybe for configurations like a FPGA in an Opteron socket).

umm :-)

So we don't touch it unless we need to touch it? That worries me.

ron



From info at coresystems.de  Thu Oct  2 00:50:35 2008
From: info at coresystems.de (coreboot information)
Date: Thu, 02 Oct 2008 00:50:35 +0200
Subject: [coreboot] r3627 build service
Message-ID: <E1KlAWh-0007FS-Jl@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "mjones" checked in revision 3627 to
the coreboot source repository and caused the following 
changes:

Change Log:
Missed a CONFIG_USE_PRINTK_IN_CAR define for the Asus m2v-mx_se.
This fixes that build error. (trivial)

Signed-off-by: Marc Jones <marc.jones at amd.com>
Acked-by: Marc Jones <marc.jones at amd.com>



Build Log:
Compilation of asus:m2v-mx_se has been fixed
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3627&device=j7f24&vendor=jetway
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3627&device=epia-cn&vendor=via


If something broke during this checkin please be a pain 
in mjones's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  2 01:09:37 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 02 Oct 2008 01:09:37 +0200
Subject: [coreboot] Some v3 Kconfig options into dts?
In-Reply-To: <13426df10810011548wa4a2b90i3dd61b1eb2de3dc3@mail.gmail.com>
References: <20081001194424.18100.qmail@stuge.se>	
	<13426df10810011418m483427b4k55835bf4f41de6c0@mail.gmail.com>	
	<48E3FC5D.1000403@gmx.net>
	<13426df10810011548wa4a2b90i3dd61b1eb2de3dc3@mail.gmail.com>
Message-ID: <48E40331.40809@gmx.net>

On 02.10.2008 00:48, ron minnich wrote:
> On Wed, Oct 1, 2008 at 3:40 PM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>
>   
>> My idea was that dts are pure hardware description and Kconfig should be
>> pure feature and board selection.
>>     
>
> That's a good point and I think Peter was making it as well.
>   

Well, your point is good as well.


>>>> svn at coreboot.org wrote:
>>>>
>>>>         
>>>>>  config K8_SCAN_PCI_BUS
>>>>> +       Whether to scan the PCI bus in stage1.
>>>>>
>>>>>
>>>>>           
>>> I adopted this from v2 but it would only be a mainboard issue; it
>>> should never be in dts since it's not an option anyone should ever
>>> set.
>>>
>>>       
>> I'm not sure I understand this completely. Do you suggest to keep
>> mainboard settings nobody should ever touch out of the dts?
>>     
>
> on re-reading this I am no longer so sure.
>
> BUT: remember that some of this stuff is stage1 and dts is not there
> in stage1. This is arguably a design problem. But after two years I am
> tired of designing and want to get this thing running :-)
>   

Absolutely. How about you get/keep it working and from time to time I
send patches to make the design a bit cleaner?

I really really want you to go ahead without considering these design
things. v3 already has a really good design and making the design
perfect shouldn't be in the way of getting hardware running.
Once we have a few boards in v3 which are also available on the market
for reasonable prices, we can attract more developers.


>>>>>  config K8_ALLOCATE_IO_RANGE
>>>>> +       Whether to allocate I/O space in stage1.
>>>>>
>>>>>  config K8_ALLOCATE_MMIO_RANGE
>>>>> +       Whether to allocate MMIO space in stage1.
>>>>>
>>>>>           
>>> same.
>>>
>>>       
>> Are there any boards which need the option?
>>     
>
> There probably are else it would not be in there :-)
>   

I believe I saw quite a few always-unused chunks of code in v2, so I
asked. But you're right ;-)


>>>>>  config MAX_PHYSICAL_CPUS
>>>>> +       Maximum number of physical CPUs (sockets).
>>>>>
>>>>>           
>>>> dts?
>>>>
>>>>
>>>>         
>>> This comes down to wires. I don't see it in the dts.
>>>
>>>       
>> So it's a hardware description. In theory, we could derive the number of
>> sockets from the dts if we ever place complete HT tree info there.
>>     
>
> yeah, good point. But the HT tree is even deeper in startup. You
> can't, for example, expand FLASH decoding to large size until you've
> wired up hypertransport, There is always going to be a chicken-and-egg
> issue with these early bits.
>   

I see. I'll try to make my stage1-dts design capable of handling this.


>>>>>  config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
>>>>> +       Config with 4 CPUs even if more are installed.
>>>>>
>>>>>           
>>>> But I think this should stay in Kconfig.
>>>>         
>>> yes. It's a bizarre variable which I hope to remove some day.
>>>       
>> Should it really be user-selectable? If so, would NVRAM be a better place?
>>     
>
> I am not sure.
>   

We'll probably have this variable killed a year from now, so I wouldn't
invest too much brainpower in it.


>>>>>  config CROSS_BAR_47_56
>>>>> +       Configure for the type of crossbar on the mainboard.
>>>>>
>>>>>           
>>>> dts?
>>>>
>>>>         
>>> no. It's wires.
>>>
>>>       
>> Hardware description -> dts.
>>     
>
> You win. (You too peter!)
>
>   
>>>>>  config IOAPIC
>>>>> @@ -153,7 +152,7 @@
>>>>>       depends ARCH_X86 && CPU_AMD_K8
>>>>>       default 0
>>>>>       help
>>>>> +       If you want to configure an IOAPIC, set this.
>>>>>
>>>>>           
>>>> Will the builder really have an opinion on this? Isn't it chip
>>>> dependent? (ie -> dts?)
>>>>
>>>>         
>>> it's something they should never want to see or change. Not even dts.
>>>
>>>       
>> If it is mainboard-hardware-specific and should not be changed, we
>> should place it in the dts.
>>     
>
> you win again! I am losing bonus points!
>   

Your score is still at +infinity. I doubt that's going to make a dent in
it. ;-)


>>>>>  config K8_HT_FREQ_1G_SUPPORT
>>>>> +       1 GHz support. Opteron E0 or later can support 1G HT,
>>>>> +       but still depends on the mainboard.
>>>>>
>>>>>           
>>>> dts?
>>>>
>>>>         
>>> no, it's a mainboard issue.
>>>
>>>       
>> dito.
>>     
>
> yeah. Except we need to see if this comes up in stage 1.
>   

OK, stays in Kconfig until stage1-dts is done.


>> I'd like to treat the dts as "don't touch" for normal users anyway. It's
>> hardware description and users are extremely unlikely to change the
>> board wiring.
>>     
>
> which is fine but there are going to be some variables set in kconfig
> which might need to change variables in dts.
>   

That's tricky but doable.


>>> For that latter type of variable, I just created mainboard.h. For the
>>> Kconfig/dts issue, it's a judgement call. Possibly the best thing to
>>> do is have the dts able to use Kconfig variables in some settings:
>>> baud = "CONFIG_TTYS0_BAUD";
>>>
>>>       
>> Hm. That's an interesting idea. Maybe we could couple it with my "dts
>> from stage1" idea.
>>     
>
> mainboard.h is a stopgap, I bet, until we get your idea.
>   

Go ahead with the stopgap.


>> That's where our understanding about the role of the dts differs. IMO
>> there should not be any reason why anybody would touch the dts (except
>> maybe for configurations like a FPGA in an Opteron socket).
>>     
>
> umm :-)
>
> So we don't touch it unless we need to touch it? That worries me.
>   

Like we specify CPU type right now, I'd like to argue that replacing a
CPU with a FPGA is changing the hardware, so a dts modification would be
appropriate. But I see your concerns and I'll try to address them in a
later proposal.

I have 296 coreboot mails to reply to, so this will probably take a few
days.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Thu Oct  2 01:12:13 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 16:12:13 -0700
Subject: [coreboot] Some v3 Kconfig options into dts?
In-Reply-To: <48E40331.40809@gmx.net>
References: <20081001194424.18100.qmail@stuge.se>
	<13426df10810011418m483427b4k55835bf4f41de6c0@mail.gmail.com>
	<48E3FC5D.1000403@gmx.net>
	<13426df10810011548wa4a2b90i3dd61b1eb2de3dc3@mail.gmail.com>
	<48E40331.40809@gmx.net>
Message-ID: <13426df10810011612k1bf3bbc1o8a7abbd7fe44b02@mail.gmail.com>

On Wed, Oct 1, 2008 at 4:09 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

> I have 296 coreboot mails to reply to, so this will probably take a few
> days.
>

296!?!? Yikes!

thanks, I needed that chuckle :-)

ron



From peter at stuge.se  Thu Oct  2 01:16:19 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Oct 2008 01:16:19 +0200
Subject: [coreboot] splash screen
In-Reply-To: <13426df10810011505i7d5cddfewde911e857faa13b9@mail.gmail.com>
References: <20080923140452.GB26027@cosmic.amd.com>
	<20080923172805.12279.qmail@stuge.se>
	<20080923173708.GB30198@cosmic.amd.com>
	<20080923174449.17274.qmail@stuge.se>
	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>
	<20081001184713.GD22980@cosmic.amd.com>
	<13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
	<20081001214824.GA25831@cosmic.amd.com>
	<13426df10810011505i7d5cddfewde911e857faa13b9@mail.gmail.com>
Message-ID: <20081001231619.31486.qmail@stuge.se>

ron minnich wrote:
> almost as if politics were a beauty contest

I think it's about pleasing people. Beautiful things go a long way.


//Peter



From rminnich at gmail.com  Thu Oct  2 01:19:40 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 16:19:40 -0700
Subject: [coreboot] splash screen
In-Reply-To: <20081001231619.31486.qmail@stuge.se>
References: <20080923140452.GB26027@cosmic.amd.com>
	<20080923173708.GB30198@cosmic.amd.com>
	<20080923174449.17274.qmail@stuge.se>
	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>
	<20081001184713.GD22980@cosmic.amd.com>
	<13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
	<20081001214824.GA25831@cosmic.amd.com>
	<13426df10810011505i7d5cddfewde911e857faa13b9@mail.gmail.com>
	<20081001231619.31486.qmail@stuge.se>
Message-ID: <13426df10810011619n5f421430gc978082c6f561777@mail.gmail.com>

On Wed, Oct 1, 2008 at 4:16 PM, Peter Stuge <peter at stuge.se> wrote:
> ron minnich wrote:
>> almost as if politics were a beauty contest
>
> I think it's about pleasing people. Beautiful things go a long way.
>

Yeah, I was making an indirect joke about our election :-)

ron



From rminnich at gmail.com  Thu Oct  2 01:20:32 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Oct 2008 16:20:32 -0700
Subject: [coreboot] splash screen
In-Reply-To: <13426df10810011619n5f421430gc978082c6f561777@mail.gmail.com>
References: <20080923140452.GB26027@cosmic.amd.com>
	<20080923174449.17274.qmail@stuge.se>
	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>
	<20081001184713.GD22980@cosmic.amd.com>
	<13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
	<20081001214824.GA25831@cosmic.amd.com>
	<13426df10810011505i7d5cddfewde911e857faa13b9@mail.gmail.com>
	<20081001231619.31486.qmail@stuge.se>
	<13426df10810011619n5f421430gc978082c6f561777@mail.gmail.com>
Message-ID: <13426df10810011620q4c105d95y237e42fa04f3d757@mail.gmail.com>

On Wed, Oct 1, 2008 at 4:19 PM, ron minnich <rminnich at gmail.com> wrote:
> On Wed, Oct 1, 2008 at 4:16 PM, Peter Stuge <peter at stuge.se> wrote:
>> ron minnich wrote:
>>> almost as if politics were a beauty contest
>>
>> I think it's about pleasing people. Beautiful things go a long way.
>>
>
> Yeah, I was making an indirect joke about our election :-)
>
and let's leave it at that, we've never had a political discussion on
this list and I apologize for even hinting at one :-)

ron



From stepan at coresystems.de  Thu Oct  2 01:23:51 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 02 Oct 2008 01:23:51 +0200
Subject: [coreboot] splash screen
In-Reply-To: <20081001214824.GA25831@cosmic.amd.com>
References: <13426df10809230447r7395364ay36ee8dacf1fba0f8@mail.gmail.com>	<20080923140452.GB26027@cosmic.amd.com>	<20080923172805.12279.qmail@stuge.se>	<20080923173708.GB30198@cosmic.amd.com>	<20080923174449.17274.qmail@stuge.se>	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>	<20081001184713.GD22980@cosmic.amd.com>	<13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
	<20081001214824.GA25831@cosmic.amd.com>
Message-ID: <48E40687.9090501@coresystems.de>

Jordan Crouse wrote:
> On 01/10/08 11:49 -0700, ron minnich wrote:
>   
>> On Wed, Oct 1, 2008 at 11:47 AM, Jordan Crouse <jordan.crouse at amd.com> wrote:
>>     
>>> On 01/10/08 11:03 -0700, ron minnich wrote:
>>>       
>>>> OK I should read my mail more ... mode 3 it is.
>>>>         
>>> No - not mode 3.  You'll want to kick into a VESA mode of suitable
>>> size so you can draw directly to the framebuffer.
>>>
>>>       
>> I'm trying x117 now?
>>     
>
> Okay, since Ron is clearly serious about this, we have some matters to
> attend to.  The most important is how we are going to format the image
> in the payload.  I think we need to use a format that is
> already familiar to the bootloader community - two that come to mind are
> the lss16 format from Syslinux [1] and the xpm.gz format from Grub.
>   
For the bootsplash (www.bootsplash.org) we used an integer only jpeg
decompressor that fit into round about 8kb of code.
Together with the compression rate of the jpeg picture itself, this is
hard to beat in terms of size ..

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From jordan.crouse at amd.com  Thu Oct  2 01:42:32 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 1 Oct 2008 17:42:32 -0600
Subject: [coreboot] splash screen
In-Reply-To: <48E40687.9090501@coresystems.de>
References: <20080923140452.GB26027@cosmic.amd.com>
	<20080923172805.12279.qmail@stuge.se>
	<20080923173708.GB30198@cosmic.amd.com>
	<20080923174449.17274.qmail@stuge.se>
	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>
	<20081001184713.GD22980@cosmic.amd.com>
	<13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
	<20081001214824.GA25831@cosmic.amd.com>
	<48E40687.9090501@coresystems.de>
Message-ID: <20081001234232.GC25831@cosmic.amd.com>

On 02/10/08 01:23 +0200, Stefan Reinauer wrote:
> Jordan Crouse wrote:
> > On 01/10/08 11:49 -0700, ron minnich wrote:
> >   
> >> On Wed, Oct 1, 2008 at 11:47 AM, Jordan Crouse <jordan.crouse at amd.com> wrote:
> >>     
> >>> On 01/10/08 11:03 -0700, ron minnich wrote:
> >>>       
> >>>> OK I should read my mail more ... mode 3 it is.
> >>>>         
> >>> No - not mode 3.  You'll want to kick into a VESA mode of suitable
> >>> size so you can draw directly to the framebuffer.
> >>>
> >>>       
> >> I'm trying x117 now?
> >>     
> >
> > Okay, since Ron is clearly serious about this, we have some matters to
> > attend to.  The most important is how we are going to format the image
> > in the payload.  I think we need to use a format that is
> > already familiar to the bootloader community - two that come to mind are
> > the lss16 format from Syslinux [1] and the xpm.gz format from Grub.
> >   
> For the bootsplash (www.bootsplash.org) we used an integer only jpeg
> decompressor that fit into round about 8kb of code.
> Together with the compression rate of the jpeg picture itself, this is
> hard to beat in terms of size ..

Is said decompressor in a license that we can be happy with?  If so,
then I think we should consider adding it.

As a comparison - Ron's screenshot:

.png - 97466  bytes
.jpg - 46877  bytes
.rle - 24846  bytes

Implementation wise - the LSS16 function I just wrote is about 40 lines
of code with lots of whitespace.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  2 02:21:24 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 02 Oct 2008 02:21:24 +0200
Subject: [coreboot] [PATCH v2] AMD DBM690T IRQ cleanup
In-Reply-To: <48E3F874.2090600@gmx.net>
References: <48E379E5.4080706@gmx.net> <48E3B90A.2030304@amd.com>
	<48E3F874.2090600@gmx.net>
Message-ID: <48E41404.5090307@gmx.net>

On 02.10.2008 00:23, Carl-Daniel Hailfinger wrote:
> On 01.10.2008 19:53, Marc Jones wrote:
>   
>> Carl-Daniel Hailfinger wrote:
>>     
>>> Hi,
>>>
>>> I decided to prepare a patch for the stuff I mentioned in the DBM690T
>>> review.
>>>
>>> Use easily readable macros to setup interrupt routing.
>>> Change a few PCI bus/dev/fn to use hexadecimal numbers.
>>>
>>> Signed-off-by: Carl-Daniel Hailfinger
>>> <c-d.hailfinger.devel.2006 at gmx.net>
>>>       
>> The cleanup is nice but you didn't translate correctly. See below.
>>     
>
> Thanks for checking! It seems I mistyped the regular expression for
> search and replace.
>   

New attempt with more cleanups and hopefully correct conversion:
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c
===================================================================
--- LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c	(Revision 3624)
+++ LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c	(Arbeitskopie)
@@ -45,7 +45,6 @@
 	static const char oem[8] = "ATI     ";
 	static const char productid[12] = "DBM690T     ";
 	struct mp_config_table *mc;
-	int i, j;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	memset(mc, 0, sizeof(*mc));
@@ -119,104 +118,77 @@
 	}
 
 	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	smp_write_intsrc(mc, mp_ExtINT,
-			 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa,
-			 0x0, apicid_sb600, 0x0);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x1, apicid_sb600, 0x1);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x0, apicid_sb600, 0x2);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x3, apicid_sb600, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x4, apicid_sb600, 0x4);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x6, apicid_sb600, 0x6);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x7, apicid_sb600, 0x7);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0xc, apicid_sb600, 0xc);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0xd, apicid_sb600, 0xd);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0xe, apicid_sb600, 0xe);
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+	smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+	
+	IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb600, 0x0);
 
+	/* ISA ints are edge-triggered, and usually originate from the ISA bus,
+	 * or its remainings.
+	 */
+#define ISA_INT(intr, pin) \
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, (intr), apicid_sb600, (pin))
+
+	ISA_INT(0x1, 0x1);
+	ISA_INT(0x0, 0x2);
+	ISA_INT(0x3, 0x3);
+	ISA_INT(0x4, 0x4);
+	ISA_INT(0x6, 0x6);
+	ISA_INT(0x7, 0x7);
+	ISA_INT(0xc, 0xc);
+	ISA_INT(0xd, 0xd);
+	ISA_INT(0xe, 0xe);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
+#define PCI_INT(bus, dev, fn, pin) \
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
+
 	/* usb */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 19 << 2 | 0, apicid_sb600, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 19 << 2 | 1, apicid_sb600, 0x11);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 19 << 2 | 2, apicid_sb600, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 19 << 2 | 3, apicid_sb600, 0x13);
+	PCI_INT(0x0, 0x13, 0x0, 0x10);
+	PCI_INT(0x0, 0x13, 0x1, 0x11);
+	PCI_INT(0x0, 0x13, 0x2, 0x12);
+	PCI_INT(0x0, 0x13, 0x3, 0x13);
 
 	/* sata */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 18 << 2 | 0, apicid_sb600, 22);
+	PCI_INT(0x0, 0x13, 0x0, 0x16);
 
 	/* HD Audio: b0:d20:f1:reg63 should be 0. */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 20 << 2 | 0, apicid_sb600, 16);
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
 
 	/* on board NIC & Slot PCIE.  */
-	i = 2;
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[1], 0x5 << 2 | 0, apicid_sb600, 18);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[1], 0x5 << 2 | 1, apicid_sb600, 19);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[2], 0x0 << 2 | 0, apicid_sb600, 18);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[3], 0x0 << 2 | 0, apicid_sb600, 19);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[4], 0x0 << 2 | 0, apicid_sb600, 16);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[5], 0x0 << 2 | 0, apicid_sb600, 17);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[6], 0x0 << 2 | 0, apicid_sb600, 18);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[7], 0x0 << 2 | 0, apicid_sb600, 19);
+	PCI_INT(bus_rs690[1], 0x5, 0x0, 0x13);
+	PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
+	PCI_INT(bus_rs690[2], 0x0, 0x0, 0x13);
+	PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
+	PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
+	PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
+	PCI_INT(bus_rs690[6], 0x0, 0x0, 0x13);
+	PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
 
 	/* PCI slots */
-	i += 6;
-	j = 5;
 	/* PCI_SLOT 0. */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 5 << 2 | 0, apicid_sb600, 20);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 5 << 2 | 1, apicid_sb600, 21);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 5 << 2 | 2, apicid_sb600, 22);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 5 << 2 | 3, apicid_sb600, 23);
+	PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
 
 	/* PCI_SLOT 1. */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 6 << 2 | 0, apicid_sb600, 21);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 6 << 2 | 1, apicid_sb600, 22);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 6 << 2 | 2, apicid_sb600, 23);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 6 << 2 | 3, apicid_sb600, 20);
+	PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
 
 	/* PCI_SLOT 2. */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 7 << 2 | 0, apicid_sb600, 22);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 7 << 2 | 1, apicid_sb600, 23);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 7 << 2 | 2, apicid_sb600, 20);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 7 << 2 | 3, apicid_sb600, 21);
+	PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
 
 	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	smp_write_intsrc(mc, mp_ExtINT,
-			 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa,
-			 0x0, MP_APIC_ALL, 0x0);
-	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
 	/* There is no extension information... */
 
 	/* Compute the checksums */


-- 
http://www.hailfinger.org/




From peter at stuge.se  Thu Oct  2 02:30:49 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Oct 2008 02:30:49 +0200
Subject: [coreboot] splash screen
In-Reply-To: <20081001234232.GC25831@cosmic.amd.com>
References: <20080923172805.12279.qmail@stuge.se>
	<20080923173708.GB30198@cosmic.amd.com>
	<20080923174449.17274.qmail@stuge.se>
	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>
	<20081001184713.GD22980@cosmic.amd.com>
	<13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
	<20081001214824.GA25831@cosmic.amd.com>
	<48E40687.9090501@coresystems.de>
	<20081001234232.GC25831@cosmic.amd.com>
Message-ID: <20081002003049.13358.qmail@stuge.se>

Jordan Crouse wrote:
> As a comparison - Ron's screenshot:
> 
> .png - 97466  bytes
> .jpg - 46877  bytes
> .rle - 24846  bytes

What about .lzma? If it's going into the larball, we already have
compression implemented, and it would be nice to have lossless
graphics and less computation.

Maybe we can even blit? How does lzma perform on bitmaps?


> Implementation wise - the LSS16 function I just wrote is about 40
> lines of code with lots of whitespace.

My only problem with LSS16 is that it's clearly designed for, and
thus limited to, a 16-color VGA mode. (The palette gives it away.)

For a 21st century firmware designed for 21st century hardware I
would like to have 21st century graphics. Please?

If we want to do modesetting (no) we could pick the nearest larger
mode and center the image. I am fine with picking one mode for now
and centering the image, possibly cropping it's edges.

As for formats, there are many choices. PCX is RLE but with some
metadata to allow for more image sizes and bit depths. PNG would
be cool because it is ubiquitous, however it isn't super simple.


//Peter



From peter at stuge.se  Thu Oct  2 02:41:34 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Oct 2008 02:41:34 +0200
Subject: [coreboot] [PATCH v2] AMD DBM690T IRQ cleanup
In-Reply-To: <48E41404.5090307@gmx.net>
References: <48E379E5.4080706@gmx.net> <48E3B90A.2030304@amd.com>
	<48E3F874.2090600@gmx.net> <48E41404.5090307@gmx.net>
Message-ID: <20081002004134.15845.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> New attempt with more cleanups and hopefully correct conversion:

Still not. I think this will be faster by hand.


> +#define IO_LOCAL_INT(type, intr, apicid, pin) \
> +#define ISA_INT(intr, pin) \

..maybe ISA_INT should also take apicid?


>  	/* sata */
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
> -			 0, 18 << 2 | 0, apicid_sb600, 22);
> +	PCI_INT(0x0, 0x13, 0x0, 0x16);

Problem here: 18 != 0x13


> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
> -			 bus_rs690[2], 0x0 << 2 | 0, apicid_sb600, 18);
..
> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
> -			 bus_rs690[6], 0x0 << 2 | 0, apicid_sb600, 18);

> +	PCI_INT(bus_rs690[2], 0x0, 0x0, 0x13);
> +	PCI_INT(bus_rs690[6], 0x0, 0x0, 0x13);

Again: 18 != 0x13


Fine otherwise. Fix the above and commit please.

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Thu Oct  2 02:52:53 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Oct 2008 02:52:53 +0200
Subject: [coreboot] r3628 - trunk/coreboot-v2/src/mainboard/amd/dbm690t
Message-ID: <mailman.2153.1355071390.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-10-02 02:52:53 +0200 (Thu, 02 Oct 2008)
New Revision: 3628

Modified:
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c
Log:
Use easily readable macros to setup interrupt routing.
Change a few PCI bus/dev/fn to use hexadecimal numbers.
Kill unused variables.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c	2008-10-01 22:15:20 UTC (rev 3627)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c	2008-10-02 00:52:53 UTC (rev 3628)
@@ -45,7 +45,6 @@
 	static const char oem[8] = "ATI     ";
 	static const char productid[12] = "DBM690T     ";
 	struct mp_config_table *mc;
-	int i, j;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	memset(mc, 0, sizeof(*mc));
@@ -119,104 +118,77 @@
 	}
 
 	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	smp_write_intsrc(mc, mp_ExtINT,
-			 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa,
-			 0x0, apicid_sb600, 0x0);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x1, apicid_sb600, 0x1);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x0, apicid_sb600, 0x2);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x3, apicid_sb600, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x4, apicid_sb600, 0x4);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x6, apicid_sb600, 0x6);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x7, apicid_sb600, 0x7);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0xc, apicid_sb600, 0xc);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0xd, apicid_sb600, 0xd);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0xe, apicid_sb600, 0xe);
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+	smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+	
+	IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb600, 0x0);
 
+	/* ISA ints are edge-triggered, and usually originate from the ISA bus,
+	 * or its remainings.
+	 */
+#define ISA_INT(intr, pin) \
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, (intr), apicid_sb600, (pin))
+
+	ISA_INT(0x1, 0x1);
+	ISA_INT(0x0, 0x2);
+	ISA_INT(0x3, 0x3);
+	ISA_INT(0x4, 0x4);
+	ISA_INT(0x6, 0x6);
+	ISA_INT(0x7, 0x7);
+	ISA_INT(0xc, 0xc);
+	ISA_INT(0xd, 0xd);
+	ISA_INT(0xe, 0xe);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
+#define PCI_INT(bus, dev, fn, pin) \
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
+
 	/* usb */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 19 << 2 | 0, apicid_sb600, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 19 << 2 | 1, apicid_sb600, 0x11);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 19 << 2 | 2, apicid_sb600, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 19 << 2 | 3, apicid_sb600, 0x13);
+	PCI_INT(0x0, 0x13, 0x0, 0x10);
+	PCI_INT(0x0, 0x13, 0x1, 0x11);
+	PCI_INT(0x0, 0x13, 0x2, 0x12);
+	PCI_INT(0x0, 0x13, 0x3, 0x13);
 
 	/* sata */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 18 << 2 | 0, apicid_sb600, 22);
+	PCI_INT(0x0, 0x12, 0x0, 0x16);
 
 	/* HD Audio: b0:d20:f1:reg63 should be 0. */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 0, 20 << 2 | 0, apicid_sb600, 16);
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
 
 	/* on board NIC & Slot PCIE.  */
-	i = 2;
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[1], 0x5 << 2 | 0, apicid_sb600, 18);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[1], 0x5 << 2 | 1, apicid_sb600, 19);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[2], 0x0 << 2 | 0, apicid_sb600, 18);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[3], 0x0 << 2 | 0, apicid_sb600, 19);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[4], 0x0 << 2 | 0, apicid_sb600, 16);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[5], 0x0 << 2 | 0, apicid_sb600, 17);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[6], 0x0 << 2 | 0, apicid_sb600, 18);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_rs690[7], 0x0 << 2 | 0, apicid_sb600, 19);
+	PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
+	PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
+	PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
+	PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
+	PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
+	PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
+	PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
+	PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
 
 	/* PCI slots */
-	i += 6;
-	j = 5;
 	/* PCI_SLOT 0. */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 5 << 2 | 0, apicid_sb600, 20);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 5 << 2 | 1, apicid_sb600, 21);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 5 << 2 | 2, apicid_sb600, 22);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 5 << 2 | 3, apicid_sb600, 23);
+	PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
 
 	/* PCI_SLOT 1. */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 6 << 2 | 0, apicid_sb600, 21);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 6 << 2 | 1, apicid_sb600, 22);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 6 << 2 | 2, apicid_sb600, 23);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 6 << 2 | 3, apicid_sb600, 20);
+	PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
 
 	/* PCI_SLOT 2. */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 7 << 2 | 0, apicid_sb600, 22);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 7 << 2 | 1, apicid_sb600, 23);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 7 << 2 | 2, apicid_sb600, 20);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
-			 bus_sb600[1], 7 << 2 | 3, apicid_sb600, 21);
+	PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
 
 	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	smp_write_intsrc(mc, mp_ExtINT,
-			 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa,
-			 0x0, MP_APIC_ALL, 0x0);
-	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
 	/* There is no extension information... */
 
 	/* Compute the checksums */




From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  2 02:53:28 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 02 Oct 2008 02:53:28 +0200
Subject: [coreboot] [PATCH v2] AMD DBM690T IRQ cleanup
In-Reply-To: <20081002004134.15845.qmail@stuge.se>
References: <48E379E5.4080706@gmx.net>
	<48E3B90A.2030304@amd.com>	<48E3F874.2090600@gmx.net>
	<48E41404.5090307@gmx.net> <20081002004134.15845.qmail@stuge.se>
Message-ID: <48E41B88.1020104@gmx.net>

On 02.10.2008 02:41, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> New attempt with more cleanups and hopefully correct conversion:
>>     
>
> Still not. I think this will be faster by hand.
>   

Ah, and I did a search/replace for the decimal/hex conversion to avoid
typos, so the typo struck me in thesearch/replace. My bad.


>> +#define IO_LOCAL_INT(type, intr, apicid, pin) \
>> +#define ISA_INT(intr, pin) \
>>     
>
> ..maybe ISA_INT should also take apicid?
>   

I'll try to find out whether there is any board in v2 where ISA_INT
would need two different apicids. This is on my global cleanup list anyway.


>>  	/* sata */
>> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
>> -			 0, 18 << 2 | 0, apicid_sb600, 22);
>> +	PCI_INT(0x0, 0x13, 0x0, 0x16);
>>     
>
> Problem here: 18 != 0x13
>
>
>   
>> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
>> -			 bus_rs690[2], 0x0 << 2 | 0, apicid_sb600, 18);
>>     
> ..
>   
>> -	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
>> -			 bus_rs690[6], 0x0 << 2 | 0, apicid_sb600, 18);
>>     
>
>   
>> +	PCI_INT(bus_rs690[2], 0x0, 0x0, 0x13);
>> +	PCI_INT(bus_rs690[6], 0x0, 0x0, 0x13);
>>     
>
> Again: 18 != 0x13
>
>
> Fine otherwise. Fix the above and commit please.
>
> Acked-by: Peter Stuge <peter at stuge.se>
>   

Thanks, r3628.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From info at coresystems.de  Thu Oct  2 03:27:11 2008
From: info at coresystems.de (coreboot information)
Date: Thu, 02 Oct 2008 03:27:11 +0200
Subject: [coreboot] r3628 build service
Message-ID: <E1KlCyF-0000Sy-Cr@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "hailfinger" checked in revision 3628 to
the coreboot source repository and caused the following 
changes:

Change Log:
Use easily readable macros to setup interrupt routing.
Change a few PCI bus/dev/fn to use hexadecimal numbers.
Kill unused variables.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>


Build Log:
Compilation of amd:dbm690t has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3628&device=dbm690t&vendor=amd
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3628&device=j7f24&vendor=jetway
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3628&device=epia-cn&vendor=via


If something broke during this checkin please be a pain 
in hailfinger's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Thu Oct  2 03:35:04 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Oct 2008 03:35:04 +0200
Subject: [coreboot] r3629 - trunk/coreboot-v2/src/mainboard/amd/dbm690t
Message-ID: <mailman.2154.1355071390.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-10-02 03:35:03 +0200 (Thu, 02 Oct 2008)
New Revision: 3629

Modified:
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c
Log:
Fix a typo.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c	2008-10-02 00:52:53 UTC (rev 3628)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c	2008-10-02 01:35:03 UTC (rev 3629)
@@ -45,6 +45,7 @@
 	static const char oem[8] = "ATI     ";
 	static const char productid[12] = "DBM690T     ";
 	struct mp_config_table *mc;
+	int j;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	memset(mc, 0, sizeof(*mc));




From info at coresystems.de  Thu Oct  2 04:10:47 2008
From: info at coresystems.de (coreboot information)
Date: Thu, 02 Oct 2008 04:10:47 +0200
Subject: [coreboot] r3629 build service
Message-ID: <E1KlDeR-0003BN-7S@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "hailfinger" checked in revision 3629 to
the coreboot source repository and caused the following 
changes:

Change Log:
Fix a typo.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Build Log:
Compilation of amd:dbm690t has been fixed
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3629&device=j7f24&vendor=jetway
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3629&device=epia-cn&vendor=via


If something broke during this checkin please be a pain 
in hailfinger's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From corey.osgood at gmail.com  Thu Oct  2 05:31:21 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 1 Oct 2008 23:31:21 -0400
Subject: [coreboot] splash screen
In-Reply-To: <20081002003049.13358.qmail@stuge.se>
References: <20080923172805.12279.qmail@stuge.se>
	<20080923174449.17274.qmail@stuge.se>
	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>
	<20081001184713.GD22980@cosmic.amd.com>
	<13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
	<20081001214824.GA25831@cosmic.amd.com>
	<48E40687.9090501@coresystems.de>
	<20081001234232.GC25831@cosmic.amd.com>
	<20081002003049.13358.qmail@stuge.se>
Message-ID: <dd3c80060810012031x54655195t2204d54290b6cf89@mail.gmail.com>

On Wed, Oct 1, 2008 at 8:30 PM, Peter Stuge <peter at stuge.se> wrote:
> Jordan Crouse wrote:
>> As a comparison - Ron's screenshot:
>>
>> .png - 97466  bytes
>> .jpg - 46877  bytes
>> .rle - 24846  bytes
>
> What about .lzma? If it's going into the larball, we already have
> compression implemented, and it would be nice to have lossless
> graphics and less computation.
>
> Maybe we can even blit? How does lzma perform on bitmaps?
>
>
>> Implementation wise - the LSS16 function I just wrote is about 40
>> lines of code with lots of whitespace.
>
> My only problem with LSS16 is that it's clearly designed for, and
> thus limited to, a 16-color VGA mode. (The palette gives it away.)
>
> For a 21st century firmware designed for 21st century hardware I
> would like to have 21st century graphics. Please?

Fully agreed. IMO, if you're going to do bootsplash, you might as well
do it right. Is there any reason we can only support one standard?

-Corey



From cirdec.arevir at gmail.com  Thu Oct  2 09:23:42 2008
From: cirdec.arevir at gmail.com (Cedric RIVERA)
Date: Thu, 2 Oct 2008 09:23:42 +0200
Subject: [coreboot] Master degree student wanting to give some help.
In-Reply-To: <13426df10810011409n41b616f7v5149149872dea0ca@mail.gmail.com>
References: <5450d0b40809300420x46eca371s6705799e1e87cd4@mail.gmail.com>
	<20080930144953.26824.qmail@stuge.se>
	<5450d0b40810010140l2ac3e6c3na08c7d0a2442889e@mail.gmail.com>
	<13426df10810011409n41b616f7v5149149872dea0ca@mail.gmail.com>
Message-ID: <5450d0b40810020023s5c88a234x3a0d7e28d8c7d4c1@mail.gmail.com>

  Hello,

  Yes, 'I'm on it, first for Gigabyte M57SLI.

Cedric.

2008/10/1 ron minnich <rminnich at gmail.com>

> Cedric this is good news. You'll be working on v3 right :-)
>
> ron
>
-------------- next part --------------
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From svn at coreboot.org  Thu Oct  2 09:38:29 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Oct 2008 09:38:29 +0200
Subject: [coreboot] r74 - trunk/filo/main/grub
Message-ID: <mailman.2155.1355071390.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2008-10-02 09:38:29 +0200 (Thu, 02 Oct 2008)
New Revision: 74

Modified:
   trunk/filo/main/grub/builtins.c
Log:
Make the FILO 'color' command set a more helpful errnum rather than
using the one from the integer parser.

Signed-off-by: Alex Mauer <hawke at hawkensest.net> 
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>

Modified: trunk/filo/main/grub/builtins.c
===================================================================
--- trunk/filo/main/grub/builtins.c	2008-09-30 21:14:11 UTC (rev 73)
+++ trunk/filo/main/grub/builtins.c	2008-10-02 07:38:29 UTC (rev 74)
@@ -218,8 +218,10 @@
 	highlight = skip_to(0, arg);
 
 	new_normal_color = color_number(normal);
-	if (new_normal_color < 0 && !safe_parse_maxint(&normal, &new_normal_color))
+	if (new_normal_color < 0 && !safe_parse_maxint(&normal, &new_normal_color)) {
+		errnum = ERR_BAD_ARGUMENT;
 		return 1;
+	}
 
 	/* The second argument is optional, so set highlight_color to inverted NORMAL_COLOR.  */
 	if (!*highlight)
@@ -227,8 +229,10 @@
 				       | ((new_normal_color & 0xf) << 4));
 	else {
 		new_highlight_color = color_number(highlight);
-		if (new_highlight_color < 0 && !safe_parse_maxint(&highlight, &new_highlight_color))
+		if (new_highlight_color < 0 && !safe_parse_maxint(&highlight, &new_highlight_color)) {
+			errnum = ERR_BAD_ARGUMENT;
 			return 1;
+		}
 	}
 
 	console_setcolor(new_normal_color, new_highlight_color);




From svn at coreboot.org  Thu Oct  2 09:39:09 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Oct 2008 09:39:09 +0200
Subject: [coreboot] r75 - trunk/filo/main/grub
Message-ID: <mailman.2156.1355071390.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2008-10-02 09:39:09 +0200 (Thu, 02 Oct 2008)
New Revision: 75

Modified:
   trunk/filo/main/grub/builtins.c
   trunk/filo/main/grub/char_io.c
   trunk/filo/main/grub/grub.c
Log:
Swaps the order of the nybbles in the color setting byte to make it
the same as the traditional VGA BIOS color byte.

Signed-off-by: Alex Mauer <hawke at hawkesnest.net> 
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>

Modified: trunk/filo/main/grub/builtins.c
===================================================================
--- trunk/filo/main/grub/builtins.c	2008-10-02 07:38:29 UTC (rev 74)
+++ trunk/filo/main/grub/builtins.c	2008-10-02 07:39:09 UTC (rev 75)
@@ -166,7 +166,7 @@
 
 	auto int color_number(char *str);
 
-	/* Convert the color name STR into the magical number.  */
+	/* Convert the color name STR into a VGA color number.  */
 	auto int color_number(char *str) {
 		char *ptr;
 		int i;
@@ -188,10 +188,10 @@
 			str += 6;
 		}
 
-		/* Search for the color name.  */
+		/* Search for the foreground color name.  */
 		for (i = 0; i < 16; i++)
 			if (strcmp(color_list[i], str) == 0) {
-				color |= (i << 4);
+				color |= i;
 				break;
 			}
 
@@ -201,10 +201,10 @@
 		str = ptr;
 		nul_terminate(str);
 
-		/* Search for the color name.  */
+		/* Search for the background color name.  */
 		for (i = 0; i < 8; i++)
 			if (strcmp(color_list[i], str) == 0) {
-				color |= i;
+				color |= (i <<4);
 				break;
 			}
 

Modified: trunk/filo/main/grub/char_io.c
===================================================================
--- trunk/filo/main/grub/char_io.c	2008-10-02 07:38:29 UTC (rev 74)
+++ trunk/filo/main/grub/char_io.c	2008-10-02 07:39:09 UTC (rev 75)
@@ -746,8 +746,8 @@
 
 void console_setcolor(int normal_color, int highlight_color)
 {
-	init_pair(1,(normal_color >> 4) &0xf, normal_color & 0xf);
-	init_pair(2,(highlight_color >> 4) &0xf, highlight_color & 0xf);
+	init_pair(1, normal_color & 0xf, (normal_color >> 4) & 0xf);
+	init_pair(2, highlight_color & 0xf, (highlight_color >> 4) & 0xf);
 
 	/* Make curses update the whole screen */
 	redrawwin(stdscr);

Modified: trunk/filo/main/grub/grub.c
===================================================================
--- trunk/filo/main/grub/grub.c	2008-10-02 07:38:29 UTC (rev 74)
+++ trunk/filo/main/grub/grub.c	2008-10-02 07:39:09 UTC (rev 75)
@@ -901,8 +901,8 @@
 	endwin();
 	using_grub_interface = 1;
 
-	console_setcolor((COLOR_WHITE << 4) | COLOR_BLACK, 
-			 (COLOR_BLACK << 4) | COLOR_WHITE);
+	console_setcolor((COLOR_BLACK << 4) | COLOR_WHITE,
+			 (COLOR_WHITE << 4) | COLOR_BLACK);
 
 	/* Initialize the kill buffer.  */
 	*kill_buf = 0;




From svn at coreboot.org  Thu Oct  2 09:42:24 2008
From: svn at coreboot.org (FILO)
Date: Thu, 02 Oct 2008 07:42:24 -0000
Subject: [coreboot] [FILO] #15: 'color' command doesn't accept
In-Reply-To: <060.7c9084bfebba45b6a6df864d30819b59@coreboot.org>
References: <060.7c9084bfebba45b6a6df864d30819b59@coreboot.org>
Message-ID: <069.fedb2dfd3b9c0f2684678bee39585138@coreboot.org>

#15: 'color' command doesn't accept
-------------------------------------+--------------------------------------
    Reporter:  hawke at hawkesnest.net  |         Owner:  oxygene                 
        Type:  defect                |        Status:  reopened                
    Priority:  minor                 |     Milestone:                          
   Component:  FILO                  |       Version:                          
  Resolution:                        |      Keywords:                          
Dependencies:                        |   Patchstatus:  patch has been committed
-------------------------------------+--------------------------------------

Comment(by oxygene):

 I commited hawke's patches (Changesets 74, 75). Please re-test and close.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/filo/ticket/15#comment:7>
FILO <http://www.coreboot.org/FILO>


From scrocker at ampltd.com  Thu Oct  2 10:09:49 2008
From: scrocker at ampltd.com (Stephen Crocker)
Date: Thu, 02 Oct 2008 09:09:49 +0100
Subject: [coreboot] lpgcc calling itself
Message-ID: <48E481CD.3020409@ampltd.com>

I have noticed a problem with lpgcc under Fedora Core 9 when building 
Tint.  Instead of calling gcc, it calls itself.  Looking at the Makefile 
and the script itself, I think I can see why:

 From lpgcc:
if [ "$CC" != "" ]; then
DEFAULT_CC=$CC
else
DEFAULT_CC=gcc
fi

 From the tint Makefile:
CC := $(LIBPAYLOAD_DIR)/bin/lpgcc

Is this a bug in tint or a bug in libpayload?



From cirdec.arevir at gmail.com  Wed Oct  1 09:40:01 2008
From: cirdec.arevir at gmail.com (Cedric RIVERA)
Date: Wed, 1 Oct 2008 09:40:01 +0200
Subject: [coreboot] Master degree student wanting to give some help.
In-Reply-To: <48E23929.5080100@onelabs.com>
References: <5450d0b40809300420x46eca371s6705799e1e87cd4@mail.gmail.com>
	<48E23929.5080100@onelabs.com>
Message-ID: <5450d0b40810010040wfb7d08clbda1b68c39756d06@mail.gmail.com>

  Hello,

  Well, thank you for welcoming me like this, I'm little impressed by this
so amazing Coreboot project but I will be so glad to give help.

  Like I said before I have no AMD690 board yet but I could start testing
and working on the M57SLI to get familiar with the project architecture and
then if you can get me a board it would be great, I'll accept with no
condition ;-)

Thank you so much.

Cedric.


2008/9/30 bari <bari at onelabs.com>

> It would be great if you could get the AM2, 690/600 code to work on a few
> production boards that are readily available through distributors.
>
> I'd be happy to get you a board to start on and supervise.
>
> -Bari
>
> Cedric RIVERA wrote:
>
>>  Hello everybody,
>>
>>  I'm a french master degree student in Free Software ingeneering, looking
>> for a year project to join and I really love to be involved in Coreboot
>> community to :
>>
>>   improve AMD690G chipset support, or
>>   Openmoko coreboot port or
>>   port coreboot-v3 to Gigabyte M57SLI-S4, I've got one to develop.
>>
>>  I just need that someone supervise my work and do, monthly, a feedback to
>> my teacher at the university to have a note.
>>
>> Son is someone interested ?
>>
>> Thank you for your attention,
>>
>> Regards,
>>
>> Cedric RIVERA.
>>
>> Master I2L - Universit? du Littoral - C?te d'Opale, France.
>>
>>
>>
>> ------------------------------------------------------------------------
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
>
>
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From scrocker at ampltd.com  Thu Oct  2 12:21:51 2008
From: scrocker at ampltd.com (Stephen Crocker)
Date: Thu, 02 Oct 2008 11:21:51 +0100
Subject: [coreboot] Status of OpenVSA?
Message-ID: <48E4A0BF.9050009@ampltd.com>

I have been experimenting with the OpenVSA code and have found that it 
becomes stuck on POST code 17.  By adding extra codes, I have narrowed 
this down to the SAVE_STATE macro, which reads the PCI address port (cf8).

Furthermore, in order to build it, I had to remove the -Werror flag from 
the Makefile because of several "cast from pointer to integer of 
different size" errors.

What is the status of the OpenVSA code at the moment?  Are these known 
problems or could it be a problem with my build environment?  Has anyone 
used it successfully?



From avg at icyb.net.ua  Thu Oct  2 12:27:11 2008
From: avg at icyb.net.ua (Andriy Gapon)
Date: Thu, 02 Oct 2008 13:27:11 +0300
Subject: [coreboot] Is Coreboot selfmodifying? Award legacy Bios is!
In-Reply-To: <E1Kl4BW-0000eP-QL@aun.bellman.mea>
References: <E1Kl4BW-0000eP-QL@aun.bellman.mea>
Message-ID: <48E4A1FF.30304@icyb.net.ua>

on 01/10/2008 19:04 Mats Erik Andersson said the following:
> Hello all,
> 
> the cryptic subject of this message is due to my efforts
> to verify that Flashrom is producing correct images.
> 
> After much practical testing I have been able to conclude
> positively that the Award Bios 4.51 of a FIC mainboard
> is rewriting the blocks
> 
>    0x0003800 - 0x00038fff     cleartext on system characteristica,
>    0x0003a00 - 0x0003afff     pci-table.

I think that this is related to ESCD updates.
It seems that some proprietary BIOSes contain flash writing routines
which sometimes are even exposed for external use (via special signatures).

> at each reboot. Now I wonder if also Coreboot is using this opportunity
> under some circumstances. It is not that I think it is a commendable
> thing to do, instead it is a rather hazardous endeavour in my eyes.
> 
> Best regards,
> 
> Mats Erik Andersson
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 


-- 
Andriy Gapon



From avg at icyb.net.ua  Thu Oct  2 12:35:06 2008
From: avg at icyb.net.ua (Andriy Gapon)
Date: Thu, 02 Oct 2008 13:35:06 +0300
Subject: [coreboot] keyboard init patch
In-Reply-To: <48E10FA1.8090201@amd.com>
References: <48DD1598.5040901@amd.com> <48E0F3AF.30308@icyb.net.ua>
	<48E10FA1.8090201@amd.com>
Message-ID: <48E4A3DA.8030902@icyb.net.ua>

on 29/09/2008 20:25 Marc Jones said the following:
> Andriy Gapon wrote:
>> on 26/09/2008 20:02 Marc Jones said the following:
>>> This patch fixes the it8712f keyboard issues and should also fix any
>>> general keyboard init issues with other SIOs.
>>>
>>> Marc
>>
>> Guys,
>>
>> you might find this useful:
>> http://article.gmane.org/gmane.comp.emulators.bochs.devel/7843
>> It seems that this was included into bochs code.
>>
>> Maybe this is something that we would qemu to support as well.
>>
> 
> coreboot is a little better behaved than that. It only writes 0xCA/0xCB
> for specific SIOs(keyboard controllers). Since coreboot builds for qemu
> we don't need to make any changes.

I see, thank you.

Actually I have a goal to tweak qemu so that it can run coreboot images
that are configured for real 440BX systems. For that qemu should be both
sufficiently correct and sufficiently generic in its emulation of 440BX
hardware.

But I am highjacking this thread already.


-- 
Andriy Gapon



From svn at coreboot.org  Thu Oct  2 13:07:04 2008
From: svn at coreboot.org (FILO)
Date: Thu, 02 Oct 2008 11:07:04 -0000
Subject: [coreboot] [FILO] #10: 'help' word wrapping problem
In-Reply-To: <060.dafbcbfdd3c3a1648de61224b50ee624@coreboot.org>
References: <060.dafbcbfdd3c3a1648de61224b50ee624@coreboot.org>
Message-ID: <069.58ac20b7d7d2a910bfd2ceef50bb2c88@coreboot.org>

#10: 'help' word wrapping problem
-------------------------------------+--------------------------------------
    Reporter:  hawke at hawkesnest.net  |         Owner:  oxygene          
        Type:  defect                |        Status:  assigned         
    Priority:  minor                 |     Milestone:                   
   Component:  FILO                  |       Version:                   
  Resolution:                        |      Keywords:                   
Dependencies:                        |   Patchstatus:  there is no patch
-------------------------------------+--------------------------------------
Changes (by oxygene):

  * owner:  somebody => oxygene
  * status:  new => assigned


Comment:

 You're on the right track, I think. Following fixes it for me:
 --- main/grub/char_io.c (revision 2062)
 +++ main/grub/char_io.c (local)
 @@ -935,6 +935,7 @@
         } else if (isprint(c)) {
                 getyx(stdscr, y, x);
                 if (x + 1 == COLS) {
 +                       console_putchar('\r');
                         console_putchar('\n');
                 }
                 if (console_color_state == COLOR_STATE_HIGHLIGHT)


 There is another issue (the four spaces on the long description lines are
 not always clean). Once I figured that out, I'll post a patch

-- 
Ticket URL: <http://tracker.coreboot.org/trac/filo/ticket/10#comment:1>
FILO <http://www.coreboot.org/FILO>


From svn at coreboot.org  Thu Oct  2 13:20:57 2008
From: svn at coreboot.org (FILO)
Date: Thu, 02 Oct 2008 11:20:57 -0000
Subject: [coreboot] [FILO] #10: 'help' word wrapping problem
In-Reply-To: <060.dafbcbfdd3c3a1648de61224b50ee624@coreboot.org>
References: <060.dafbcbfdd3c3a1648de61224b50ee624@coreboot.org>
Message-ID: <069.8ba85f3ea86a2e9ba0f1874c2529e2f9@coreboot.org>

#10: 'help' word wrapping problem
-------------------------------------+--------------------------------------
    Reporter:  hawke at hawkesnest.net  |         Owner:  oxygene           
        Type:  defect                |        Status:  assigned          
    Priority:  minor                 |     Milestone:                    
   Component:  FILO                  |       Version:                    
  Resolution:                        |      Keywords:                    
Dependencies:                        |   Patchstatus:  patch needs review
-------------------------------------+--------------------------------------
Changes (by oxygene):

  * patchstatus:  there is no patch => patch needs review


Comment:

 Patch attached. I'll need to figure out why grub_printf("const string") is
 different than grub_putstr("const string"), but putstr is the faster
 choice anyway (not that this really matters ;-) )

-- 
Ticket URL: <http://tracker.coreboot.org/trac/filo/ticket/10#comment:2>
FILO <http://www.coreboot.org/FILO>


From mats.andersson at gisladisker.se  Thu Oct  2 14:13:46 2008
From: mats.andersson at gisladisker.se (Mats Erik Andersson)
Date: Thu, 02 Oct 2008 14:13:46 +0200
Subject: [coreboot] Exact status of gPXE support?
Message-ID: <E1KlN3y-00012I-7O@aun.bellman.mea>

Hi there!

Spurred by the tellings of Chris Kilgour on his modifications
to gPXE and libpayload, paired with my own inability to find
the full answer as to the interface between Coreboot and gPXE,
I now plead to those of you with thorough insight:

   To what extent does gPXE presently interface "well" with Coreboot?
   Is the position identical for coreboot-v2 and coreboot-v3?

To be specific for my present intents, my interest is not
primarily geared towards the ability to use gPXE and ELF-images,
but is more basic:

   1. Is there an available and ready interface in Coreboot
      that allows the detection of an PXE-ROM image inside
      an PCI ethernet card adapter? Can execution be transferred
      to a copy of that code segment?

   2. Is it known whether a "slimmed down" gPXE can be built and
      incorporated into a Coreboot image under the lesser demand
      that the purpose of the gPXE code is only that of getting
      and running the executable "pxelinux.0", fetched from another
      server, thus making the system autonomous? There could possibly
      exist some code segment in PXElinux that depends on either
      16-bit mode, or lagacy Bios calls, but I do not a priori know
      that with any certainty!

The previous discussions and informations that I have found,
they were all centered on the ELF format and its concequences
for Coreboot in conjunction with gPXE/Etherboot. I would gladly
receive pointers and references that prove me wrong or my
misconceptions to be grave!

Kind regards

Mats E Andersson



From peter at stuge.se  Thu Oct  2 14:18:44 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Oct 2008 14:18:44 +0200
Subject: [coreboot] Status of OpenVSA?
In-Reply-To: <48E4A0BF.9050009@ampltd.com>
References: <48E4A0BF.9050009@ampltd.com>
Message-ID: <20081002121844.15245.qmail@stuge.se>

Stephen Crocker wrote:
> Has anyone used it successfully?

I don't think so. So far it is very early work not receiving much
other attention.


//Peter



From peter at stuge.se  Thu Oct  2 14:26:31 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Oct 2008 14:26:31 +0200
Subject: [coreboot] Exact status of gPXE support?
In-Reply-To: <E1KlN3y-00012I-7O@aun.bellman.mea>
References: <E1KlN3y-00012I-7O@aun.bellman.mea>
Message-ID: <20081002122631.17400.qmail@stuge.se>

Mats Erik Andersson wrote:
> To what extent does gPXE presently interface "well" with Coreboot?

Very little. Without the work as outlined by Chris gPXE does not
function as a payload at all. Etherboot works just fine however.


> Is the position identical for coreboot-v2 and coreboot-v3?

Yes.


> 1. Is there an available and ready interface in Coreboot
>    that allows the detection of an PXE-ROM image inside
>    an PCI ethernet card adapter?

If by PXE-ROM you mean option ROM then yes, coreboot scans for
option ROMs.


>    Can execution be transferred to a copy of that code segment?

No, if option ROMs are executed they are executed in emulated real
mode. Either in VM8086 mode, or using x86emu.


> 2. Is it known whether a "slimmed down" gPXE can be built and
>    incorporated into a Coreboot image under the lesser demand
>    that the purpose of the gPXE code is only that of getting
>    and running the executable "pxelinux.0", fetched from another
>    server, thus making the system autonomous?

This is not possible.


>    There could possibly exist some code segment in PXElinux that
>    depends on either 16-bit mode, or lagacy Bios calls, but I do
>    not a priori know that with any certainty!

Yes, PXE requires real mode and BIOS interrupt services.


But all network booting is not PXE. PXE is just a standard with a
limited subset of what Etherboot and gPXE can do. They can both
simply use DHCP+TFTP to boot a system, and that will work just fine
with coreboot.


//Peter



From tiagomnm at gmail.com  Thu Oct  2 14:32:02 2008
From: tiagomnm at gmail.com (Tiago Marques)
Date: Thu, 2 Oct 2008 13:32:02 +0100
Subject: [coreboot] Master degree student wanting to give some help.
In-Reply-To: <20081001212933.10147.qmail@stuge.se>
References: <5450d0b40809300420x46eca371s6705799e1e87cd4@mail.gmail.com>
	<20080930144953.26824.qmail@stuge.se>
	<b1335fe90810010635jc25fe7euda301ca46581e325@mail.gmail.com>
	<20081001212933.10147.qmail@stuge.se>
Message-ID: <b1335fe90810020532me2305e4ib39e4f8bdb3fa663@mail.gmail.com>

The current Atom platform and the Poulsbo platform havea PCI bus, it's
successor, Moorestown, will have no PCI bus and this is pointed as a problem
to run Windows in it, Linux, I've heard, will work fine even without the PCI
bus.

If coreboot is to be eventually ported to that platform, I'm just pointing
this out, so you can prevent decisions that can hurt Coreboot in the long
run and cause a new code overhaul(v4).

Best regards,

                          Tiago Marques


On Wed, Oct 1, 2008 at 10:29 PM, Peter Stuge <peter at stuge.se> wrote:

> Hi Tiago,
>
> Tiago Marques wrote:
> > > >    Openmoko coreboot port or
> > >
> > > Probably not so useful. Is there a PCI bus in the Openmoko?
> >
> > Why is this important?
>
> coreboot really does just two things; RAM init and bus init.
>
> The buses coreboot knows so far are V-Link, HT and PCI(e).
> (Did I miss some?)
>
>
> > Supposedly, the next iteration of Intel's Atom platform won't
> > feature a PCI bus, coreboot won't work with it?
>
> coreboot already does not work with much of Intel's hardware, I don't
> think a new Atom will have much effect on that.
>
> That aside, of course coreboot could be made to support Atom. If
> there's no PCI then maybe something else needs initialization,
> complex or simple.
>
> The point is that RAM and bus init is often pretty tricky, and on
> smaller systems with simpler buses there isn't as much for coreboot
> to do.
>
> But of course, coreboot should run everywhere! :p
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From stepan at coresystems.de  Thu Oct  2 15:34:38 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 02 Oct 2008 15:34:38 +0200
Subject: [coreboot] r877 - in coreboot-v3: arch/x86/amd/model_fxx
 mainboard/gigabyte/m57sli northbridge/amd/k8 southbridge/nvidia/mcp55
In-Reply-To: <13426df10810010702n1633fff3kb764852c6eedbd23@mail.gmail.com>
References: <48E343A1.4000003@coresystems.de>
	<13426df10810010702n1633fff3kb764852c6eedbd23@mail.gmail.com>
Message-ID: <48E4CDEE.4050806@coresystems.de>

ron minnich wrote:
>>> m57sli mostly builds again. The stage0 is too large at 24k.
>>> We need to figure out if we should just grow stage0. My inclination is
>>> to say 'yes'.
>>>
>>>       
>> What's in stage0 that makes it so big? Is that part really required in
>> stage0?
>>     
>
> hyptertransport setup has to be in stage0. I can't see a way around it.
>   

Why? Can't this go to initram?




-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From jordan.crouse at amd.com  Thu Oct  2 16:36:19 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 2 Oct 2008 08:36:19 -0600
Subject: [coreboot] splash screen
In-Reply-To: <20081002003049.13358.qmail@stuge.se>
References: <20080923173708.GB30198@cosmic.amd.com>
	<20080923174449.17274.qmail@stuge.se>
	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>
	<20081001184713.GD22980@cosmic.amd.com>
	<13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
	<20081001214824.GA25831@cosmic.amd.com>
	<48E40687.9090501@coresystems.de>
	<20081001234232.GC25831@cosmic.amd.com>
	<20081002003049.13358.qmail@stuge.se>
Message-ID: <20081002143619.GE25831@cosmic.amd.com>

On 02/10/08 02:30 +0200, Peter Stuge wrote:
> Jordan Crouse wrote:
> > As a comparison - Ron's screenshot:
> > 
> > .png - 97466  bytes
> > .jpg - 46877  bytes
> > .rle - 24846  bytes
> 
> What about .lzma? If it's going into the larball, we already have
> compression implemented, and it would be nice to have lossless
> graphics and less computation.
>
> Maybe we can even blit? How does lzma perform on bitmaps?
> 
> 
> > Implementation wise - the LSS16 function I just wrote is about 40
> > lines of code with lots of whitespace.
> 
> My only problem with LSS16 is that it's clearly designed for, and
> thus limited to, a 16-color VGA mode. (The palette gives it away.)
> 
> For a 21st century firmware designed for 21st century hardware I
> would like to have 21st century graphics. Please?

Okay, everybody needs to calm down and take a step back here and look
at what we are talking about.  We are talking about an extensive
graphics infrastructure to display a splash screen for firmware
that can be up and into the kernel in less then a second.  Coreinfo
comes up so quickly on a Geode that it is visible when the monitor
finishes syncing.  Indeed, we are going to have to SLOW DOWN our 
payloads in order to display a splashscreen long enough for people
to read it.

Ron is right, there is something soothing about a splash screen - it
warms the hearts of our customers.  But come on - PNG?  PCX?  
16 bit color depths?  Is this really needed?  I am not at all interested
in making libpayload into a fully featured graphics engine - there are
better libraries that can do that.  All I was trying to do was something
simple to benefit Ron, and since every distribution in the world uses
isolinux + lss16, I figured that was a good shot.

Thats just my opinion - as always, patches are gladly accepted.  Just
remember who we are, what we are doing.  Somebody at the Linux Plumbers
Conference said, "Every time I see a splash screen, I wonder what they
have to hide".  Coreboot is the only loader on earth that doesn't actually
have anything to hide.  Lets try not to go overboard architecting a solution
for one problem we don't have.

Jordan


-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From jordan.crouse at amd.com  Thu Oct  2 16:37:26 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 2 Oct 2008 08:37:26 -0600
Subject: [coreboot] lpgcc calling itself
In-Reply-To: <48E481CD.3020409@ampltd.com>
References: <48E481CD.3020409@ampltd.com>
Message-ID: <20081002143726.GF25831@cosmic.amd.com>

On 02/10/08 09:09 +0100, Stephen Crocker wrote:
> I have noticed a problem with lpgcc under Fedora Core 9 when building 
> Tint.  Instead of calling gcc, it calls itself.  Looking at the Makefile 
> and the script itself, I think I can see why:
> 
>  From lpgcc:
> if [ "$CC" != "" ]; then
> DEFAULT_CC=$CC
> else
> DEFAULT_CC=gcc
> fi
> 
>  From the tint Makefile:
> CC := $(LIBPAYLOAD_DIR)/bin/lpgcc
> 
> Is this a bug in tint or a bug in libpayload?

Dohhh - thats very very bad.  Fixes forthcoming.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From stepan at coresystems.de  Thu Oct  2 16:44:42 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 02 Oct 2008 16:44:42 +0200
Subject: [coreboot] [PATCH] copy libpayload config to stage directory
Message-ID: <48E4DE5A.9020507@coresystems.de>

See patch

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From jordan.crouse at amd.com  Thu Oct  2 17:09:26 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 2 Oct 2008 09:09:26 -0600
Subject: [coreboot] copy libpayload config to stage directory
In-Reply-To: <48E4DE5A.9020507@coresystems.de>
References: <48E4DE5A.9020507@coresystems.de>
Message-ID: <20081002150926.GH25831@cosmic.amd.com>

On 02/10/08 16:44 +0200, Stefan Reinauer wrote:
> See patch
> 
> -- 
> coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
>       Tel.: +49 761 7668825 ? Fax: +49 761 7664613
> Email: info at coresystems.de  ? http://www.coresystems.de/
> Registergericht: Amtsgericht Freiburg ? HRB 7656
> Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866
> 

> * create directories explicitly. Not all versions of install know -D
> * install libpayload-config and libpayload.config, too.
> 
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Would it be less confusing if we named config.h libpayload-config.h
from the beginning?

Joradn

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Would it be less confusing if we named config.h libpayload-config.h
from the beginning?

Joradn

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Would it be less confusing if we named config.h libpayload-config.h
from the beginning?

Joradn

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Would it be less confusing if we named config.h libpayload-config.h
from the beginning?

Joradn

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Would it be less confusing if we named config.h libpayload-config.h
from the beginning?

Joradn

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Would it be less confusing if we named config.h libpayload-config.h
from the beginning?

Joradn

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Would it be less confusing if we named config.h libpayload-config.h
from the beginning and used the same name internally and externally?

Jordan

> Index: Makefile
> ===================================================================
> --- Makefile	(revision 3560)
> +++ Makefile	(working copy)
> @@ -126,13 +126,16 @@
>  	$(Q)printf "  INSTALL $(DESTDIR)/libpayload/include\n"
>  	$(Q)install -m 755 -d $(DESTDIR)/libpayload/include
>  	$(Q)for file in `find include -name *.h -type f`; do \
> -		install -m 644 -D $$file $(DESTDIR)/libpayload/$$file; \
> +		install -m 755 -d $(DESTDIR)/libpayload/`dirname $$file`; \
> +		install -m 644 $$file $(DESTDIR)/libpayload/$$file; \
>  	done
>  	$(Q)printf "  INSTALL $(DESTDIR)/libpayload/bin\n"
>  	$(Q)install -m 755 -d $(DESTDIR)/libpayload/bin
>  	$(Q)install -m 755 bin/lpgcc $(DESTDIR)/libpayload/bin
>  	$(Q)install -m 755 bin/lpas $(DESTDIR)/libpayload/bin
>  	$(Q)install -m 644 bin/lp.functions $(DESTDIR)/libpayload/bin
> +	$(Q)install -m 644 $(KCONFIG_AUTOHEADER) $(DESTDIR)/libpayload/include/libpayload-config.h
> +	$(Q)install -m 644 $(KCONFIG_AUTOCONFIG) $(DESTDIR)/libpayload/libpayload.config
>  
>  prepare:
>  	$(Q)mkdir -p $(obj)/util/kconfig/lxdialog




> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From svn at coreboot.org  Thu Oct  2 17:42:14 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Oct 2008 17:42:14 +0200
Subject: [coreboot] r3630 - trunk/coreboot-v2/src/southbridge/amd/sb600
Message-ID: <mailman.2157.1355071390.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-10-02 17:42:14 +0200 (Thu, 02 Oct 2008)
New Revision: 3630

Added:
   trunk/coreboot-v2/src/southbridge/amd/sb600/ac97.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/ac97audio.dts
   trunk/coreboot-v2/src/southbridge/amd/sb600/ac97modem.dts
   trunk/coreboot-v2/src/southbridge/amd/sb600/enable_usbdebug_direct.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/hda.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/hda.dts
   trunk/coreboot-v2/src/southbridge/amd/sb600/ide.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/ide.dts
   trunk/coreboot-v2/src/southbridge/amd/sb600/lpc.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/lpc.dts
   trunk/coreboot-v2/src/southbridge/amd/sb600/pci.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/pci.dts
   trunk/coreboot-v2/src/southbridge/amd/sb600/sata.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sata.dts
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.dts
   trunk/coreboot-v2/src/southbridge/amd/sb600/sm.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sm.dts
   trunk/coreboot-v2/src/southbridge/amd/sb600/stage1.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/stage1_reset.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/stage1_smbus.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/usb.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/usb.dts
   trunk/coreboot-v2/src/southbridge/amd/sb600/usb2.dts
Modified:
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.h
Log:
This is so that people can see it. This is the sb600 for v3. It almost 
certainly won't build -- that comes later. I am hoping to get some 
eyeballs on it for simple errors. 

rs690 is next. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Added: trunk/coreboot-v2/src/southbridge/amd/sb600/ac97.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/ac97.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/ac97.c	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/pci.h>
+#include <msr.h>
+#include <legacy.h>
+#include <device/pci_ids.h>
+#include <statictree.h>
+#include <config.h>
+#include "sb600.h"
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+struct device_operations ac97audio = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_AMD,
+			      .device = PCI_DEVICE_ID_ATI_SB600_ACI}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = 0,
+	.phase4_read_resources	 = pci_dev_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = pci_dev_enable_resources,
+	.phase6_init		 = NULL,
+	.ops_pci		 = &lops_pci,
+};
+
+struct device_operations ac97modem = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_AMD,
+			      .device = PCI_DEVICE_ID_ATI_SB600_MCI}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = 0,
+	.phase4_read_resources	 = pci_dev_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = pci_dev_enable_resources,
+	.phase6_init		 = NULL,
+	.ops_pci		 = &lops_pci,
+};
+

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/ac97audio.dts
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/ac97audio.dts	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/ac97audio.dts	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+{
+	device_operations = "ac97modem";
+	/* configuration variables go here */
+};

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/ac97modem.dts
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/ac97modem.dts	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/ac97modem.dts	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "ac97modem";
+	/* configuration variables go here */
+};

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/enable_usbdebug_direct.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/enable_usbdebug_direct.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/enable_usbdebug_direct.c	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/pci.h>
+#include <msr.h>
+#include <legacy.h>
+#include <device/pci.h>
+#include <statictree.h>
+#include <config.h>
+#include <io.h>
+#define SMBUS_IO_BASE 0x1000	/* Is it a temporary SMBus I/O base address? */
+	 /*SIZE 0x40 */
+
+#ifndef SB600_DEVN_BASE
+
+#define SB600_DEVN_BASE 0
+
+#endif
+
+#define EHCI_BAR_INDEX 0x10
+#define EHCI_BAR 0xFEF00000
+#define EHCI_DEBUG_OFFSET 0xE0
+
+void sb600_enable_usbdebug_direct(u32 port)
+{
+	set_debug_port(port);
+	pci_conf1_write_config32(PCI_BDF(0, SB600_DEVN_BASE + 0x13, 5),
+			   EHCI_BAR_INDEX, EHCI_BAR);
+	pci_conf1_write_config8(PCI_BDF(0, SB600_DEVN_BASE + 0x13, 5), 0x04, 0x2);	/* mem space enable */
+}

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/hda.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/hda.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/hda.c	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,265 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/pci.h>
+#include <msr.h>
+#include <legacy.h>
+#include <device/pci_ids.h>
+#include <statictree.h>
+#include <config.h>
+#include "sb600.h"
+
+static int set_bits(u8 * port, u32 mask, u32 val)
+{
+	u32 dword;
+	int count;
+
+	val &= mask;
+	dword = readl(port);
+	dword &= ~mask;
+	dword |= val;
+	writel(dword, port);
+
+	count = 50;
+	do {
+		dword = readl(port);
+		dword &= mask;
+		udelay(100);
+	} while ((dword != val) && --count);
+
+	if (!count)
+		return -1;
+
+	udelay(540);
+	return 0;
+}
+
+static int codec_detect(u8 * base)
+{
+	u32 dword;
+
+	/* 1 */
+	set_bits(base + 0x08, 1, 1);
+
+	/* 2 */
+	dword = readl(base + 0x0e);
+	dword |= 7;
+	writel(dword, base + 0x0e);
+
+	/* 3 */
+	set_bits(base + 0x08, 1, 0);
+
+	/* 4 */
+	set_bits(base + 0x08, 1, 1);
+
+	/* 5 */
+	dword = readl(base + 0xe);
+	dword &= 7;
+
+	/* 6 */
+	if (!dword) {
+		set_bits(base + 0x08, 1, 0);
+		printk(BIOS_DEBUG, "No codec!\n");
+		return 0;
+	}
+	return dword;
+
+}
+
+static u32 cim_verb_data[] = {
+	0x01471c10,
+	0x01471d40,
+	0x01471e01,
+	0x01471f01,
+/* 1 */
+	0x01571c12,
+	0x01571d10,
+	0x01571e01,
+	0x01571f01,
+/* 2 */
+	0x01671c11,
+	0x01671d60,
+	0x01671e01,
+	0x01671f01,
+/* 3 */
+	0x01771c14,
+	0x01771d20,
+	0x01771e01,
+	0x01771f01,
+/* 4 */
+	0x01871c30,
+	0x01871d90,
+	0x01871ea1,
+	0x01871f01,
+/* 5 */
+	0x01971cf0,
+	0x01971d11,
+	0x01971e11,
+	0x01971f41,
+/* 6 */
+	0x01a71c80,
+	0x01a71d30,
+	0x01a71e81,
+	0x01a71f01,
+/* 7 */
+	0x01b71cf0,
+	0x01b71d11,
+	0x01b71e11,
+	0x01b71f41,
+/* 8 */
+	0x01c71cf0,
+	0x01c71d11,
+	0x01c71e11,
+	0x01c71f41,
+/* 9 */
+	0x01d71cf0,
+	0x01d71d11,
+	0x01d71e11,
+	0x01d71f41,
+/* 10 */
+	0x01e71c50,
+	0x01e71d11,
+	0x01e71e44,
+	0x01e71f01,
+/* 11 */
+	0x01f71c60,
+	0x01f71d61,
+	0x01f71ec4,
+	0x01f71f01,
+};
+static unsigned find_verb(u32 viddid, u32 ** verb)
+{
+	struct device * azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));
+	struct southbridge_amd_sb600_dts_config *cfg =
+	    (struct southbridge_amd_sb600_config *)azalia_dev->chip_info;
+	printk(BIOS_DEBUG, "Dev=%s\n", dev_path(azalia_dev));
+	printk(BIOS_DEBUG, "Default viddid=%x\n", cfg->hda_viddid);
+	printk(BIOS_DEBUG, "Reading viddid=%x\n", viddid);
+	if (!cfg)
+		return 0;
+	if (viddid != cfg->hda_viddid)
+		return 0;
+	*verb = (u32 *) cim_verb_data;
+	return sizeof(cim_verb_data) / sizeof(u32);
+}
+
+static void codec_init(u8 * base, int addr)
+{
+	u32 dword;
+	u32 *verb;
+	u32 verb_size;
+	int i;
+
+	/* 1 */
+	do {
+		dword = readl(base + 0x68);
+	} while (dword & 1);
+
+	dword = (addr << 28) | 0x000f0000;
+	writel(dword, base + 0x60);
+
+	do {
+		dword = readl(base + 0x68);
+	} while ((dword & 3) != 2);
+
+	dword = readl(base + 0x64);
+
+	/* 2 */
+	printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
+	verb_size = find_verb(dword, &verb);
+
+	if (!verb_size) {
+		printk(BIOS_DEBUG, "No verb!\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "verb_size: %d\n", verb_size);
+	/* 3 */
+	for (i = 0; i < verb_size; i++) {
+		do {
+			dword = readl(base + 0x68);
+		} while (dword & 1);
+
+		writel(verb[i], base + 0x60);
+
+		do {
+			dword = readl(base + 0x68);
+		} while ((dword & 3) != 2);
+	}
+	printk(BIOS_DEBUG, "verb loaded!\n");
+}
+
+static void codecs_init(u8 * base, u32 codec_mask)
+{
+	int i;
+	for (i = 2; i >= 0; i--) {
+		if (codec_mask & (1 << i))
+			codec_init(base, i);
+	}
+}
+
+static void hda_init(struct device *dev)
+{
+	u8 *base;
+	struct resource *res;
+	u32 codec_mask;
+
+	/* SM Setting */
+	struct device * hda_dev;
+	hda_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	/* Set routing pin */
+	pci_write_config32(dev, 0xf8, 0x0);
+	pci_write_config8(dev, 0xfc, 0xAA);
+	/* Set INTA */
+	pci_write_config8(dev, 0x63, 0x0);
+	/* Enable azalia, disable ac97 */
+	pm_iowrite(0x59, 0xB);
+
+	res = find_resource(dev, 0x10);
+	if (!res)
+		return;
+
+	base = (u8 *) ((u32)res->base);
+	printk(BIOS_DEBUG, "base = %08x\n", base);
+	codec_mask = codec_detect(base);
+
+	if (codec_mask) {
+		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
+		codecs_init(base, codec_mask);
+	}
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+struct device_operations sb600_hda = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
+			      .device = PCI_DEVICE_ID_ATI_SB600_HDA}}},
+	.constructor		 = default_device_constructor,
+	.phase4_read_resources	 = pci_dev_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = pci_dev_enable_resources,
+	.phase6_init		 = hda_init,
+	.ops_pci          = &lops_pci
+};

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/hda.dts
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/hda.dts	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/hda.dts	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "sb600_hda";
+};

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/ide.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/ide.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/ide.c	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/pci.h>
+#include <msr.h>
+#include <legacy.h>
+#include <device/pci_ids.h>
+#include <statictree.h>
+#include <config.h>
+#include "sb600.h"
+
+static void ide_init(struct device *dev)
+{
+	struct southbridge_amd_sb600_ide_dts_config *conf;
+	/* Enable ide devices so the linux ide driver will work */
+	u32 dword;
+	u8 byte;
+	conf = dev->device_configuration;
+
+	/* RPR10.1 disable MSI */
+	dword = pci_read_config32(dev, 0x70);
+	dword &= ~(1 << 16);
+	pci_write_config32(dev, 0x70, dword);
+
+	/* Ultra DMA mode */
+	byte = pci_read_config8(dev, 0x54);
+	byte |= 1 << 0;
+	pci_write_config8(dev, 0x54, byte);
+	byte = pci_read_config8(dev, 0x56);
+	byte &= ~(7 << 0);
+	byte |= 5 << 0;		/* mode 5 */
+	pci_write_config8(dev, 0x56, byte);
+
+	/* Enable I/O Access&& Bus Master */
+	dword = pci_read_config16(dev, 0x4);
+	dword |= 1 << 2;
+	pci_write_config16(dev, 0x4, dword);
+
+#if CONFIG_PCI_ROM_RUN == 1
+	pci_dev_init(dev);
+#endif
+
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+struct device_operations sb600_ide = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
+			      .device = PCI_DEVICE_ID_ATI_SB600_IDE}}},
+	.constructor		 = default_device_constructor,
+	.phase4_read_resources	 = pci_dev_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = pci_dev_enable_resources,
+	.phase6_init		 = ide_init,
+	.ops_pci          = &lops_pci
+};

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/ide.dts
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/ide.dts	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/ide.dts	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "sb600_ide";
+	/* ignored in driver at present! */
+	ide0_enable = "0";
+	ide1_enable = "1";
+};

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/lpc.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/lpc.c	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/pci.h>
+#include <msr.h>
+#include <legacy.h>
+#include <device/pci_ids.h>
+#include <statictree.h>
+#include <config.h>
+#include "sb600.h"
+
+static void lpc_init(struct device * dev)
+{
+	u8 byte;
+	u32 dword;
+	struct device * sm_dev;
+
+	/* Enable the LPC Controller */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	dword = pci_read_config32(sm_dev, 0x64);
+	dword |= 1 << 20;
+	pci_write_config32(sm_dev, 0x64, dword);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+
+	/* RPR 7.2 Enable DMA transaction on the LPC bus */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 2);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR 7.3 Disable the timeout mechanism on LPC */
+	byte = pci_read_config8(dev, 0x48);
+	byte &= ~(1 << 7);
+	pci_write_config8(dev, 0x48, byte);
+
+	/* RPR 7.5 Disable LPC MSI Capability */
+	byte = pci_read_config8(dev, 0x78);
+	byte &= ~(1 << 1);
+	pci_write_config8(dev, 0x78, byte);
+
+}
+
+static void sb600_lpc_read_resources(struct device * dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);	/* We got one for APIC, or one more for TRAP */
+
+	pci_get_resource(dev, 0xA0); /* SPI ROM base address */
+
+	/* Add an extra subtractive resource for both memory and I/O */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->flags =
+	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->flags =
+	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+
+	compact_resources(dev);
+}
+
+/**     
+ * @brief Enable resources for children devices
+ *      
+ * @param dev the device whos children's resources are to be enabled
+ *      
+ * This function is call by the global enable_resources() indirectly via the
+ * device_operation::enable_resources() method of devices.
+ *      
+ * Indirect mutual recursion:
+ *      enable_childrens_resources() -> enable_resources()
+ *      enable_resources() -> device_operation::enable_resources()
+ *      device_operation::enable_resources() -> enable_children_resources()
+ */
+static void sb600_lpc_enable_childrens_resources(struct device * dev)
+{
+	u32 link;
+	u32 reg, reg_x;
+	int i;
+	int var_num = 0;
+	u16 reg_var[3];
+
+	reg = pci_read_config32(dev, 0x44);
+	reg_x = pci_read_config32(dev, 0x48);
+
+	for (link = 0; link < dev->links; link++) {
+		struct device * child;
+		for (child = dev->link[link].children; child;
+		     child = child->sibling) {
+			enable_resources(child);
+			if (child->have_resources
+			    && (child->path.type == DEVICE_PATH_PNP)) {
+				for (i = 0; i < child->resources; i++) {
+					struct resource *res;
+					unsigned long base, end;	/*  don't need long long */
+					res = &child->resource[i];
+					if (!(res->flags & IORESOURCE_IO))
+						continue;
+					base = res->base;
+					end = resource_end(res);
+					printk_debug
+					    ("sb600 lpc decode:%s, base=0x%08x, end=0x%08x\n",
+					     dev_path(child), base, end);
+					switch (base) {
+					case 0x60:	/*  KB */
+					case 0x64:	/*  MS */
+						reg |= (1 << 29);
+						break;
+					case 0x3f8:	/*  COM1 */
+						reg |= (1 << 6);
+						break;
+					case 0x2f8:	/*  COM2 */
+						reg |= (1 << 7);
+						break;
+					case 0x378:	/*  Parallal 1 */
+						reg |= (1 << 0);
+						break;
+					case 0x3f0:	/*  FD0 */
+						reg |= (1 << 26);
+						break;
+					case 0x220:	/*  Aduio 0 */
+						reg |= (1 << 8);
+						break;
+					case 0x300:	/*  Midi 0 */
+						reg |= (1 << 18);
+						break;
+					case 0x400:
+						reg_x |= (1 << 16);
+						break;
+					case 0x480:
+						reg_x |= (1 << 17);
+						break;
+					case 0x500:
+						reg_x |= (1 << 18);
+						break;
+					case 0x580:
+						reg_x |= (1 << 19);
+						break;
+					case 0x4700:
+						reg_x |= (1 << 22);
+						break;
+					case 0xfd60:
+						reg_x |= (1 << 23);
+						break;
+					      default:
+						if (var_num >= 3)
+							continue;	/* only 3 var ; compact them ? */
+						switch (var_num) {
+						case 0:
+							reg_x |= (1 << 2);
+							break;
+						case 1:
+							reg_x |= (1 << 24);
+							break;
+						case 2:
+							reg_x |= (1 << 25);
+							break;
+						}
+						reg_var[var_num++] =
+						    base & 0xffff;
+					}
+				}
+			}
+		}
+	}
+	pci_write_config32(dev, 0x44, reg);
+	pci_write_config32(dev, 0x48, reg_x);
+	switch (var_num) {
+	case 2:
+		pci_write_config16(dev, 0x90, reg_var[2]);
+	case 1:
+		pci_write_config16(dev, 0x66, reg_var[1]);
+	case 0:
+		pci_write_config16(dev, 0x64, reg_var[0]);
+		break;
+	}
+}
+
+static void sb600_lpc_enable_resources(struct device * dev)
+{
+	pci_dev_enable_resources(dev);
+	sb600_lpc_enable_childrens_resources(dev);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+struct device_operations sb600_lpc = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_AMD,
+			      .device = PCI_DEVICE_ID_AMD_8111_IDE}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan_bus	= scan_status_bus,
+	.phase4_read_resources	 = sb600_lpc_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = sb600_lpc_enable_resources,
+	.phase6_init		 = lpc_init,
+	.ops_pci          = &lops_pci
+};

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/lpc.dts
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/lpc.dts	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/lpc.dts	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "sb600_lpc";
+};

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/pci.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/pci.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/pci.c	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "sb600.h"
+
+static void pci_init(struct device *dev)
+{
+	u32 dword;
+	u16 word;
+	u8 byte;
+
+	/* RPR 4.1 Enables the PCI-bridge subtractive decode */
+	/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 7;
+	pci_write_config8(dev, 0x4B, byte);
+	byte = pci_read_config8(dev, 0x40);
+	byte |= 1 << 5;
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR4.2 PCI-bridge upstream dual address window */
+	/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
+	byte = pci_read_config8(dev, 0x50);
+	byte |= 1 << 0;
+	pci_write_config8(dev, 0x50, byte);
+
+	/* RPR 4.3 PCI bus 64-byte DMA read access */
+	/* Enhance the PCI bus DMA performance */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 4;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 4.4 Enables the PCIB writes to be cacheline aligned. */
+	/* The size of the writes will be set in the Cacheline Register */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= 1 << 1;
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR 4.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */
+	pci_write_config8(dev, 0x0D, 0x40);
+	pci_write_config8(dev, 0x1B, 0x40);
+
+	/* RPR 4.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 6;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 4.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 0;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 4.8 Adjusts the GNT# de-assertion time */
+	word = pci_read_config16(dev, 0x64);
+	word |= 1 << 12;
+	pci_write_config16(dev, 0x64, word);
+
+	/* RPR 4.9 Fast Back to Back transactions support */
+	byte = pci_read_config8(dev, 0x48);
+	byte |= 1 << 2;
+	pci_write_config8(dev, 0x48, byte);
+
+	/* RPR 4.10 Enable Lock Operation */
+	byte = pci_read_config8(dev, 0x48);
+	byte |= 1 << 3;
+	pci_write_config8(dev, 0x48, byte);
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 2);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR 4.11 Enable additional optional PCI clock */
+	word = pci_read_config16(dev, 0x64);
+	word |= 1 << 8;
+	pci_write_config16(dev, 0x64, word);
+
+	/* rpr4.12 Disable Fewer-Retry Mode for A11-A13 only. 0x64[5:4] clear */
+	byte = pci_read_config8(dev, 0x64);
+	byte &= 0xcf;
+	pci_write_config8(dev, 0x64, byte);
+
+	/* rpr4.14 Disabling Downstream Flush, for A12 only, 0x64[18]. */
+	dword = pci_read_config32(dev, 0x64);
+	dword |= (1 << 18);
+	pci_write_config32(dev, 0x64, dword);
+
+	/* RPR 4.13 Enable One-Prefetch-Channel Mode */
+	dword = pci_read_config32(dev, 0x64);
+	dword |= 1 << 20;
+	pci_write_config32(dev, 0x64, dword);
+
+	/* RPR 4.15 Disable PCIB MSI Capability */
+	byte = pci_read_config8(dev, 0x40);
+	byte &= ~(1 << 3);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* rpr4.16 Adjusting CLKRUN# */
+	dword = pci_read_config32(dev, 0x64);
+	dword |= (1 << 15);
+	pci_write_config32(dev, 0x64, dword);
+}
+
+struct device_operations amd8111_pci = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
+			      .device = PCI_DEVICE_ID_ATI_SB600_PCI}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = pci_scan_bridge,
+	.phase4_enable_disable           = amd8111_enable,
+	.phase4_read_resources	 = pci_bus_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = pci_bus_enable_resources,
+	.phase6_init		 = pci_init,
+	.reset_bus = pci_bus_reset,
+};

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/pci.dts
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/pci.dts	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/pci.dts	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "sb600_pci";
+};

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/sata.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sata.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sata.c	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,200 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/pci.h>
+#include <msr.h>
+#include <legacy.h>
+#include <device/pci_ids.h>
+#include <statictree.h>
+#include <config.h>
+#include "sb600.h"
+
+static void sata_init(struct device *dev)
+{
+	u8 byte;
+	u16 word;
+	u32 dword;
+	u8 *sata_bar5;
+	u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
+
+	struct southbridge_ati_sb600_sata_dts_config *conf;
+	conf = dev->device_configuration;
+
+	struct device * sm_dev;
+	/* SATA SMBus Disable */
+	/* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	/* Disable SATA SMBUS */
+	byte = pci_read_config8(sm_dev, 0xad);
+	byte |= (1 << 1);
+	/* Enable SATA and power saving */
+	byte = pci_read_config8(sm_dev, 0xad);
+	byte |= (1 << 0);
+	byte |= (1 << 5);
+	pci_write_config8(sm_dev, 0xad, byte);
+	/* Set the interrupt Mapping to INTG# */
+	byte = pci_read_config8(sm_dev, 0xaf);
+	byte = 0x6 << 2;
+	pci_write_config8(sm_dev, 0xaf, byte);
+
+	/* get base addresss */
+	sata_bar5 = (u8 *) (pci_read_config32(dev, 0x24) & ~0x3FF);
+	sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
+	sata_bar1 = pci_read_config16(dev, 0x14) & ~0x7;
+	sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
+	sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x7;
+	sata_bar4 = pci_read_config16(dev, 0x20) & ~0x7;
+
+	printk(BIOS_DEBUG, "sata_bar0=%x\n", sata_bar0);	/* 3030 */
+	printk(BIOS_DEBUG, "sata_bar1=%x\n", sata_bar1);	/* 3070 */
+	printk(BIOS_DEBUG, "sata_bar2=%x\n", sata_bar2);	/* 3040 */
+	printk(BIOS_DEBUG, "sata_bar3=%x\n", sata_bar3);	/* 3080 */
+	printk(BIOS_DEBUG, "sata_bar4=%x\n", sata_bar4);	/* 3000 */
+	printk(BIOS_DEBUG, "sata_bar5=%x\n", sata_bar5);	/* e0309000 */
+
+	/* Program the 2C to 0x43801002 */
+	dword = 0x43801002;
+	pci_write_config32(dev, 0x2c, dword);
+
+	/* SERR-Enable */
+	word = pci_read_config16(dev, 0x04);
+	word |= (1 << 8);
+	pci_write_config16(dev, 0x04, word);
+
+	/* Dynamic power saving */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 2);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* Set SATA Operation Mode, Set to IDE mode */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 0);
+	byte |= (1 << 4);
+	pci_write_config8(dev, 0x40, byte);
+
+	dword = 0x01018f00;
+	pci_write_config32(dev, 0x8, dword);
+
+	byte = pci_read_config8(dev, 0x40);
+	byte &= ~(1 << 0);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* Enable the SATA watchdog counter */
+	byte = pci_read_config8(dev, 0x44);
+	byte |= (1 << 0);
+	pci_write_config8(dev, 0x44, byte);
+
+	/* Program the watchdog counter to 0x10 */
+	byte = 0x10;
+	pci_write_config8(dev, 0x46, byte);
+
+	/* RPR6.5 Program the PHY Global Control to 0x2C00 for A13 */
+	word = 0x2c00;
+	pci_write_config16(dev, 0x86, word);
+
+	/* RPR6.5 Program the Phy Tuning4Ports */
+	dword = 0x00B401D6;
+	pci_write_config32(dev, 0x88, dword);
+	pci_write_config32(dev, 0x8c, dword);
+	pci_write_config32(dev, 0x90, dword);
+	pci_write_config32(dev, 0x94, dword);
+
+	byte = 0xB8;
+	pci_write_config8(dev, 0xA5, byte);
+	pci_write_config8(dev, 0xAD, byte);
+	pci_write_config8(dev, 0xB5, byte);
+	pci_write_config8(dev, 0xBD, byte);
+
+	/* RPR 6.8  */
+	word = pci_read_config16(dev, 0x42);
+	word |= 1 << 7;
+	pci_write_config16(dev, 0x42, word);
+	/* RPR 6.9  */
+	dword = pci_read_config32(dev, 0x40);
+	dword |= 1 << 25;
+	pci_write_config32(dev, 0x40, dword);
+
+	/* Enable the I/O ,MM ,BusMaster access for SATA */
+	byte = pci_read_config8(dev, 0x4);
+	byte |= 7 << 0;
+	pci_write_config8(dev, 0x4, byte);
+
+	/* RPR6.6 SATA drive detection. Currently we detect Primary Master Device only */
+	/* Use BAR5+0x1A8,BAR0+0x6 for Primary Slave */
+	/* Use BAR5+0x228,BAR0+0x6 for Secondary Master */
+	/* Use BAR5+0x2A8,BAR0+0x6 for Secondary Slave */
+
+	byte = readb(sata_bar5 + 0x128);
+	printk(BIOS_DEBUG, "byte=%x\n", byte);
+	byte &= 0xF;
+	if (byte == 0x3) {
+		outb(0xA0, sata_bar0 + 0x6);
+		while ((inb(sata_bar0 + 0x6) != 0xA0)
+		       || ((inb(sata_bar0 + 0x7) & 0x88) != 0)) {
+			mdelay(10);
+			printk(BIOS_DEBUG, "0x6=%x,0x7=%x\n", inb(sata_bar0 + 0x6),
+				     inb(sata_bar0 + 0x7));
+			printk(BIOS_DEBUG, "drive detection fail,trying...\n");
+		}
+		printk(BIOS_DEBUG, "Primary master device is ready\n");
+	} else {
+		printk(BIOS_DEBUG, "No Primary master SATA drive on Slot0\n");
+	}
+
+	/* Below is CIM InitSataLateFar */
+	/* Enable interrupts from the HBA  */
+	byte = readb(sata_bar5 + 0x4);
+	byte |= 1 << 1;
+	writeb(byte, (sata_bar5 + 0x4));
+
+	/* Clear error status */
+	writel(0xFFFFFFFF, (sata_bar5 + 0x130));
+	writel(0xFFFFFFFF, (sata_bar5 + 0x1b0));
+	writel(0xFFFFFFFF, (sata_bar5 + 0x230));
+	writel(0xFFFFFFFF, (sata_bar5 + 0x2b0));
+
+	/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
+	/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
+
+	/* word = 0x0000; */
+	/* word = pm_ioread(0x28); */
+	/* byte = pm_ioread(0x29); */
+	/* word |= byte<<8; */
+	/* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */
+	/* writel(0x80000000 , word); */
+}
+
+static struct pci_operations lops_pci = {
+	/* .set_subsystem = pci_dev_set_subsystem, */
+};
+
+struct device_operations amd8111_ide = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
+			      .device = PCI_DEVICE_ID_ATI_SB600_SATA}}},
+	.constructor		 = default_device_constructor,
+	.phase4_read_resources	 = pci_dev_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = pci_dev_enable_resources,
+	.phase6_init		 = sata_init,
+	.ops_pci          = &lops_pci
+};
\ No newline at end of file

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/sata.dts
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sata.dts	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sata.dts	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "sb600_sata";
+};

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.c	2008-10-02 01:35:03 UTC (rev 3629)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.c	2008-10-02 15:42:14 UTC (rev 3630)
@@ -17,19 +17,20 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <console/console.h>
-
-#include <arch/io.h>
-
-#include <device/device.h>
+#include <types.h>
+#include <lib.h>
+#include <console.h>
 #include <device/pci.h>
+#include <msr.h>
+#include <legacy.h>
 #include <device/pci_ids.h>
-#include <device/pci_ops.h>
+#include <statictree.h>
+#include <config.h>
 #include "sb600.h"
 
-static device_t find_sm_dev(device_t dev, u32 devfn)
+static struct device * find_sm_dev(struct device * dev, u32 devfn)
 {
-	device_t sm_dev;
+	struct device * sm_dev;
 
 	sm_dev = dev_find_slot(dev->bus->secondary, devfn);
 	if (!sm_dev)
@@ -49,7 +50,7 @@
 	return sm_dev;
 }
 
-void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val)
+void set_sm_enable_bits(struct device * sm_dev, u32 reg_pos, u32 mask, u32 val)
 {
 	u32 reg_old, reg;
 	reg = reg_old = pci_read_config32(sm_dev, reg_pos);
@@ -96,7 +97,7 @@
 	return pmio_read_index(port_base, reg);
 }
 
-static void set_pmio_enable_bits(device_t sm_dev, u32 reg_pos,
+static void set_pmio_enable_bits(struct device * sm_dev, u32 reg_pos,
 				 u32 mask, u32 val)
 {
 	u8 reg_old, reg;
@@ -108,10 +109,10 @@
 	}
 }
 
-void sb600_enable(device_t dev)
+void sb600_enable(struct device * dev)
 {
-	device_t sm_dev = 0;
-	device_t bus_dev = 0;
+	struct device * sm_dev = 0;
+	struct device * bus_dev = 0;
 	int index = -1;
 	u32 deviceid;
 	u32 vendorid;
@@ -122,7 +123,7 @@
 
 	u32 devfn;
 
-	printk_debug("sb600_enable()\n");
+	printk(BIOS_DEBUG, "sb600_enable()\n");
 
 /*
 *	0:12.0  SATA	bit 8 of sm_dev 0xac : 1 - enable, default         + 32 * 3
@@ -150,13 +151,13 @@
 	bus_dev = dev->bus->dev;
 	if ((bus_dev->vendor == PCI_VENDOR_ID_ATI) &&
 	    (bus_dev->device == PCI_DEVICE_ID_ATI_SB600_PCI)) {
-		devfn = (bus_dev->path.u.pci.devfn) & ~7;
+		devfn = (bus_dev->path.pci.devfn) & ~7;
 		sm_dev = find_sm_dev(bus_dev, devfn);
 		if (!sm_dev)
 			return;
 
 		/* something under 00:01.0 */
-		switch (dev->path.u.pci.devfn) {
+		switch (dev->path.pci.devfn) {
 		case 5 << 3:
 			;
 		}
@@ -164,7 +165,7 @@
 		return;
 	}
 
-	i = (dev->path.u.pci.devfn) & ~7;
+	i = (dev->path.pci.devfn) & ~7;
 	i += (2 << 3);
 	for (devfn = (0x14 << 3); devfn <= i; devfn += (1 << 3)) {
 		sm_dev = find_sm_dev(dev, devfn);
@@ -174,7 +175,7 @@
 	if (!sm_dev)
 		return;
 
-	switch (dev->path.u.pci.devfn - (devfn - (0x14 << 3))) {
+	switch (dev->path.pci.devfn - (devfn - (0x14 << 3))) {
 	case (0x12 << 3) | 0:
 		index = 8;
 		set_sm_enable_bits(sm_dev, 0xac, 1 << index,
@@ -187,7 +188,7 @@
 	case (0x13 << 3) | 3:
 	case (0x13 << 3) | 4:
 	case (0x13 << 3) | 5:
-		index = dev->path.u.pci.devfn & 7;
+		index = dev->path.pci.devfn & 7;
 		index++;
 		index %= 6;
 		set_sm_enable_bits(sm_dev, 0x68, 1 << index,
@@ -217,19 +218,27 @@
 		break;
 	case (0x14 << 3) | 5:
 	case (0x14 << 3) | 6:
-		index = dev->path.u.pci.devfn & 7;
+		index = dev->path.pci.devfn & 7;
 		index -= 5;
 		set_pmio_enable_bits(sm_dev, 0x59, 1 << index,
 				     (dev->enabled ? 0 : 1) << index);
 		index += 32 * 4;
 		break;
 	default:
-		printk_debug("unknown dev: %s deviceid=%4x\n", dev_path(dev),
+		printk(BIOS_DEBUG, "unknown dev: %s deviceid=%4x\n", dev_path(dev),
 			     deviceid);
 	}
 }
 
-struct chip_operations southbridge_amd_sb600_ops = {
-	CHIP_NAME("ATI SB600")
-	.enable_dev = sb600_enable,
+struct device_operations sb600 = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_AMD,
+			      .device = xz}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = 0,
+	.phase4_enable_disable           = sb600_enable,
+	.phase4_read_resources	 = pci_dev_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase6_init		 = NULL,
+	.ops_pci		 = &pci_dev_ops_pci,
 };

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.dts
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.dts	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.dts	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "sb600";
+};

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.h	2008-10-02 01:35:03 UTC (rev 3629)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.h	2008-10-02 15:42:14 UTC (rev 3630)
@@ -20,8 +20,6 @@
 #ifndef SB600_H
 #define SB600_H
 
-#include "chip.h"
-
 #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D
 #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380
 #define PCI_DEVICE_ID_ATI_SB600_IDE 0x438C
@@ -36,6 +34,7 @@
 #define PCI_DEVICE_ID_ATI_SB600_USB_2 0x4389
 #define PCI_DEVICE_ID_ATI_SB600_USB_3 0x438A
 #define PCI_DEVICE_ID_ATI_SB600_USB_4 0x438B
+
 extern void pm_iowrite(u8 reg, u8 value);
 extern u8 pm_ioread(u8 reg);
 extern void pm2_iowrite(u8 reg, u8 value);

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/sm.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sm.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sm.c	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,387 @@
+/* This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/pci.h>
+#include <msr.h>
+#include <legacy.h>
+#include <device/pci_ids.h>
+#include <statictree.h>
+#include <config.h>
+#include "sb600.h"
+#include "sb600_smbus.c"
+
+#define NMI_OFF 0
+
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON 1
+
+#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+struct ioapicreg {
+	unsigned int reg;
+	unsigned int value_low, value_high;
+};
+
+static struct ioapicreg ioapicregvalues[] = {
+#define ALL		(0xff << 24)
+#define NONE		(0)
+#define DISABLED	(1 << 16)
+#define ENABLED		(0 << 16)
+#define TRIGGER_EDGE	(0 << 15)
+#define TRIGGER_LEVEL	(1 << 15)
+#define POLARITY_HIGH	(0 << 13)
+#define POLARITY_LOW	(1 << 13)
+#define PHYSICAL_DEST	(0 << 11)
+#define LOGICAL_DEST	(1 << 11)
+#define ExtINT		(7 << 8)
+#define NMI		(4 << 8)
+#define SMI		(2 << 8)
+#define INT		(1 << 8)
+	/* IO-APIC virtual wire mode configuration */
+	/* mask, trigger, polarity, destination, delivery, vector */
+	{0, DISABLED, NONE},
+	{1, DISABLED, NONE},
+	{2, DISABLED, NONE},
+	{3, DISABLED, NONE},
+	{4, DISABLED, NONE},
+	{5, DISABLED, NONE},
+	{6, DISABLED, NONE},
+	{7, DISABLED, NONE},
+	{8, DISABLED, NONE},
+	{9, DISABLED, NONE},
+	{10, DISABLED, NONE},
+	{11, DISABLED, NONE},
+	{12, DISABLED, NONE},
+	{13, DISABLED, NONE},
+	{14, DISABLED, NONE},
+	{15, DISABLED, NONE},
+	{16, DISABLED, NONE},
+	{17, DISABLED, NONE},
+	{18, DISABLED, NONE},
+	{19, DISABLED, NONE},
+	{20, DISABLED, NONE},
+	{21, DISABLED, NONE},
+	{22, DISABLED, NONE},
+	{23, DISABLED, NONE},
+	/* Be careful and don't write past the end... */
+};
+
+static void setup_ioapic(unsigned long ioapic_base)
+{
+	int i;
+	unsigned long value_low, value_high;
+	volatile unsigned long *l;
+	struct ioapicreg *a = ioapicregvalues;
+
+	ioapicregvalues[0].value_high = lapicid() << (56 - 32);
+
+	printk(BIOS_DEBUG, "lapicid = %016x\n", ioapicregvalues[0].value_high);
+
+	l = (unsigned long *)ioapic_base;
+
+	for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
+	     i++, a++) {
+		l[0] = (a->reg * 2) + 0x10;
+		l[4] = a->value_low;
+		value_low = l[4];
+		l[0] = (a->reg * 2) + 0x11;
+		l[4] = a->value_high;
+		value_high = l[4];
+		if ((i == 0) && (value_low == 0xffffffff)) {
+			printk_warning("IO APIC not responding.\n");
+			return;
+		}
+	}
+}
+
+/*
+* SB600 enables all USB controllers by default in SMBUS Control.
+* SB600 enables SATA by default in SMBUS Control.
+*/
+static void sm_init(struct device * dev)
+{
+	u8 byte;
+	u8 byte_old;
+	u32 dword;
+	unsigned long ioapic_base;
+	int on;
+	int nmi_option;
+
+	printk(BIOS_INFO, "sm_init().\n");
+
+	ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0);	/* some like mem resource, but does not have  enable bit */
+	setup_ioapic(ioapic_base);
+
+	dword = pci_read_config8(dev, 0x62);
+	dword |= 1 << 2;
+	pci_write_config8(dev, 0x62, dword);
+
+	dword = pci_read_config32(dev, 0x78);
+	dword |= 1 << 9;
+	pci_write_config32(dev, 0x78, dword);	/* enable 0xCD6 0xCD7 */
+
+	/* enable serial irq */
+	byte = pci_read_config8(dev, 0x69);
+	byte |= 1 << 7;		/* enable serial irq function */
+	byte &= ~(0xF << 2);
+	byte |= 4 << 2;		/* set NumSerIrqBits=4 */
+	pci_write_config8(dev, 0x69, byte);
+
+	byte = pm_ioread(0x61);
+	byte |= 1 << 1;		/* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
+	pm_iowrite(0x61, byte);
+
+	/* disable SMI */
+	byte = pm_ioread(0x53);
+	byte |= 1 << 3;
+	pm_iowrite(0x53, byte);
+
+	/* power after power fail */
+	on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	get_option(&on, "power_on_after_fail");
+	byte = pm_ioread(0x74);
+	byte &= ~0x03;
+	if (on) {
+		byte |= 2;
+	}
+	byte |= 1 << 2;
+	pm_iowrite(0x74, byte);
+	printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
+
+	/* sb600 rpr:2.3.3: */
+	byte = pm_ioread(0x9A);
+	byte |= 1 << 5 | 1 << 4 | 1 << 2;
+	pm_iowrite(0x9A, byte);
+
+	byte = pm_ioread(0x8F);
+	byte |= 1 << 5;
+	byte &= ~(1 << 4);
+	pm_iowrite(0x8F, byte);
+
+	pm_iowrite(0x8B, 0x01);
+	pm_iowrite(0x8A, 0x90);
+	pm_iowrite(0x88, 0x10);	/* A21 */
+
+	byte = pm_ioread(0x7C);
+	byte |= 1 << 0;
+	pm_iowrite(0x7C, byte);
+
+	byte = pm_ioread(0x68);
+	byte &= ~(1 << 1);
+	pm_iowrite(0x68, byte);
+
+	byte = pm_ioread(0x8D);
+	byte &= ~(1 << 6);
+	pm_iowrite(0x8D, byte);
+
+	byte = pm_ioread(0x61);
+	byte &= ~(1 << 2);
+	pm_iowrite(0x61, byte);
+
+	byte = pm_ioread(0x42);
+	byte &= ~(1 << 2);
+	pm_iowrite(0x42, byte);
+
+	/* Set up NMI on errors */
+	byte = inb(0x70);	/* RTC70 */
+	byte_old = byte;
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if (nmi_option) {
+		byte &= ~(1 << 7);	/* set NMI */
+		printk(BIOS_INFO, "++++++++++set NMI+++++\n");
+	} else {
+		byte |= (1 << 7);	/* Can not mask NMI from PCI-E and NMI_NOW */
+		printk(BIOS_INFO, "++++++++++no set NMI+++++\n");
+	}
+	byte &= ~(1 << 7);
+	if (byte != byte_old) {
+		outb(byte, 0x70);
+	}
+
+	/* 2.10 IO Trap Settings */
+	abcfg_reg(0x10090, 1 << 16, 1 << 16);
+
+	/* ab index */
+	pci_write_config32(dev, 0xF0, AB_INDX);
+	/* Initialize the real time clock */
+	rtc_init(0);
+
+	/*3.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
+	abcfg_reg(0x10060, 9 << 17, 9 << 17);
+	abcfg_reg(0x10064, 9 << 17, 9 << 17);
+
+	/* 3.5 Enabling OHCI Prefetch for Performance Enhancement */
+	abcfg_reg(0x80, 1 << 0, 1<< 0);
+
+	/* 3.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */
+	/* 3.7 Enabling Additional Address Bits Checking in Downstream */
+	abcfg_reg(0x9c, 3 << 0, 3 << 0);
+
+	/* 3.8 Set B-Link Prefetch Mode */
+	abcfg_reg(0x80, 3 << 17, 3 << 17);
+
+	/* 3.9 Enabling Detection of Upstream Interrupts */
+	abcfg_reg(0x94, 1 << 20,1 << 20);
+
+	/* 3.10: Enabling Downstream Posted Transactions to Pass Non-Posted
+	 *  Transactions for the K8 Platform (for All Revisions) */
+	abcfg_reg(0x10090, 1 << 8, 1 << 8);
+
+	/* 3.11:Programming Cycle Delay for AB and BIF Clock Gating */
+	/* 3.12: Enabling AB and BIF Clock Gating */
+	abcfg_reg(0x10054, 0xFFFF0000, 0x1040000);
+	abcfg_reg(0x54, 0xFF << 16, 4 << 16);
+	printk(BIOS_INFO, "3.11, ABCFG:0x54\n");
+	abcfg_reg(0x54, 1 << 24, 1 << 24);
+	printk(BIOS_INFO, "3.12, ABCFG:0x54\n");
+	abcfg_reg(0x98, 0x0000FF00, 0x00004700);
+
+	/* 3.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */
+	abcfg_reg(0x10054, 0x0000FFFF, 0x07FF);
+
+	/* 3.14:Enabling L1 on A-link Express */
+	axcfg_reg(0x68, 0x00000003, 0x2);
+	axindxp_reg(0xa0, 0x0000F000, 0x6000);
+
+	abcfg_reg(0x10098, 0xFFFFFFFF, 0x4000);
+	abcfg_reg(0x04, 0xFFFFFFFF, 0x6);
+	printk(BIOS_INFO, "sm_init() end\n");
+
+	/* Enable NbSb virtual channel */
+	axcfg_reg(0x114, 0x3f << 1, 0 << 1);
+	axcfg_reg(0x120, 0x7f << 1, 0x7f << 1);
+	axcfg_reg(0x120, 7 << 24, 1 << 24);
+	axcfg_reg(0x120, 1 << 31, 1 << 31);
+	abcfg_reg(0x50, 1 << 3, 1 << 3);
+}
+
+static int lsmbus_recv_byte(struct device * dev)
+{
+	u32 device;
+	struct resource *res;
+	struct bus *pbus;
+
+	device = dev->path.i2c.device;
+	pbus = get_pbus_smbus(dev);
+
+	res = find_resource(pbus->dev, 0x10);
+
+	return do_smbus_recv_byte(res->base, device);
+}
+
+static int lsmbus_send_byte(struct device * dev, u8 val)
+{
+	u32 device;
+	struct resource *res;
+	struct bus *pbus;
+
+	device = dev->path.i2c.device;
+	pbus = get_pbus_smbus(dev);
+
+	res = find_resource(pbus->dev, 0x10);
+
+	return do_smbus_send_byte(res->base, device, val);
+}
+
+static int lsmbus_read_byte(struct device * dev, u8 address)
+{
+	u32 device;
+	struct resource *res;
+	struct bus *pbus;
+
+	device = dev->path.i2c.device;
+	pbus = get_pbus_smbus(dev);
+
+	res = find_resource(pbus->dev, 0x10);
+
+	return do_smbus_read_byte(res->base, device, address);
+}
+
+static int lsmbus_write_byte(struct device * dev, u8 address, u8 val)
+{
+	u32 device;
+	struct resource *res;
+	struct bus *pbus;
+
+	device = dev->path.i2c.device;
+	pbus = get_pbus_smbus(dev);
+
+	res = find_resource(pbus->dev, 0x10);
+
+	return do_smbus_write_byte(res->base, device, address, val);
+}
+static struct smbus_bus_operations lops_smbus_bus = {
+	.recv_byte = lsmbus_recv_byte,
+	.send_byte = lsmbus_send_byte,
+	.read_byte = lsmbus_read_byte,
+	.write_byte = lsmbus_write_byte,
+};
+
+static void sb600_sm_read_resources(struct device * dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+
+	/* apic */
+	res = new_resource(dev, 0x74);
+	res->base  = 0xfec00000;
+	res->size = 256 * 0x10;
+	res->limit = 0xFFFFFFFFUL;	/* res->base + res->size -1; */
+	res->align = 8;
+	res->gran = 8;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
+
+	/* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */
+
+	compact_resources(dev);
+
+}
+static void sb600_sm_set_resources(struct device *dev)
+{
+	struct resource *res;
+
+	pci_dev_set_resources(dev);
+
+	res = find_resource(dev, 0x74);
+	pci_write_config32(dev, 0x74, res->base | 1 << 3);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+struct device_operations sb600_sm = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
+			      .device = PCI_DEVICE_ID_ATI_SB600_SM}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = 0,
+	.phase4_read_resources	 = sb600_sm_read_resources,
+	.phase4_set_resources	 = sb600_sm_set_resources,
+	.phase5_enable_resources = pci_dev_enable_resources,
+	.phase6_init		 = sm_init,
+	.ops_pci          = &lops_pci
+	.ops_smbus_bus = &lops_smbus_bus,
+};
\ No newline at end of file

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/sm.dts
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sm.dts	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sm.dts	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "sb600_sm";
+};

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/stage1.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/stage1.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/stage1.c	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,640 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/pci.h>
+#include <msr.h>
+#include <legacy.h>
+#include <device/pci.h>
+#include <statictree.h>
+#include <config.h>
+#include <io.h>
+BORKED
+#define SMBUS_IO_BASE 0x1000	/* Is it a temporary SMBus I/O base address? */
+	 /*SIZE 0x40 */
+
+/* Get SB ASIC Revision.*/
+static u8 get_sb600_revision()
+{
+	u32 dev;
+	pci_conf1_find_device(0x1002,  0x4385, &dev);
+
+	if (dev == PCI_DEV_INVALID) {
+		die("SMBUS controller not found\r\n");
+	}
+	return pci_conf1_read_config8(dev, 0x08);
+}
+
+
+/***************************************
+* Legacy devices are mapped to LPC space.
+*	serial port 0
+*	KBC Port
+*	ACPI Micro-controller port
+*	LPC ROM size,
+* NOTE: Call me ASAP, because I will reset LPC ROM size!
+***************************************/
+static void sb600_lpc_init(void)
+{
+	u8 reg8;
+	u32 reg32;
+	u32 dev;
+
+	/* Enable lpc controller */
+	pci_conf1_find_device(0x1002,  0x4385, &dev);	/* SMBUS controller */
+	reg32 = pci_conf1_read_config32(dev, 0x64);
+	reg32 |= 0x00100000;
+	pci_conf1_write_config32(dev, 0x64, reg32);
+
+	pci_conf1_find_device(0x1002,  0x438d, &dev);	/* LPC Controller */
+	/* Serial 0 */
+	reg8 = pci_conf1_read_config8(dev, 0x44);
+	reg8 |= (1 << 6);
+	pci_conf1_write_config8(dev, 0x44, reg8);
+
+	/* PS/2 keyboard, ACPI */
+	reg8 = pci_conf1_read_config8(dev, 0x47);
+	reg8 |= (1 << 5) | (1 << 6);
+	pci_conf1_write_config8(dev, 0x47, reg8);
+
+	/* SuperIO, LPC ROM */
+	reg8 = pci_conf1_read_config8(dev, 0x48);
+	reg8 |= (1 << 1) | (1 << 0);	/* enable Super IO config port 2e-2h, 4e-4f */
+	reg8 |= (1 << 3) | (1 << 4);	/* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF  */
+	reg8 |= 1 << 6;		/* enable for RTC I/O range */
+	pci_conf1_write_config8(dev, 0x48, reg8);
+
+	/* hardware should enable LPC ROM by pin strapes */
+	/*  rom access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */
+	/* See detail in BDG-215SB600-03.pdf page 15. */
+	pci_conf1_write_config16(dev, 0x68, 0x000e);	/* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; */
+	pci_conf1_write_config16(dev, 0x6c, 0xfff0);	/* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB  */
+}
+
+/* what is its usage? */
+static u32 get_sbdn(u32 bus)
+{
+	u32 dev;
+
+	/* Find the device. */
+	pci_conf1_find_on_bus(bus, 0x1002, 0x4385, &dev);
+	return (dev >> 15) & 0x1f;
+}
+
+
+static u8 dual_core()
+{
+	if(((cpuid_eax(0x80000000) & ~0xff) >= 8)) {
+		if(cpuid_ecx(0x80000008) & 1)
+			return 1;
+	}
+	return 0;
+}
+
+/*
+SB600 VFSMAF (VID/FID System Management Action Field)  is 010b by default.
+RPR 2.3.3 C-state and VID/FID change for the K8 platform.
+*/
+static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
+{
+	u8 byte;
+	byte = pmio_read(0x9a);
+	byte &= ~0x34;
+	if(dual_core())
+		byte |= 0x34;
+	else
+		byte |= 0x04;
+	pmio_write(0x9a, byte);
+
+	byte = pmio_read(0x8f);
+	byte &= ~0x30;
+	byte |= 0x20;
+	pmio_write(0x8f, byte);
+
+	pmio_write(0x8b, 0x01);
+	pmio_write(0x8a, 0x90);
+
+	if(get_sb600_revision() > 0x13)
+		pmio_write(0x88, 0x10);
+	else
+		pmio_write(0x88, 0x06);
+
+	byte = pmio_read(0x7c);
+	byte &= ~0x01;
+	byte |= 0x01;
+	pmio_write(0x7c, byte);
+
+	/*Must be 0 for K8 platform.*/
+	byte = pmio_read(0x68);
+	byte &= ~0x01;
+	pmio_write(0x68, byte);
+	/*Must be 0 for K8 platform.*/
+	byte = pmio_read(0x8d);
+	byte &= ~(1<<6);
+	pmio_write(0x8d, byte);
+
+	byte = pmio_read(0x61);
+	byte &= ~0x04;
+	pmio_write(0x61, byte);
+
+	byte = pmio_read(0x42);
+	byte &= ~0x04;
+	pmio_write(0x42, byte);
+
+	if(get_sb600_revision() == 0x14) {
+		pmio_write(0x89, 0x10);
+
+		byte = pmio_read(0x52);
+		byte |= 0x80;
+		pmio_write(0x52, byte);
+	}
+}
+
+
+static void hard_reset(void)
+{
+	set_bios_reset();
+
+	/* full reset */
+	outb(0x0a, 0x0cf9);
+	outb(0x0e, 0x0cf9);
+}
+
+static void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
+
+
+static void sb600_pci_port80()
+{
+	u8 byte;
+	u32 dev;
+
+	/* P2P Bridge */
+	pci_conf1_find_device(0x1002,  0x4384, &dev);
+
+	byte = pci_conf1_read_config8(dev, 0x40);
+	byte |= 1 << 5;
+	pci_conf1_write_config8(dev, 0x40, byte);
+
+	byte = pci_conf1_read_config8(dev, 0x4B);
+	byte |= 1 << 7;
+	pci_conf1_write_config8(dev, 0x4B, byte);
+
+	byte = pci_conf1_read_config8(dev, 0x1C);
+	byte |= 0xF << 4;
+	pci_conf1_write_config8(dev, 0x1C, byte);
+
+	byte = pci_conf1_read_config8(dev, 0x1D);
+	byte |= 0xF << 4;
+	pci_conf1_write_config8(dev, 0x1D, byte);
+
+	byte = pci_conf1_read_config8(dev, 0x04);
+	byte |= 1 << 0;
+	pci_conf1_write_config8(dev, 0x04, byte);
+
+	pci_conf1_find_device(0x1002,  0x438D, &dev);
+
+	byte = pci_conf1_read_config8(dev, 0x4A);
+	byte &= ~(1 << 5);	/* disable lpc port 80 */
+	pci_conf1_write_config8(dev, 0x4A, byte);
+}
+
+static void sb600_lpc_port80(void)
+{
+	u8 byte;
+	u32 dev;
+	u32 reg32;
+
+	/* enable lpc controller */
+	pci_conf1_find_device(0x1002,  0x4385, &dev);
+	reg32 = pci_conf1_read_config32(dev, 0x64);
+	reg32 |= 0x00100000;	/* lpcEnable */
+	pci_conf1_write_config32(dev, 0x64, reg32);
+
+	/* enable prot80 LPC decode in pci function 3 configuration space. */
+	pci_conf1_find_device(0x1002,  0x438d, &dev);
+	byte = pci_conf1_read_config8(dev, 0x4a);
+	byte |= 1 << 5;		/* enable port 80 */
+	pci_conf1_write_config8(dev, 0x4a, byte);
+}
+
+
+/* sbDevicesPorInitTable */
+static void sb600_devices_por_init()
+{
+	u32 dev;
+	u8 byte;
+
+	printk(BIOS_INFO, "sb600_devices_por_init()\n");
+	/* SMBus Device, BDF:0-20-0 */
+	printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n");
+	pci_conf1_find_device(0x1002,  0x4385, &dev);
+
+	if (dev == PCI_DEV_INVALID) {
+		die("SMBUS controller not found\r\n");
+	}
+	printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\r\n",
+		    get_sb600_revision());
+
+	/* sbPorAtStartOfTblCfg */
+	/* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
+	 * This is an I/O address. The I/O address must be on 16-byte boundry.  */
+	pci_conf1_write_config32(dev, 0xf0, AB_INDX);
+
+	/* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
+	/*Enables the SB600 to send transactions upstream over A-Link Express interface. */
+	axcfg_reg(0x04, 1 << 2, 1 << 2);
+	axindxc_reg(0x21, 0xff, 0);
+
+	/* 2.3.5:Enabling Non-Posted Memory Write for the K8 Platform */
+	axindxc_reg(0x10, 1 << 9, 1 << 9);
+	/* END of sbPorAtStartOfTblCfg */
+
+	/* sbDevicesPorInitTables */
+	/* set smbus iobase */
+	pci_conf1_write_config32(dev, 0x10, SMBUS_IO_BASE | 1);
+
+	/* enable smbus controller interface */
+	byte = pci_conf1_read_config8(dev, 0xd2);
+	byte |= (1 << 0);
+	pci_conf1_write_config8(dev, 0xd2, byte);
+
+	/* set smbus 1, ASF 2.0 (Alert Standard Format), iobase */
+	pci_conf1_write_config16(dev, 0x58, SMBUS_IO_BASE | 0x11);
+
+	/* TODO: I don't know the useage of followed two lines. I copied them from CIM. */
+	pci_conf1_write_config8(dev, 0x0a, 0x1);
+	pci_conf1_write_config8(dev, 0x0b, 0x6);
+
+	/* KB2RstEnable */
+	pci_conf1_write_config8(dev, 0x40, 0xd4);
+
+	/* Enable ISA Address 0-960K decoding */
+	pci_conf1_write_config8(dev, 0x48, 0x0f);
+
+	/* Enable ISA  Address 0xC0000-0xDFFFF decode */
+	pci_conf1_write_config8(dev, 0x49, 0xff);
+
+	/* Enable decode cycles to IO C50, C51, C52 GPM controls. */
+	byte = pci_conf1_read_config8(dev, 0x41);
+	byte &= 0x80;
+	byte |= 0x33;
+	pci_conf1_write_config8(dev, 0x41, byte);
+
+	/* Legacy DMA Prefetch Enhancement, CIM masked it. */
+	/* pci_conf1_write_config8(dev, 0x43, 0x1); */
+
+	/* Disabling Legacy USB Fast SMI# */
+	byte = pci_conf1_read_config8(dev, 0x62);
+	byte |= 0x24;
+	pci_conf1_write_config8(dev, 0x62, byte);
+
+	/* Features Enable */
+	pci_conf1_write_config32(dev, 0x64, 0x829E79BF);
+
+	/* SerialIrq Control */
+	pci_conf1_write_config8(dev, 0x69, 0x90);
+
+	/* Test Mode, PCIB_SReset_En Mask is set. */
+	pci_conf1_write_config8(dev, 0x6c, 0x20);
+
+	/* IO Address Enable, CIM set 0x78 only and masked 0x79. */
+	/*pci_conf1_write_config8(dev, 0x79, 0x4F); */
+	pci_conf1_write_config8(dev, 0x78, 0xFF);
+
+	/* This register is not used on sb600. It came from older chipset. */
+	/*pci_conf1_write_config8(dev, 0x95, 0xFF); */
+
+	/* Set smbus iospace enable, I don't know why write 0x04 into reg5 that is reserved */
+	pci_conf1_write_config16(dev, 0x4, 0x0407);
+
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+
+	/* IDE Device, BDF:0-20-1 */
+	printk(BIOS_INFO, "sb600_devices_por_init(): IDE Device, BDF:0-20-1\n");
+	pci_conf1_find_device(0x1002,  0x438C, &dev);
+	/* Disable prefetch */
+	byte = pci_conf1_read_config8(dev, 0x63);
+	byte |= 0x1;
+	pci_conf1_write_config8(dev, 0x63, byte);
+
+	/* LPC Device, BDF:0-20-3 */
+	printk(BIOS_INFO, "sb600_devices_por_init(): LPC Device, BDF:0-20-3\n");
+	pci_conf1_find_device(0x1002,  0x438D, &dev);
+	/* DMA enable */
+	pci_conf1_write_config8(dev, 0x40, 0x04);
+
+	/* IO Port Decode Enable */
+	pci_conf1_write_config8(dev, 0x44, 0xFF);
+	pci_conf1_write_config8(dev, 0x45, 0xFF);
+	pci_conf1_write_config8(dev, 0x46, 0xC3);
+	pci_conf1_write_config8(dev, 0x47, 0xFF);
+
+	/* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
+	 *  Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f),
+	 * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65).
+	 * Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/
+	byte = pci_conf1_read_config8(dev, 0x48);
+	byte |= (1 << 1) | (1 << 0);	/* enable Super IO config port 2e-2h, 4e-4f */
+	byte |= (1 << 3) | (1 << 4);	/* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */
+	byte |= 1 << 6;		/* enable for RTC I/O range */
+	pci_conf1_write_config8(dev, 0x48, byte);
+	pci_conf1_write_config8(dev, 0x49, 0xFF);
+	/* Enable 0x480-0x4bf, 0x4700-0x470B */
+	byte = pci_conf1_read_config8(dev, 0x4A);
+	byte |= ((1 << 1) + (1 << 6));	/*0x42, save the configuraion for port 0x80. */
+	pci_conf1_write_config8(dev, 0x4A, byte);
+
+	/* Set LPC ROM size, it has been done in sb600_lpc_init(). 
+	 * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
+	 * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB
+	 * pci_conf1_write_config16(dev, 0x68, 0x000e)
+	 * pci_conf1_write_config16(dev, 0x6c, 0xfff0);*/
+
+	/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
+	pci_conf1_write_config8(dev, 0x7C, 0x05);
+
+	/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, 
+	 * TODO: I don't know what are their mean? */
+	printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
+	pci_conf1_find_device(0x1002,  0x4384, &dev);
+	/* I don't know why CIM tried to write into a read-only reg! */
+	/*pci_conf1_write_config8(dev, 0x0c, 0x20) */ ;
+
+	/* Arbiter enable. */
+	pci_conf1_write_config8(dev, 0x43, 0xff);
+
+	/* Set PCDMA request into hight priority list. */
+	/* pci_conf1_write_config8(dev, 0x49, 0x1) */ ;
+
+	pci_conf1_write_config8(dev, 0x40, 0x26);
+
+	/* I don't know why CIM set reg0x1c as 0x11. 
+	 * System will block at sdram_initialize() if I set it before call sdram_initialize().
+	 * If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize().
+	 * pci_conf1_write_config8(dev, 0x1c, 0x11);
+	 * pci_conf1_write_config8(dev, 0x1d, 0x11);*/
+
+	/*CIM set this register; but I didn't find its description in RPR.
+	On DBM690T platform, I didn't find different between set and skip this register.
+	But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed
+	after the bit0 of this register is set.
+	pci_conf1_write_config8(dev, 0x04, 0x21);
+	*/
+	pci_conf1_write_config8(dev, 0x0d, 0x40);
+	pci_conf1_write_config8(dev, 0x1b, 0x40);
+	/* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
+	pci_conf1_write_config8(dev, 0x50, 0x01);
+
+	/* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
+	printk(BIOS_INFO, "sb600_devices_por_init(): SATA Device, BDF:0-18-0\n");
+	pci_conf1_find_device(0x1002,  0x4380, &dev);
+
+	/*PHY Global Control, we are using A14.
+	 * default:  0x2c40 for ASIC revision A12 and below
+	 *      0x2c00 for ASIC revision A13 and above.*/
+	pci_conf1_write_config16(dev, 0x86, 0x2C00);
+
+	/* PHY Port0-3 Control */
+	pci_conf1_write_config32(dev, 0x88, 0xB400DA);
+	pci_conf1_write_config32(dev, 0x8c, 0xB400DA);
+	pci_conf1_write_config32(dev, 0x90, 0xB400DA);
+	pci_conf1_write_config32(dev, 0x94, 0xB400DA);
+
+	/* Port0-3 BIST Control/Status */
+	pci_conf1_write_config8(dev, 0xa5, 0xB8);
+	pci_conf1_write_config8(dev, 0xad, 0xB8);
+	pci_conf1_write_config8(dev, 0xb5, 0xB8);
+	pci_conf1_write_config8(dev, 0xbd, 0xB8);
+}
+
+/* sbPmioPorInitTable, Pre-initializing PMIO register space
+* The power management (PM) block is resident in the PCI/LPC/ISA bridge.
+* The PM regs are accessed via IO mapped regs 0xcd6 and 0xcd7.
+* The index address is first programmed into IO reg 0xcd6.
+* Read or write values are accessed through IO reg 0xcd7.
+*/
+static void sb600_pmio_por_init()
+{
+	u8 byte;
+
+	printk(BIOS_INFO, "sb600_pmio_por_init()\n");
+	/* K8KbRstEn, KB_RST# control for K8 system. */
+	byte = pmio_read(0x66);
+	byte |= 0x20;
+	pmio_write(0x66, byte);
+
+	/* RPR2.3.4 S3/S4/S5 Function for the K8 Platform. */
+	byte = pmio_read(0x52);
+	byte &= 0xc0;
+	byte |= 0x08;
+	pmio_write(0x52, byte);
+
+	/* C state enable and SLP enable in C states. */
+	byte = pmio_read(0x67);
+	byte |= 0x6;
+	pmio_write(0x67, byte);
+
+	/* CIM sets 0x0e, but bit2 is for P4 system. */
+	byte = pmio_read(0x68);
+	byte &= 0xf0;
+	byte |= 0x0c;
+	pmio_write(0x68, byte);
+
+	/* Watch Dog Timer Control
+	 * Set watchdog time base to 0xfec000f0 to avoid SCSI card boot failure.
+	 * But I don't find WDT is enabled in SMBUS 0x41 bit3 in CIM.
+	 */
+	pmio_write(0x6c, 0xf0);
+	pmio_write(0x6d, 0x00);
+	pmio_write(0x6e, 0xc0);
+	pmio_write(0x6f, 0xfe);
+
+	/* rpr2.14: Enables HPET periodical mode */
+	byte = pmio_read(0x9a);
+	byte |= 1 << 7;
+	pmio_write(0x9a, byte);
+	byte = pmio_read(0x9f);
+	byte |= 1 << 5;
+	pmio_write(0x9f, byte);
+	byte = pmio_read(0x9e);
+	byte |= (1 << 6) | (1 << 7);
+	pmio_write(0x9e, byte);
+
+	/* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */
+	byte = pmio_read(0x55);
+	byte |= 1 << 7;
+	pmio_write(0x55, byte);
+
+	/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */
+	byte = pmio_read(0x52);
+	byte |= 1 << 6;
+	pmio_write(0x52, byte);
+
+	/* rpr2.22: PLL Reset */
+	byte = pmio_read(0x86);
+	byte |= 1 << 7;
+	pmio_write(0x86, byte);
+
+	/* rpr2.3.3 */
+	/* This provides 16us delay before the assertion of LDTSTP# when C3 is entered.
+	* The delay will allow USB DMA to go on in a continuous manner
+	*/
+	pmio_write(0x89, 0x10);
+	/* Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time */
+	byte = pmio_read(0x52);
+	byte |= 1 << 7;
+	pmio_write(0x52, byte);
+
+	/* rpr2.15: ASF Remote Control Action */
+	byte = pmio_read(0x9f);
+	byte |= 1 << 6;
+	pmio_write(0x9f, byte);
+
+	/* rpr2.19: Enabling Spread Spectrum */
+	byte = pmio_read(0x42);
+	byte |= 1 << 7;
+	pmio_write(0x42, byte);
+}
+
+/*
+* Compliant with CIM_48's sbPciCfg.
+* Add any south bridge setting.
+*/
+static void sb600_pci_cfg()
+{
+	u32 dev;
+	u8 byte;
+
+	/* SMBus Device, BDF:0-20-0 */
+	pci_conf1_find_device(0x1002,  0x4385, &dev);
+	/* Eable the hidden revision ID, available after A13. */
+	byte = pci_conf1_read_config8(dev, 0x70);
+	byte |= (1 << 8);
+	pci_conf1_write_config8(dev, 0x70, byte);
+	/* rpr2.20 Disable Timer IRQ Enhancement for proper operation of the 8254 timer, 0xae[5]. */
+	byte = pci_conf1_read_config8(dev, 0xae);
+	byte |= (1 << 5);
+	pci_conf1_write_config8(dev, 0xae, byte);
+
+	/* Enable watchdog decode timer */
+	byte = pci_conf1_read_config8(dev, 0x41);
+	byte |= (1 << 3);
+	pci_conf1_write_config8(dev, 0x41, byte);
+
+	/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles) 
+	 * generated PCIRST#. */
+	byte = pmio_read(0x65);
+	byte |= (1 << 4);
+	pmio_write(0x65, byte);
+	/*For A13 and above. */
+	if (get_sb600_revision() > 0x12) {
+		/* rpr2.16 C-State Reset, PMIO 0x9f[7]. */
+		byte = pmio_read(0x9f);
+		byte |= (1 << 7);
+		pmio_write(0x9f, byte);
+		/* rpr2.17 PCI Clock Period will increase to 30.8ns. 0x53[7]. */
+		byte = pmio_read(0x53);
+		byte |= (1 << 7);
+		pmio_write(0x53, byte);
+	}
+
+	/* IDE Device, BDF:0-20-1 */
+	pci_conf1_find_device(0x1002,  0x438C, &dev);
+	/* Enable IDE Explicit prefetch, 0x63[0] clear */
+	byte = pci_conf1_read_config8(dev, 0x63);
+	byte &= 0xfe;
+	pci_conf1_write_config8(dev, 0x63, byte);
+
+	/* LPC Device, BDF:0-20-3 */
+	pci_conf1_find_device(0x1002,  0x438D, &dev);
+	/* rpr7.2 Enabling LPC DMA function. */
+	byte = pci_conf1_read_config8(dev, 0x40);
+	byte |= (1 << 2);
+	pci_conf1_write_config8(dev, 0x40, byte);
+	/* rpr7.3 Disabling LPC TimeOut. 0x48[7] clear. */
+	byte = pci_conf1_read_config8(dev, 0x48);
+	byte &= 0x7f;
+	pci_conf1_write_config8(dev, 0x48, byte);
+	/* rpr7.5 Disabling LPC MSI Capability, 0x78[1] clear. */
+	byte = pci_conf1_read_config8(dev, 0x78);
+	byte &= 0xfd;
+	pci_conf1_write_config8(dev, 0x78, byte);
+
+	/* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
+	pci_conf1_find_device(0x1002,  0x4380, &dev);
+	/* rpr6.8 Disabling SATA MSI Capability, for A13 and above, 0x42[7]. */
+	if (0x12 < get_sb600_revision()) {
+		u32 reg32;
+		reg32 = pci_conf1_read_config32(dev, 0x40);
+		reg32 |= (1 << 23);
+		pci_conf1_write_config32(dev, 0x40, reg32);
+	}
+
+	/* EHCI Device, BDF:0-19-5, ehci usb controller */
+	pci_conf1_find_device(0x1002,  0x4386, &dev);
+	/* rpr5.10 Disabling USB EHCI MSI Capability. 0x50[6]. */
+	byte = pci_conf1_read_config8(dev, 0x50);
+	byte |= (1 << 6);
+	pci_conf1_write_config8(dev, 0x50, byte);
+
+	/* OHCI0 Device, BDF:0-19-0, ohci usb controller #0 */
+	pci_conf1_find_device(0x1002,  0x4387, &dev);
+	/* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */
+	byte = pci_conf1_read_config8(dev, 0x41);
+	byte |= 0x1f;
+	pci_conf1_write_config8(dev, 0x41, byte);
+
+}
+
+/*
+* Compliant with CIM_48's ATSBPowerOnResetInitJSP
+*/
+static void sb600_por_init()
+{
+	/* sbDevicesPorInitTable + sbK8PorInitTable */
+	sb600_devices_por_init();
+
+	/* sbPmioPorInitTable + sbK8PmioPorInitTable */
+	sb600_pmio_por_init();
+}
+
+/*
+* Compliant with CIM_48's AtiSbBeforePciInit
+* It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration.
+*/
+static void sb600_before_pci_init()
+{
+	sb600_pci_cfg();
+}
+
+/*
+* This function should be called after enable_sb600_smbus().
+*/
+static void sb600_stage1(void)
+{
+	printk(BIOS_INFO, "sb600_early_setup()\n");
+	sb600_por_init();
+}

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/stage1_reset.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/stage1_reset.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/stage1_reset.c	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/pci.h>
+#include <msr.h>
+#include <legacy.h>
+#include <device/pci_ids.h>
+#include <statictree.h>
+#include <config.h>
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only resets coherent link table, but 
+	 * does not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/stage1_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/stage1_smbus.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/stage1_smbus.c	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,229 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/pci.h>
+#include <msr.h>
+#include <legacy.h>
+#include <device/pci.h>
+#include <statictree.h>
+#include <config.h>
+#include <io.h>
+#include "sb600_smbus.h"
+
+void smbus_delay(void)
+{
+	inb(0x80);
+}
+
+int smbus_wait_until_ready(u32 smbus_io_base)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		u8 val;
+		val = inb(smbus_io_base + SMBHSTSTAT);
+		val &= 0x1f;
+		if (val == 0) {	/* ready now */
+			return 0;
+		}
+		outb(val, smbus_io_base + SMBHSTSTAT);
+	} while (--loops);
+	return -2;		/* time out */
+}
+
+int smbus_wait_until_done(u32 smbus_io_base)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		u8 val;
+
+		val = inb(smbus_io_base + SMBHSTSTAT);
+		val &= 0x1f;	/* mask off reserved bits */
+		if (val & 0x1c) {
+			return -5;	/* error */
+		}
+		if (val == 0x02) {
+			outb(val, smbus_io_base + SMBHSTSTAT);	/* clear status */
+			return 0;
+		}
+	} while (--loops);
+	return -3;		/* timeout */
+}
+
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return -2;	/* not ready */
+	}
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTCMD);
+
+	return byte;
+}
+
+int do_smbus_send_byte(u32 smbus_io_base, u32 device,
+			      u8 val)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return -2;	/* not ready */
+	}
+
+	/* set the command... */
+	outb(val, smbus_io_base + SMBHSTCMD);
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	return 0;
+}
+
+int do_smbus_read_byte(u32 smbus_io_base, u32 device,
+			      u32 address)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return -2;	/* not ready */
+	}
+
+	/* set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+	/* set the device I'm talking to */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+
+	return byte;
+}
+
+int do_smbus_write_byte(u32 smbus_io_base, u32 device,
+			       u32 address, u8 val)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return -2;	/* not ready */
+	}
+
+	/* set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+	/* set the device I'm talking to */
+	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
+
+	/* output value */
+	outb(val, smbus_io_base + SMBHSTDAT0);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	return 0;
+}
+
+void alink_ab_indx(unsigned int reg_space, unsigned int reg_addr,
+			  unsigned int mask, unsigned int val)
+{
+	unsigned int tmp;
+	outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);
+	tmp = inl(AB_DATA);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	/* printk_debug("about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
+	outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
+	outl(tmp, AB_DATA);
+}
+
+/* space = 0: AX_INDXC, AX_DATAC
+*   space = 1: AX_INDXP, AX_DATAP
+ */
+void alink_ax_indx(unsigned int space /*c or p? */ , unsigned int axindc,
+			  unsigned int mask, unsigned int val)
+{
+	unsigned int tmp;
+
+	/* read axindc to tmp */
+	outl(space << 30 | space << 3 | 0x30, AB_INDX);
+	outl(axindc, AB_DATA);
+	outl(space << 30 | space << 3 | 0x34, AB_INDX);
+	tmp = inl(AB_DATA);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	/* write tmp */
+	outl(space << 30 | space << 3 | 0x30, AB_INDX);
+	outl(axindc, AB_DATA);
+	outl(space << 30 | space << 3 | 0x34, AB_INDX);
+	outl(tmp, AB_DATA);
+}
+
+
+

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/usb.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/usb.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/usb.c	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,205 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <usbdebug_direct.h>
+#include <arch/io.h>
+#include "sb600.h"
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static void usb_init(struct device *dev)
+{
+	u8 byte;
+	u16 word;
+	u32 dword;
+
+	/* Enable OHCI0-4 and EHCI Controllers */
+	struct device * sm_dev;
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	byte = pci_read_config8(sm_dev, 0x68);
+	byte |= 0x3F;
+	pci_write_config8(sm_dev, 0x68, byte);
+
+	/* RPR 5.2 Enables the USB PME Event,Enable USB resume support */
+	byte = pm_ioread(0x61);
+	byte |= 1 << 6;
+	pm_iowrite(0x61, byte);
+	byte = pm_ioread(0x65);
+	byte |= 1 << 2;
+	pm_iowrite(0x65, byte);
+
+	/* RPR 5.3 Support USB device wakeup from the S4/S5 state */
+	byte = pm_ioread(0x65);
+	byte &= ~(1 << 0);
+	pm_iowrite(0x65, byte);
+
+	/* RPR 5.6 Enable the USB controller to get reset by any software that generate a PCIRst# condition */
+	byte = pm_ioread(0x65);
+	byte |= (1 << 4);
+	pm_iowrite(0x65, byte);
+
+	/* RPR 5.11 Disable OHCI MSI Capability */
+	word = pci_read_config16(dev, 0x40);
+	word |= (0x1F << 8);
+	pci_write_config16(dev, 0x40, word);
+
+	/* RPR 5.8 Disable the OHCI Dynamic Power Saving feature  */
+	dword = pci_read_config32(dev, 0x50);
+	dword &= ~(1 << 16);
+	pci_write_config32(dev, 0x50, dword);
+
+	/* RPR 5.12 Enable prevention of OHCI accessing the invalid system memory address range */
+	word = pci_read_config16(dev, 0x50);
+	word |= 1 << 15;
+	pci_write_config16(dev, 0x50, word);
+
+	/* RPR 5.15 Disable SMI handshake in between USB and ACPI for USB legacy support. */
+	/* The BIOS should always set this bit to prevent the malfunction on USB legacy keyboard/mouse support */
+	word = pci_read_config16(dev, 0x50);
+	word |= 1 << 12;
+	pci_write_config16(dev, 0x50, word);
+}
+
+static void usb_init2(struct device *dev)
+{
+	u8 byte;
+	u16 word;
+	u32 dword;
+	u8 *usb2_bar0;
+	/* dword = pci_read_config32(dev, 0xf8); */
+	/* dword |= 40; */
+	/* pci_write_config32(dev, 0xf8, dword); */
+
+	usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF);
+	printk_info("usb2_bar0=%x\n", usb2_bar0);
+
+	/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */
+	dword = 0x00020F00;
+	writel(dword, usb2_bar0 + 0xC0);
+
+	/* RPR5.5 Sets In/OUT FIFO threshold for best performance */
+	dword = 0x00200040;
+	writel(dword, usb2_bar0 + 0xA4);
+
+	/* RPR5.9 Disable the EHCI Dynamic Power Saving feature */
+	word = readl(usb2_bar0 + 0xBC);
+	word &= ~(1 << 12);
+	writew(word, usb2_bar0 + 0xBC);
+
+	/* RPR5.10 Disable EHCI MSI support */
+	byte = pci_read_config8(dev, 0x50);
+	byte |= (1 << 6);
+	pci_write_config8(dev, 0x50, byte);
+
+	/* RPR5.13 Disable C3 time enhancement feature */
+	dword = pci_read_config32(dev, 0x50);
+	dword &= ~(1 << 28);
+	pci_write_config32(dev, 0x50, dword);
+
+	/* RPR5.14 Disable USB PHY PLL Reset signal to come from ACPI */
+	byte = pci_read_config8(dev, 0x54);
+	byte &= ~(1 << 0);
+	pci_write_config8(dev, 0x54, byte);
+}
+
+static void usb_set_resources(struct device *dev)
+{
+#ifdef CONFIG_USBDEBUG_DIRECT
+	struct resource *res;
+	u32 base;
+	u32 old_debug;
+
+	old_debug = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+	pci_dev_set_resources(dev);
+
+#ifdef CONFIG_USBDEBUG_DIRECT
+	res = find_resource(dev, 0x10);
+	set_ehci_debug(old_debug);
+	if (!res)
+		return;
+	base = res->base;
+	set_ehci_base(base);
+	report_resource_stored(dev, res, "");
+#endif
+
+}
+
+/* note that below there are a lot of usb drivers. But we don't support linker sets
+ * What we need to do is has a phase 2 function that puts the many usb devices into the device tree. 
+ * That's one of the purposes of phase 2. We will write this later. 
+ *
+ */
+#warning need USB phase 2 function to populate device tree
+struct device_operations sb600_usb = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
+			      .device = PCI_DEVICE_ID_ATI_SB600_USB_0}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = scan_static_bus,
+	.phase4_read_resources	 = pci_dev_read_resources,
+	.phase4_set_resources	 = usb_set_resources,
+	.phase5_enable_resources = pci_dev_enable_resources,
+	.phase6_init		 = usb_init,
+	.ops_pci          = &lops_pci
+};
+
+#if 0
+static struct pci_driver usb_1_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB_1,
+};
+static struct pci_driver usb_2_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB_2,
+};
+static struct pci_driver usb_3_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB_3,
+};
+static struct pci_driver usb_4_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB_4,
+};
+#endif
+
+struct device_operations sb600_usb2 = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
+			      .device = PCI_DEVICE_ID_ATI_SB600_USB2}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = scan_static_bus,
+	.phase4_read_resources	 = pci_dev_read_resources,
+	.phase4_set_resources	 = usb_set_resources,
+	.phase5_enable_resources = pci_dev_enable_resources,
+	.phase6_init		 = usb_init,
+	.ops_pci          = &lops_pci
+};

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/usb.dts
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/usb.dts	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/usb.dts	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "sb600_usb";
+};

Added: trunk/coreboot-v2/src/southbridge/amd/sb600/usb2.dts
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/usb2.dts	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/usb2.dts	2008-10-02 15:42:14 UTC (rev 3630)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "sb600_usb2";
+};




From rminnich at gmail.com  Thu Oct  2 17:46:10 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 2 Oct 2008 08:46:10 -0700
Subject: [coreboot] Status of OpenVSA?
In-Reply-To: <48E4A0BF.9050009@ampltd.com>
References: <48E4A0BF.9050009@ampltd.com>
Message-ID: <13426df10810020846w26832420se812cc3e4d159a6f@mail.gmail.com>

On Thu, Oct 2, 2008 at 3:21 AM, Stephen Crocker <scrocker at ampltd.com> wrote:
> I have been experimenting with the OpenVSA code and have found that it
> becomes stuck on POST code 17.  By adding extra codes, I have narrowed this
> down to the SAVE_STATE macro, which reads the PCI address port (cf8).
>
> Furthermore, in order to build it, I had to remove the -Werror flag from the
> Makefile because of several "cast from pointer to integer of different size"
> errors.

I think you really want to fix that error. I don't like to let that
kind of thing go by.

ron



From svn at coreboot.org  Thu Oct  2 17:50:38 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Oct 2008 17:50:38 +0200
Subject: [coreboot] r243 - buildrom-devel/config/platforms
Message-ID: <mailman.2158.1355071390.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-10-02 17:50:37 +0200 (Thu, 02 Oct 2008)
New Revision: 243

Added:
   buildrom-devel/config/platforms/asus_a8n-e.conf
Modified:
   buildrom-devel/config/platforms/Config.in
   buildrom-devel/config/platforms/platforms.conf
Log:
Add buildrom support for the ASUS A8N-E.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>



Modified: buildrom-devel/config/platforms/Config.in
===================================================================
--- buildrom-devel/config/platforms/Config.in	2008-09-29 21:53:20 UTC (rev 242)
+++ buildrom-devel/config/platforms/Config.in	2008-10-02 15:50:37 UTC (rev 243)
@@ -97,6 +97,13 @@
        select PLATFORM
        select PLATFORM_SUPPORT_64BIT
 
+config PLATFORM_ASUS_A8N_E
+       bool "ASUS A8N-E"
+       depends on VENDOR_ASUS
+       depends on COREBOOT_V2
+       select PLATFORM
+       select PLATFORM_SUPPORT_64BIT
+
 config PLATFORM_GA_2761GXDK
 	bool "GIGABYTE GA-2761GXDK"
 	depends on VENDOR_GIGABYTE

Added: buildrom-devel/config/platforms/asus_a8n-e.conf
===================================================================
--- buildrom-devel/config/platforms/asus_a8n-e.conf	                        (rev 0)
+++ buildrom-devel/config/platforms/asus_a8n-e.conf	2008-10-02 15:50:37 UTC (rev 243)
@@ -0,0 +1,29 @@
+# Support for the ASUS A8N-E board
+
+#### Platform configuration
+
+ifeq ($(CONFIG_TARGET_64BIT),y)
+TARGET_ARCH=x86_64
+CFLAGS_platform =
+else
+TARGET_ARCH=i686
+CFLAGS_platform =
+endif
+
+# kernel configuration (for LAB)
+
+# TODO
+
+UCLIBC_ARCH=$(TARGET_ARCH)
+
+# Etherboot configuration
+
+ETHERBOOT_ARCH=i386
+
+# coreboot configuration
+
+COREBOOT_VENDOR=asus
+COREBOOT_BOARD=a8n_e
+CBV2_TDIR=asus_a8n_e
+CBV2_TAG=3626
+

Modified: buildrom-devel/config/platforms/platforms.conf
===================================================================
--- buildrom-devel/config/platforms/platforms.conf	2008-09-29 21:53:20 UTC (rev 242)
+++ buildrom-devel/config/platforms/platforms.conf	2008-10-02 15:50:37 UTC (rev 243)
@@ -22,6 +22,7 @@
 PLATFORM-$(CONFIG_PLATFORM_DBE61) = dbe61.conf
 PLATFORM-$(CONFIG_PLATFORM_GA_M57SLI_S4) = m57sli.conf
 PLATFORM-$(CONFIG_PLATFORM_ASUS_A8V_E_SE) = asus_a8v-e_se.conf
+PLATFORM-$(CONFIG_PLATFORM_ASUS_A8N_E) = asus_a8n-e.conf
 PLATFORM-$(CONFIG_PLATFORM_TYAN_S2881) = tyan-s2881.conf
 PLATFORM-$(CONFIG_PLATFORM_TYAN_S2882) = tyan-s2882.conf
 PLATFORM-$(CONFIG_PLATFORM_TYAN_S2891) = tyan-s2891.conf




From uwe at hermann-uwe.de  Thu Oct  2 17:51:33 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 2 Oct 2008 17:51:33 +0200
Subject: [coreboot] buildrom: Add support for the ASUS A8N-E
In-Reply-To: <20081001215859.GB25831@cosmic.amd.com>
References: <20081001213347.GG22678@greenwood>
	<20081001215859.GB25831@cosmic.amd.com>
Message-ID: <20081002155133.GA27260@greenwood>

On Wed, Oct 01, 2008 at 03:58:59PM -0600, Jordan Crouse wrote:
> > Doesn't seem to build with LZMA enabled, only if you disable it. The
> > same seems to happen to all boards which don't have a Config-lab.lb
> > which should probably be fixed. IIRC LZMA should work regardless of
> > whether you have LAB as payload or not(?)
> 
> LZMA in v2 needs options set in the Config.lb that happen to
> be set in Config-lab.lb, so we sort of made the arbitrary decision to
> just use that .lb if LZMA is enabled.  I dislike this solution immensely,
> but I can't think of a good way to work around it unless we generate the
> Config.lb at runtime, which has its own bug-a-bears.  Yet another
> situation where v3 will save us all... :(
> 
> If you want to rename Config-lab.lb to something more descriptive, then
> be my guest. You have my ack for that.

Maybe Config-lzma.lb then. I might send a patch for that.


> > Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
> 
> Acked-by: Jordan Crouse <jordan.crouse at amd.com>
 
Thanks, r243.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From rminnich at gmail.com  Thu Oct  2 17:55:22 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 2 Oct 2008 08:55:22 -0700
Subject: [coreboot] r877 - in coreboot-v3: arch/x86/amd/model_fxx
	mainboard/gigabyte/m57sli northbridge/amd/k8
	southbridge/nvidia/mcp55
In-Reply-To: <48E4CDEE.4050806@coresystems.de>
References: <48E343A1.4000003@coresystems.de>
	<13426df10810010702n1633fff3kb764852c6eedbd23@mail.gmail.com>
	<48E4CDEE.4050806@coresystems.de>
Message-ID: <13426df10810020855o75a24a3dvb07d71a79fc92d76@mail.gmail.com>

On Thu, Oct 2, 2008 at 6:34 AM, Stefan Reinauer <stepan at coresystems.de> wrote:
> ron minnich wrote:
>>>> m57sli mostly builds again. The stage0 is too large at 24k.
>>>> We need to figure out if we should just grow stage0. My inclination is
>>>> to say 'yes'.
>>>>
>>>>
>>> What's in stage0 that makes it so big? Is that part really required in
>>> stage0?
>>>
>>
>> hyptertransport setup has to be in stage0. I can't see a way around it.
>>
>
> Why? Can't this go to initram?
>

not for the mcp55.

I am gong to do a quick detour to 690 support, it looks not too bad
and the nvidia parts are making my head hurt. I just remembered the
special microcode support they need, with the special ldscript Owie.

ron



From rminnich at gmail.com  Thu Oct  2 17:58:30 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 2 Oct 2008 08:58:30 -0700
Subject: [coreboot] splash screen
In-Reply-To: <20081002143619.GE25831@cosmic.amd.com>
References: <20080923173708.GB30198@cosmic.amd.com>
	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>
	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>
	<20081001184713.GD22980@cosmic.amd.com>
	<13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
	<20081001214824.GA25831@cosmic.amd.com>
	<48E40687.9090501@coresystems.de>
	<20081001234232.GC25831@cosmic.amd.com>
	<20081002003049.13358.qmail@stuge.se>
	<20081002143619.GE25831@cosmic.amd.com>
Message-ID: <13426df10810020858y8644b66r6b72ed3440cbbe4b@mail.gmail.com>

On Thu, Oct 2, 2008 at 7:36 AM, Jordan Crouse <jordan.crouse at amd.com> wrote:

> Thats just my opinion - as always, patches are gladly accepted.  Just
> remember who we are, what we are doing.  Somebody at the Linux Plumbers
> Conference said, "Every time I see a splash screen, I wonder what they
> have to hide".  Coreboot is the only loader on earth that doesn't actually
> have anything to hide.  Lets try not to go overboard architecting a solution
> for one problem we don't have.
>

in fact I may let linux do the splash screen anyway -- all other
options are looking painful.

Remember the original linuxbios slogan? "Let Linux do it".

One thing I've noticed is that, having dropped Linux as a primary
payload, we are recreating lots of code for things linux can already
do.

Once we start to implement IPV6 in a payload, we need to stop and
think hard about what we are doing.

ron



From patrick at georgi-clan.de  Thu Oct  2 18:01:43 2008
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Thu, 02 Oct 2008 18:01:43 +0200
Subject: [coreboot] splash screen
In-Reply-To: <13426df10810020858y8644b66r6b72ed3440cbbe4b@mail.gmail.com>
References: <20080923173708.GB30198@cosmic.amd.com>	<Pine.LNX.4.64.0809231354250.6877@bigred.russwhit.org>	<13426df10810011103t63ec38acq79e77ae0aa4d8871@mail.gmail.com>	<20081001184713.GD22980@cosmic.amd.com>	<13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>	<20081001214824.GA25831@cosmic.amd.com>	<48E40687.9090501@coresystems.de>	<20081001234232.GC25831@cosmic.amd.com>	<20081002003049.13358.qmail@stuge.se>	<20081002143619.GE25831@cosmic.amd.com>
	<13426df10810020858y8644b66r6b72ed3440cbbe4b@mail.gmail.com>
Message-ID: <48E4F067.5050400@georgi-clan.de>

ron minnich schrieb:
> Remember the original linuxbios slogan? "Let Linux do it".
>   
Just that Linux grew _large_. (and its devs have no interest in being
firmware agnostic)
> One thing I've noticed is that, having dropped Linux as a primary
> payload, we are recreating lots of code for things linux can already
> do.
>   
Maybe there are different operating systems that fit better into our
constraints? minix3? haiku? ;-)


Regards,
Patrick



From svn at coreboot.org  Thu Oct  2 18:07:10 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Oct 2008 18:07:10 +0200
Subject: [coreboot] r880 - coreboot-v3/include/arch/x86/amd/k8
Message-ID: <mailman.2159.1355071390.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-10-02 18:07:10 +0200 (Thu, 02 Oct 2008)
New Revision: 880

Modified:
   coreboot-v3/include/arch/x86/amd/k8/k8.h
Log:
add new socket type (trivial)
Signed-off-by: Ronald G. Minnich <rminnch at gmail.com>
Acked-by: Ronald G. Minnich <rminnch at gmail.com>



Modified: coreboot-v3/include/arch/x86/amd/k8/k8.h
===================================================================
--- coreboot-v3/include/arch/x86/amd/k8/k8.h	2008-10-01 18:29:22 UTC (rev 879)
+++ coreboot-v3/include/arch/x86/amd/k8/k8.h	2008-10-02 16:07:10 UTC (rev 880)
@@ -23,6 +23,7 @@
 #ifndef AMD_K8_H
 #define AMD_K8_H
 /* Socket types */
+#define SOCKET_S1G1 0x12
 #define SOCKET_AM2 0x11
 #define SOCKET_L1	0x10
 




From mylesgw at gmail.com  Thu Oct  2 18:10:44 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 2 Oct 2008 10:10:44 -0600
Subject: [coreboot] buildrom: Add support for the ASUS A8N-E
In-Reply-To: <20081002155133.GA27260@greenwood>
References: <20081001213347.GG22678@greenwood><20081001215859.GB25831@cosmic.amd.com>
	<20081002155133.GA27260@greenwood>
Message-ID: <AA14F0D1EFD74311832F88B7C5C9EF31@chimp>



> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Uwe Hermann
> Sent: Thursday, October 02, 2008 9:52 AM
> To: Jordan Crouse
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] buildrom: Add support for the ASUS A8N-E
> 
> On Wed, Oct 01, 2008 at 03:58:59PM -0600, Jordan Crouse wrote:
> > > Doesn't seem to build with LZMA enabled, only if you disable it. The
> > > same seems to happen to all boards which don't have a Config-lab.lb
> > > which should probably be fixed. IIRC LZMA should work regardless of
> > > whether you have LAB as payload or not(?)
> >
> > LZMA in v2 needs options set in the Config.lb that happen to
> > be set in Config-lab.lb, so we sort of made the arbitrary decision to
> > just use that .lb if LZMA is enabled.  I dislike this solution
> immensely,
> > but I can't think of a good way to work around it unless we generate the
> > Config.lb at runtime, which has its own bug-a-bears.  Yet another
> > situation where v3 will save us all... :(
> >

The original reason it was named Config-lab.lb was that some times it uses a
larger chip than is default on the board.  It also is generally
fallback-only to allow for the larger payload.

> > If you want to rename Config-lab.lb to something more descriptive, then
> > be my guest. You have my ack for that.
> 
> Maybe Config-lzma.lb then. I might send a patch for that.

Definitely a better name.

Myles





From rminnich at gmail.com  Thu Oct  2 18:02:29 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 2 Oct 2008 09:02:29 -0700
Subject: [coreboot] sb600 support in v3
Message-ID: <13426df10810020902pd2d0c35p754d0c896107dd6f@mail.gmail.com>

I just committed it, because I want some eyeballs on it. Corrections
etc. welcome.

rs690 is next, then the socket, then the mainboard.

This should be interesting.

I'm trying to get a simnow for this board, but it's the nda version,
so I'm still working it.

ron



From rminnich at gmail.com  Thu Oct  2 18:17:01 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 2 Oct 2008 09:17:01 -0700
Subject: [coreboot] splash screen
In-Reply-To: <48E4F067.5050400@georgi-clan.de>
References: <20080923173708.GB30198@cosmic.amd.com>
	<20081001184713.GD22980@cosmic.amd.com>
	<13426df10810011149j56ff374l7067db89909b658c@mail.gmail.com>
	<20081001214824.GA25831@cosmic.amd.com>
	<48E40687.9090501@coresystems.de>
	<20081001234232.GC25831@cosmic.amd.com>
	<20081002003049.13358.qmail@stuge.se>
	<20081002143619.GE25831@cosmic.amd.com>
	<13426df10810020858y8644b66r6b72ed3440cbbe4b@mail.gmail.com>
	<48E4F067.5050400@georgi-clan.de>
Message-ID: <13426df10810020917i1c955ff3q492c17327502860b@mail.gmail.com>

On Thu, Oct 2, 2008 at 9:01 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> ron minnich schrieb:
>> Remember the original linuxbios slogan? "Let Linux do it".
>>
> Just that Linux grew _large_. (and its devs have no interest in being
> firmware agnostic)

yes, they lost their way. "We don't need no steenking BIOS" is no
longer true. I wonder if they removed that quote yet.

What a shame.

ron



From info at coresystems.de  Thu Oct  2 18:21:13 2008
From: info at coresystems.de (coreboot information)
Date: Thu, 02 Oct 2008 18:21:13 +0200
Subject: [coreboot] r3630 build service
Message-ID: <E1KlQvR-0001T3-31@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "rminnich" checked in revision 3630 to
the coreboot source repository and caused the following 
changes:

Change Log:
This is so that people can see it. This is the sb600 for v3. It almost
certainly won't build -- that comes later. I am hoping to get some
eyeballs on it for simple errors.

rs690 is next.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Build Log:
Compilation of amd:dbm690t has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3630&device=dbm690t&vendor=amd
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3630&device=j7f24&vendor=jetway
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3630&device=epia-cn&vendor=via


If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From peter at stuge.se  Thu Oct  2 18:42:14 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Oct 2008 18:42:14 +0200
Subject: [coreboot] sb600 support in v3
In-Reply-To: <13426df10810020902pd2d0c35p754d0c896107dd6f@mail.gmail.com>
References: <13426df10810020902pd2d0c35p754d0c896107dd6f@mail.gmail.com>
Message-ID: <20081002164214.15886.qmail@stuge.se>

ron minnich wrote:
> I just committed it, because I want some eyeballs on it.
> Corrections etc. welcome.

For starters it went into v2. :)

I guess it's mostly copypaste so not much can be wrong?


> I'm trying to get a simnow for this board, but it's the nda
> version, so I'm still working it.

Couldn't someone with the NDA version create the board, then share it
with those who have only the public version?


//Peter



From jordan.crouse at amd.com  Thu Oct  2 18:48:35 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 2 Oct 2008 10:48:35 -0600
Subject: [coreboot] sb600 support in v3
In-Reply-To: <20081002164214.15886.qmail@stuge.se>
References: <13426df10810020902pd2d0c35p754d0c896107dd6f@mail.gmail.com>
	<20081002164214.15886.qmail@stuge.se>
Message-ID: <20081002164835.GI25831@cosmic.amd.com>

On 02/10/08 18:42 +0200, Peter Stuge wrote:
> ron minnich wrote:
> > I just committed it, because I want some eyeballs on it.
> > Corrections etc. welcome.
> 
> For starters it went into v2. :)
> 
> I guess it's mostly copypaste so not much can be wrong?
> 
> 
> > I'm trying to get a simnow for this board, but it's the nda
> > version, so I'm still working it.
> 
> Couldn't someone with the NDA version create the board, then share it
> with those who have only the public version?

No, I don't think that the public version has the models that you need.
Unfortunately.

Jordan




From svn at coreboot.org  Thu Oct  2 20:19:18 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Oct 2008 20:19:18 +0200
Subject: [coreboot] r3631 - trunk/coreboot-v2/src/southbridge/nvidia/ck804
Message-ID: <mailman.2160.1355071391.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-10-02 20:19:17 +0200 (Thu, 02 Oct 2008)
New Revision: 3631

Modified:
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_smbus.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_enable_rom.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ht.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.h
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/romstrap.inc
Log:
CK804 coding-style fixed based on an 'indent' run (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h	2008-10-02 18:19:17 UTC (rev 3631)
@@ -1,8 +1,7 @@
 #ifndef CK804_CHIP_H
 #define CK804_CHIP_H
 
-struct southbridge_nvidia_ck804_config
-{
+struct southbridge_nvidia_ck804_config {
 	unsigned int usb1_hc_reset : 1;
 	unsigned int ide0_enable : 1;
 	unsigned int ide1_enable : 1;
@@ -16,4 +15,4 @@
 struct chip_operations;
 extern struct chip_operations southbridge_nvidia_ck804_ops;
 
-#endif /* CK804_CHIP_H */
+#endif

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -4,9 +4,7 @@
  */
 
 #include <console/console.h>
-
 #include <arch/io.h>
-
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
@@ -15,178 +13,167 @@
 
 static uint32_t final_reg;
 
-static device_t find_lpc_dev( device_t dev,  unsigned devfn) 
+static device_t find_lpc_dev(device_t dev, unsigned devfn)
 {
-
 	device_t lpc_dev;
 
-        lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
+	lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
+	if (!lpc_dev)
+		return lpc_dev;
 
-        if ( !lpc_dev ) return lpc_dev;
+	if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA)
+		|| ((lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC)
+		&& (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO)
+		&& (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE)))
+	{
+		uint32_t id;
+		id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
+		if ((id != (PCI_VENDOR_ID_NVIDIA |
+		      (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16)))
+		    && (id != (PCI_VENDOR_ID_NVIDIA |
+			 (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16)))
+		    && (id != (PCI_VENDOR_ID_NVIDIA |
+			 (PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16))))
+		{
+			lpc_dev = 0;
+		}
+	}
 
-        if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || (
-		(lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC) &&
-                (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO) &&
-                (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE)) ) {
-                	uint32_t id;
-                        id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
-                        if ( (id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) &&
-                        	(id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16))) &&
-				(id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16)))
-				) {
-                               lpc_dev = 0;
-        		}
-        }
-
 	return lpc_dev;
 }
 
 void ck804_enable(device_t dev)
 {
 	device_t lpc_dev;
-	unsigned index = 0;
-	unsigned index2 = 0;
+	unsigned index = 0, index2 = 0, deviceid, vendorid, devfn;
 	uint32_t reg_old, reg;
 	uint8_t byte;
-	unsigned deviceid;
-	unsigned vendorid;
 
-        struct southbridge_nvidia_ck804_config *conf;
-        conf = dev->chip_info;
+	struct southbridge_nvidia_ck804_config *conf;
+	conf = dev->chip_info;
 
-	unsigned devfn;
-
-	if(dev->device==0x0000) {
+	if (dev->device == 0x0000) {
 		vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
-		deviceid = (vendorid>>16) & 0xffff;
-//		vendorid &= 0xffff;
+		deviceid = (vendorid >> 16) & 0xffff;
+		/* vendorid &= 0xffff; */
 	} else {
-//		vendorid = dev->vendor;
+		/* vendorid = dev->vendor; */
 		deviceid = dev->device;
 	}
 
 	devfn = (dev->path.u.pci.devfn) & ~7;
-	switch(deviceid) {
-		case PCI_DEVICE_ID_NVIDIA_CK804_SM:
-			index = 16;
-			break;
-		case PCI_DEVICE_ID_NVIDIA_CK804_USB:
-			devfn -= (1<<3);
-			index = 8;
-			break;
-                case PCI_DEVICE_ID_NVIDIA_CK804_USB2:
-                        devfn -= (1<<3);
-                        index = 20;
-                        break;
-                case PCI_DEVICE_ID_NVIDIA_CK804_NIC:
-                        devfn -= (9<<3);
-                        index = 10;
-			dev->rom_address = conf->nic_rom_address;
-                        break;
-                case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE:
-                        devfn -= (9<<3);
-                        index = 10;
-                        dev->rom_address = conf->nic_rom_address;
-                        break;
-                case PCI_DEVICE_ID_NVIDIA_CK804_ACI:
-                        devfn -= (3<<3);
-                        index = 12;
-                        break;
-                case PCI_DEVICE_ID_NVIDIA_CK804_MCI:
-                        devfn -= (3<<3);
-                        index = 13;
-                        break;
-                case PCI_DEVICE_ID_NVIDIA_CK804_IDE:
-                        devfn -= (5<<3);
-                        index = 14;
-			dev->rom_address = conf->raid_rom_address;
-                        break;
-                case PCI_DEVICE_ID_NVIDIA_CK804_SATA0:
-                        devfn -= (6<<3);
-                        index = 22;
-                        break;
-                case PCI_DEVICE_ID_NVIDIA_CK804_SATA1:
-                        devfn -= (7<<3);
-                        index = 18;
-                        break;
-                case PCI_DEVICE_ID_NVIDIA_CK804_PCI:
-                        devfn -= (8<<3);
-                        index = 15;
-                        break;
-		case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E:
-			devfn -= (0xa<<3);
-			index2 = 19;
-			break;
-		default:
-			index = 0;
+	switch (deviceid) {
+	case PCI_DEVICE_ID_NVIDIA_CK804_SM:
+		index = 16;
+		break;
+	case PCI_DEVICE_ID_NVIDIA_CK804_USB:
+		devfn -= (1 << 3);
+		index = 8;
+		break;
+	case PCI_DEVICE_ID_NVIDIA_CK804_USB2:
+		devfn -= (1 << 3);
+		index = 20;
+		break;
+	case PCI_DEVICE_ID_NVIDIA_CK804_NIC:
+		devfn -= (9 << 3);
+		index = 10;
+		dev->rom_address = conf->nic_rom_address;
+		break;
+	case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE:
+		devfn -= (9 << 3);
+		index = 10;
+		dev->rom_address = conf->nic_rom_address;
+		break;
+	case PCI_DEVICE_ID_NVIDIA_CK804_ACI:
+		devfn -= (3 << 3);
+		index = 12;
+		break;
+	case PCI_DEVICE_ID_NVIDIA_CK804_MCI:
+		devfn -= (3 << 3);
+		index = 13;
+		break;
+	case PCI_DEVICE_ID_NVIDIA_CK804_IDE:
+		devfn -= (5 << 3);
+		index = 14;
+		dev->rom_address = conf->raid_rom_address;
+		break;
+	case PCI_DEVICE_ID_NVIDIA_CK804_SATA0:
+		devfn -= (6 << 3);
+		index = 22;
+		break;
+	case PCI_DEVICE_ID_NVIDIA_CK804_SATA1:
+		devfn -= (7 << 3);
+		index = 18;
+		break;
+	case PCI_DEVICE_ID_NVIDIA_CK804_PCI:
+		devfn -= (8 << 3);
+		index = 15;
+		break;
+	case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E:
+		devfn -= (0xa << 3);
+		index2 = 19;
+		break;
+	default:
+		index = 0;
 	}
 
-	if(index2!=0) {
+	if (index2 != 0) {
 		int i;
-		for(i=0;i<4;i++) {
-			lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
-			if(!lpc_dev) continue;
+		for (i = 0; i < 4; i++) {
+			lpc_dev = find_lpc_dev(dev, devfn - (i << 3));
+			if (!lpc_dev)
+				continue;
 			index2 -= i;
 			break;
 		}
 
-		if ( lpc_dev ) {
-	                reg_old = reg =  pci_read_config32(lpc_dev, 0xe4);
-
-			if (!dev->enabled) { 
-				reg |= (1<<index2);
-			}
-
-                	if (reg != reg_old) {
-                        	pci_write_config32(lpc_dev, 0xe4, reg);
-                	}
+		if (lpc_dev) {
+			reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
+			if (!dev->enabled)
+				reg |= (1 << index2);
+			if (reg != reg_old)
+				pci_write_config32(lpc_dev, 0xe4, reg);
 		}
 
 		index2 = 0;
 		return;
 	}
 
-
 	lpc_dev = find_lpc_dev(dev, devfn);
+	if (!lpc_dev)
+		return;
 
-	if ( !lpc_dev )	return; 
-
-        if ( index == 0) {
-
+	if (index == 0) {
 		final_reg = pci_read_config32(lpc_dev, 0xe8);
-		final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<10)|(1<<12)|(1<<13)|(1<<14)|(1<<22)|(1<<18)|(1<<15));
-		pci_write_config32(lpc_dev, 0xe8, final_reg); 
+		final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 10)
+			| (1 << 12) | (1 << 13) | (1 << 14) | (1 << 22)
+			| (1 << 18) | (1 << 15));
+		pci_write_config32(lpc_dev, 0xe8, final_reg);
 
-                reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
-                reg |= (1<<20);
-                if (reg != reg_old) {
-                        pci_write_config32(lpc_dev, 0xe4, reg);
-                }
+		reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
+		reg |= (1 << 20);
+		if (reg != reg_old)
+			pci_write_config32(lpc_dev, 0xe4, reg);
 
-                byte = pci_read_config8(lpc_dev, 0x74);
-                byte |= ((1<<1)); 
-                pci_write_config8(dev, 0x74, byte);
+		byte = pci_read_config8(lpc_dev, 0x74);
+		byte |= ((1 << 1));
+		pci_write_config8(dev, 0x74, byte);
 
-                byte = pci_read_config8(lpc_dev, 0xdd);
-                byte |= ((1<<0)|(1<<3)); 
-                pci_write_config8(dev, 0xdd, byte);
+		byte = pci_read_config8(lpc_dev, 0xdd);
+		byte |= ((1 << 0) | (1 << 3));
+		pci_write_config8(dev, 0xdd, byte);
 
 		return;
+	}
 
-        }
+	if (!dev->enabled)
+		final_reg |= (1 << index);
 
-	if (!dev->enabled) {
-                final_reg |= (1 << index);
-        }
-
-	if(index == 10 ) { 
+	if (index == 10) {
 		reg_old = pci_read_config32(lpc_dev, 0xe8);
-        	if (final_reg != reg_old) {
-                	pci_write_config32(lpc_dev, 0xe8, final_reg);
-        	}
-
+		if (final_reg != reg_old)
+			pci_write_config32(lpc_dev, 0xe8, final_reg);
 	}
-
 }
 
 struct chip_operations southbridge_nvidia_ck804_ops = {

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h	2008-10-02 18:19:17 UTC (rev 3631)
@@ -5,4 +5,4 @@
 
 void ck804_enable(device_t dev);
 
-#endif /* CK804_H */
+#endif

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@
  * Copyright 2004 Tyan Computer
  *  by yhlu at tyan.com
  */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -11,19 +12,19 @@
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-        pci_write_config32(dev, 0x40,
-                ((device & 0xffff) << 16) | (vendor & 0xffff));
+	pci_write_config32(dev, 0x40,
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
 static struct pci_operations lops_pci = {
-        .set_subsystem = lpci_set_subsystem,
+	.set_subsystem = lpci_set_subsystem,
 };
 
-static struct device_operations ac97audio_ops  = {
+static struct device_operations ac97audio_ops = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-//	.enable           = ck804_enable,
+	// .enable        = ck804_enable,
 	.init             = 0,
 	.scan_bus         = 0,
 	.ops_pci          = &lops_pci,
@@ -35,12 +36,11 @@
 	.device = PCI_DEVICE_ID_NVIDIA_CK804_ACI,
 };
 
-
-static struct device_operations ac97modem_ops  = {
+static struct device_operations ac97modem_ops = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-//	.enable           = ck804_enable,
+	// .enable        = ck804_enable,
 	.init             = 0,
 	.scan_bus         = 0,
 	.ops_pci          = &lops_pci,

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@
  * Copyright 2004 Tyan Computer
  *  by yhlu at tyan.com
  */
+
 static int set_ht_link_ck804(uint8_t ht_c_num)
 {
 	unsigned vendorid = 0x10de;
@@ -9,10 +10,10 @@
 	return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
 }
 
-static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
+static void setup_ss_table(unsigned index, unsigned where, unsigned control,
+			   const unsigned int *register_values, int max)
 {
 	int i;
-
 	unsigned val;
 
 	val = inl(control);
@@ -21,7 +22,7 @@
 
 	outl(0, index);
 
-	for(i = 0; i < max; i++) {
+	for (i = 0; i < max; i++) {
 		unsigned long reg;
 		reg = register_values[i];
 		outl(reg, where);
@@ -29,67 +30,61 @@
 	val = inl(control);
 	val |= 1;
 	outl(val, control);
-
 }
 
 #define ANACTRL_IO_BASE 0x7000
 #define ANACTRL_REG_POS 0x68
 
-
 #define SYSCTRL_IO_BASE 0x6000
 #define SYSCTRL_REG_POS 0x64
 
 /*
-	16 1 1 2 :0
-	 8 8 2 2 :1
-	 8 8 4   :2
-	 8 4 4 4 :3
-	16 4     :4
+ *	16 1 1 2 :0
+ *	 8 8 2 2 :1
+ *	 8 8 4   :2
+ *	 8 4 4 4 :3
+ *	16 4     :4
 */
 
 #ifndef CK804_PCI_E_X
-	#define CK804_PCI_E_X 4
+#define CK804_PCI_E_X 4
 #endif
 
 #if CK804_NUM > 1
-	#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE+0x8000)
-	#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE+0x8000)
-
-	#ifndef CK804B_BUSN
-		#define CK804B_BUSN 0x80
-	#endif
-
-	#ifndef CK804B_PCI_E_X
-		#define CK804B_PCI_E_X 4
-	#endif
+#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000)
+#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000)
+#ifndef CK804B_BUSN
+#define CK804B_BUSN 0x80
 #endif
+#ifndef CK804B_PCI_E_X
+#define CK804B_PCI_E_X 4
+#endif
+#endif
 
 #ifndef CK804_USE_NIC
-	#define CK804_USE_NIC 0
+#define CK804_USE_NIC 0
 #endif
 
 #ifndef CK804_USE_ACI
-	#define CK804_USE_ACI 0
+#define CK804_USE_ACI 0
 #endif
 
 #define CK804_CHIP_REV 3
 
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-	#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
+#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
 #else
-	#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
 #endif
 
 #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
-	#define CK804B_DEVN_BASE 1
+#define CK804B_DEVN_BASE 1
 #else
-	#define CK804B_DEVN_BASE CK804_DEVN_BASE
+#define CK804B_DEVN_BASE CK804_DEVN_BASE
 #endif
 
-
 static void ck804_early_set_port(void)
 {
-
 	static const unsigned int ctrl_devport_conf[] = {
 		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
 #if CK804_NUM > 1
@@ -103,12 +98,10 @@
 	};
 
 	setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf));
-
 }
 
 static void ck804_early_clear_port(void)
 {
-
 	static const unsigned int ctrl_devport_conf_clear[] = {
 		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
 #if CK804_NUM > 1
@@ -122,84 +115,70 @@
 	};
 
 	setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear));
-
 }
 
 static void ck804_early_setup(void)
 {
-
 	static const unsigned int ctrl_conf[] = {
 
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000,
 
-
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,
-
-
 #if CK804_NUM > 1
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
 #endif
 
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,
 
-
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
-
-
 #if CK804_NUM > 1
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,
 #endif
 
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,
 
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
-	RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
-
 #if CK804_NUM > 1
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
-	RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,
 #endif
 
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,
 
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
-
 #if CK804_NUM > 1
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,
 #endif
 
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100,
 
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
-
-
-
 #if CK804_NUM > 1
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff,
 #endif
 
-
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
@@ -208,139 +187,125 @@
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
 
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32),
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16),
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32),
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16),
 
 #if CK804_NUM > 1
-
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
-
 #endif
 
-
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
 #if CK804_NUM > 1
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
 #endif
 
-	// Activate master port on primary SATA controller
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x50), ~(0x1f000013), 0x15000013,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x64), ~(0x00000001), 0x00000001,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x68), ~(0x02000000), 0x02000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x70), ~(0x000f0000), 0x00040000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xa0), ~(0x000001ff), 0x00000150,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x7c), ~(0x00000010), 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xd0), ~(0xf0000000), 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xe0), ~(0xf0000000), 0x00000000,
+	/* Activate master port on primary SATA controller. */
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x50), ~(0x1f000013), 0x15000013,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x64), ~(0x00000001), 0x00000001,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x68), ~(0x02000000), 0x02000000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x70), ~(0x000f0000), 0x00040000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xa0), ~(0x000001ff), 0x00000150,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x7c), ~(0x00000010), 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xd0), ~(0xf0000000), 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xe0), ~(0xf0000000), 0x00000000,
 
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,
 #if  CK804_NUM > 1
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
-
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,
 #endif
 
-
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
 #if CK804_NUM > 1
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
+	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
 #endif
 
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
 #if CK804_NUM > 1
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
+	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
 #endif
 
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
 
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8),
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),
 #if CK804_NUM > 1
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8),
+	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
 #endif
 
-
-
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
 #if CK804_USE_NIC == 1
-	RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
+	RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23),
 #endif
 
 #if CK804_USE_ACI == 1
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
 #endif
 
 #if CK804_NUM > 1
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2),
 #endif
 
-
 #if CK804_NUM > 1
-	#if CK804_USE_NIC == 1
-		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
-		RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
-		RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
-		RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
-		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
-	#endif
+#if CK804_USE_NIC == 1
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
+	RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
+	RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
+	RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
+	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23),
 #endif
+#endif
 
-
-
 #ifdef CK804_MB_SETUP
 	CK804_MB_SETUP
 #endif
-
 	};
 
-
-
 	setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf));
 
-	setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
-	setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
-	setup_ss_table(ANACTRL_IO_BASE+0xc0, ANACTRL_IO_BASE+0xc4, ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
+	setup_ss_table(ANACTRL_IO_BASE + 0x40, ANACTRL_IO_BASE + 0x44, ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64);
+	setup_ss_table(ANACTRL_IO_BASE + 0xb0, ANACTRL_IO_BASE + 0xb4, ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64);
+	setup_ss_table(ANACTRL_IO_BASE + 0xc0, ANACTRL_IO_BASE + 0xc4, ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64);
 
 #if CK804_NUM > 1
-	setup_ss_table(CK804B_ANACTRL_IO_BASE+0x40, CK804B_ANACTRL_IO_BASE+0x44, CK804B_ANACTRL_IO_BASE+0x48, pcie_ss_tbl,64);
-	setup_ss_table(CK804B_ANACTRL_IO_BASE+0xb0, CK804B_ANACTRL_IO_BASE+0xb4, CK804B_ANACTRL_IO_BASE+0xb8, sata_ss_tbl,64);
-	setup_ss_table(CK804B_ANACTRL_IO_BASE+0xc0, CK804B_ANACTRL_IO_BASE+0xc4, CK804B_ANACTRL_IO_BASE+0xc8, cpu_ss_tbl,64);
+	setup_ss_table(CK804B_ANACTRL_IO_BASE + 0x40, CK804B_ANACTRL_IO_BASE + 0x44, CK804B_ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64);
+	setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xb0, CK804B_ANACTRL_IO_BASE + 0xb4, CK804B_ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64);
+	setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64);
 #endif
 
 #if 0
 	dump_io_resources(ANACTRL_IO_BASE);
 	dump_io_resources(SYSCTRL_IO_BASE);
 #endif
-
 }
 
 static int ck804_early_setup_x(void)
@@ -369,4 +334,3 @@
 	outb(0x06, 0x0cf9);
 #endif
 }
-

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -11,365 +11,339 @@
 	return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
 }
 
-static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
+static void setup_ss_table(unsigned index, unsigned where, unsigned control,
+			   const unsigned int *register_values, int max)
 {
 	int i;
-
 	unsigned val;
+
 	val = inl(control);
 	val &= 0xfffffffe;
 	outl(val, control);
 
 	outl(0, index);
 
-	for(i = 0; i < max; i++) {
+	for (i = 0; i < max; i++) {
 		unsigned long reg;
-
 		reg = register_values[i];
 		outl(reg, where);
 	}
+
 	val = inl(control);
 	val |= 1;
 	outl(val, control);
-
 }
 
 #define ANACTRL_IO_BASE 0x3000
 #define ANACTRL_REG_POS 0x68
 
-
 #define SYSCTRL_IO_BASE 0x2000
 #define SYSCTRL_REG_POS 0x64
 
 /*
-	16 1 1 2 :0
-	 8 8 2 2 :1
-	 8 8 4   :2
-	 8 4 4 4 :3
-	16 4     :4
+ *	16 1 1 2 :0
+ *	 8 8 2 2 :1
+ *	 8 8 4   :2
+ *	 8 4 4 4 :3
+ *	16 4     :4
 */
 
 #ifndef CK804_PCI_E_X
-	#define CK804_PCI_E_X 4
+#define CK804_PCI_E_X 4
 #endif
 
-	/* we will use the offset in setup_resource_map_x_offset and setup_resource_map_offset */
-	#define CK804B_ANACTRL_IO_BASE 0x3000
-	#define CK804B_SYSCTRL_IO_BASE 0x2000
+/*
+ * We will use the offset in setup_resource_map_x_offset and
+ * setup_resource_map_offset.
+ */
+#define CK804B_ANACTRL_IO_BASE 0x3000
+#define CK804B_SYSCTRL_IO_BASE 0x2000
 
-	#ifdef CK804B_BUSN
-		#undef CK804B_BUSN
-	#endif
-	#define CK804B_BUSN 0x0
+#ifdef CK804B_BUSN
+#undef CK804B_BUSN
+#endif
+#define CK804B_BUSN 0x0
 
-	#ifndef CK804B_PCI_E_X
-		#define CK804B_PCI_E_X 4
-	#endif
+#ifndef CK804B_PCI_E_X
+#define CK804B_PCI_E_X 4
+#endif
 
 #ifndef CK804_USE_NIC
-	#define CK804_USE_NIC 0
+#define CK804_USE_NIC 0
 #endif
 
 #ifndef CK804_USE_ACI
-	#define CK804_USE_ACI 0
+#define CK804_USE_ACI 0
 #endif
 
 #define CK804_CHIP_REV 3
 
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-	#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
+#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
 #else
-	#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
 #endif
 
 #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
-	#define CK804B_DEVN_BASE 1
+#define CK804B_DEVN_BASE 1
 #else
-	#define CK804B_DEVN_BASE CK804_DEVN_BASE
+#define CK804B_DEVN_BASE CK804_DEVN_BASE
 #endif
 
-static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, unsigned *io_base)
+static void ck804_early_set_port(unsigned ck804_num, unsigned *busn,
+				 unsigned *io_base)
 {
-
 	static const unsigned int ctrl_devport_conf[] = {
-		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
-		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
+		PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
+		PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
 	};
 
 	static const unsigned int ctrl_devport_conf_b[] = {
-		PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
-		PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
+		PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
+		PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
 	};
 
 	int j;
-	for(j = 0; j < ck804_num; j++ ) {
-		if(busn[j]==0) { //sb chain
+	for (j = 0; j < ck804_num; j++) {
+		if (busn[j] == 0) {	//sb chain
 			setup_resource_map_offset(ctrl_devport_conf,
 				ARRAY_SIZE(ctrl_devport_conf),
-				PCI_DEV(busn[j], 0, 0) , io_base[j]);
+				PCI_DEV(busn[j], 0, 0), io_base[j]);
 			continue;
 		}
 		setup_resource_map_offset(ctrl_devport_conf_b,
-			ARRAY_SIZE(ctrl_devport_conf_b),
-			PCI_DEV(busn[j], 0, 0) , io_base[j]);
+					  ARRAY_SIZE(ctrl_devport_conf_b),
+					  PCI_DEV(busn[j], 0, 0), io_base[j]);
 	}
 }
 
-static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, unsigned *io_base)
+static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn,
+				   unsigned *io_base)
 {
-
 	static const unsigned int ctrl_devport_conf_clear[] = {
-		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
-		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
+		PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
+		PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
 	};
 
 	static const unsigned int ctrl_devport_conf_clear_b[] = {
-		PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
-		PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
+		PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
+		PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
 	};
 
 	int j;
-	for(j = 0; j < ck804_num; j++ ) {
-		if(busn[j]==0) { //sb chain
+	for (j = 0; j < ck804_num; j++) {
+		if (busn[j] == 0) {	//sb chain
 			setup_resource_map_offset(ctrl_devport_conf_clear,
 				ARRAY_SIZE(ctrl_devport_conf_clear),
-				PCI_DEV(busn[j], 0, 0) , io_base[j]);
+				PCI_DEV(busn[j], 0, 0), io_base[j]);
 			continue;
 		}
 		setup_resource_map_offset(ctrl_devport_conf_clear_b,
-			ARRAY_SIZE(ctrl_devport_conf_clear_b),
-			PCI_DEV(busn[j], 0, 0) , io_base[j]);
+					  ARRAY_SIZE(ctrl_devport_conf_clear_b),
+					  PCI_DEV(busn[j], 0, 0), io_base[j]);
 	}
-
-
 }
 
-
-static void ck804_early_setup(unsigned ck804_num, unsigned *busn, unsigned *io_base)
+static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
+			      unsigned *io_base)
 {
-
 	static const unsigned int ctrl_conf_master[] = {
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000,
 
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,
 
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,
 
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,
 
-
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
-	RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
-
-
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
-
-
 #ifdef CK804_MB_SETUP
-	CK804_MB_SETUP
+		CK804_MB_SETUP
 #endif
-
-
 #if CK804_NUM > 1
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
-
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100,
 #endif
 
 #if CK804_NUM == 1
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
-
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100,
 #endif
 
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
 
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32),
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16),
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32),
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16),
 
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
 
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,
 
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
 
+// PANTA	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
 
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
 
-//PANTA		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),
 
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
-
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8),
-
-
 //SYSCTRL
-
-
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
 #if CK804_USE_NIC == 1
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
-	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
+		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23),
 #endif
 
 #if CK804_USE_ACI == 1
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
 #endif
 
 #if CK804_NUM > 1
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2),
 #endif
-
-
 	};
 
-
-
-
 	static const unsigned int ctrl_conf_slave[] = {
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
 
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,
 
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,
 
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,
 
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff,
 
+		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
+		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
+		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
+		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
+		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
+		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
 
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
-	RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
+		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
 
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,
 
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,
+		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
 
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
+//PANTA		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
 
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
+		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
 
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
-	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
+		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
 
-
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
-
-//PANTA		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
-
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
-
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8),
-
-	#if CK804_USE_NIC == 1
-		RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
-		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
-		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
-		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
-		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
-	#endif
-
+#if CK804_USE_NIC == 1
+		RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE + 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
+		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
+		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23),
+#endif
 	};
 
 	int j;
-
-	for(j=0; j<ck804_num; j++) {
-		if(busn[j] == 0) {
-			setup_resource_map_x_offset(ctrl_conf_master, ARRAY_SIZE(ctrl_conf_master),
-				PCI_DEV(busn[0],0,0), io_base[0]);
+	for (j = 0; j < ck804_num; j++) {
+		if (busn[j] == 0) {
+			setup_resource_map_x_offset(ctrl_conf_master,
+				ARRAY_SIZE(ctrl_conf_master),
+				PCI_DEV(busn[0], 0, 0), io_base[0]);
 			continue;
 		}
 
-
-		setup_resource_map_x_offset(ctrl_conf_slave, ARRAY_SIZE(ctrl_conf_slave),
-			PCI_DEV(busn[j],0,0), io_base[j]);
+		setup_resource_map_x_offset(ctrl_conf_slave,
+					    ARRAY_SIZE(ctrl_conf_slave),
+					    PCI_DEV(busn[j], 0, 0), io_base[j]);
 	}
 
-	for(j=0; j< ck804_num; j++) {
-		// PCI-E (XSPLL) SS table 0x40, x044, 0x48
-		// SATA  (SPPLL) SS table 0xb0, 0xb4, 0xb8
-		// CPU   (PPLL)  SS table 0xc0, 0xc4, 0xc8
-		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,
-			io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
-		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,
-			io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
-//PANTA		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
-//			io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
+	for (j = 0; j < ck804_num; j++) {
+		/* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */
+		/* SATA  (SPPLL) SS table 0xb0, 0xb4, 0xb8 */
+		/* CPU   (PPLL)  SS table 0xc0, 0xc4, 0xc8 */
+		setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40,
+			       io_base[j] + ANACTRL_IO_BASE + 0x44,
+			       io_base[j] + ANACTRL_IO_BASE + 0x48,
+			       pcie_ss_tbl, 64);
+		setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0,
+			       io_base[j] + ANACTRL_IO_BASE + 0xb4,
+			       io_base[j] + ANACTRL_IO_BASE + 0xb8,
+			       sata_ss_tbl, 64);
+//PANTA         setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0,
+//			       io_base[j] + ANACTRL_IO_BASE + 0xc4,
+//			       io_base[j] + ANACTRL_IO_BASE + 0xc8,
+//			       cpu_ss_tbl, 64);
 	}
-
-
 }
 
 static int ck804_early_setup_x(void)
 {
-	unsigned busn[4];
-	unsigned io_base[4];
-	int ck804_num = 0;
-	int i;
+	unsigned busn[4], io_base[4];
+	int i, ck804_num = 0;
 
-	for(i=0;i<4;i++) {
+	for (i = 0; i < 4; i++) {
 		uint32_t id;
 		device_t dev;
-		if(i == 0) { // SB chain
-			dev = PCI_DEV(i*0x40, CK804_DEVN_BASE, 0);
-		}
-		else {
-			dev = PCI_DEV(i*0x40, CK804B_DEVN_BASE, 0);
-		}
+		if (i == 0) // SB chain
+			dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0);
+		else
+			dev = PCI_DEV(i * 0x40, CK804B_DEVN_BASE, 0);
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
-		if(id == 0x005e10de) {
+		if (id == 0x005e10de) {
 			busn[ck804_num] = i * 0x40;
 			io_base[ck804_num] = i * 0x4000;
 			ck804_num++;
@@ -379,6 +353,7 @@
 	ck804_early_set_port(ck804_num, busn, io_base);
 	ck804_early_setup(ck804_num, busn, io_base);
 	ck804_early_clear_port(ck804_num, busn, io_base);
+
 	return set_ht_link_ck804(4);
 }
 
@@ -399,4 +374,3 @@
 	outb(0x02, 0x0cf9);
 	outb(0x06, 0x0cf9);
 }
-

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h	2008-10-02 18:19:17 UTC (rev 3631)
@@ -69,6 +69,7 @@
 	0x0C5042040,
 	0x0C5042040,
 };
+
 static const unsigned int sata_ss_tbl[] = {
 	0x0c9044042,
 	0x0c9044042,
@@ -202,5 +203,3 @@
 	0x0C5039037,
 	0x0C5039037,
 };
-
-

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_smbus.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_smbus.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -11,16 +11,18 @@
 {
 	device_t dev;
 	dev = pci_locate_device(PCI_ID(0x10de, 0x0052), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\r\n");
-	}
+	if (dev == PCI_DEV_INVALID)
+		die("SMBus controller not found\r\n");
 
 	print_debug("SMBus controller enabled\r\n");
-	/* set smbus iobase */
+
+	/* Set SMBus I/O base. */
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
-	/* Set smbus iospace enable */
+
+	/* Set SMBus I/O space enable. */
 	pci_write_config16(dev, 0x4, 0x01);
-	/* clear any lingering errors, so the transaction will run */
+
+	/* Clear any lingering errors, so the transaction will run. */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 }
 
@@ -28,7 +30,9 @@
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
-static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+
+static int smbus_write_byte(unsigned device, unsigned address,
+			    unsigned char val)
 {
 	return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
 }

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_enable_rom.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_enable_rom.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_enable_rom.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,10 +2,11 @@
  * Copyright 2004 Tyan Computer
  *  by yhlu at tyan.com
  */
+
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-	#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
+#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
 #else
-	#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
 #endif
 
 static void ck804_enable_rom(void)
@@ -13,11 +14,11 @@
 	unsigned char byte;
 	device_t addr;
 
-	/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
-	/* Locate the ck804 LPC */
-	addr = PCI_DEV(0, (CK804_DEVN_BASE+1), 0);
+	/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
+	/* Locate the ck804 LPC. */
+	addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0);
 
-	/* Set the 4MB enable bit bit */
+	/* Set the 4MB enable bit. */
 	byte = pci_read_config8(addr, 0x88);
 	byte |= 0x80;
 	pci_write_config8(addr, 0x88, byte);

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ht.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ht.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ht.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@
  * Copyright 2004 Tyan Computer
  *  by yhlu at tyan.com
  */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -12,13 +13,14 @@
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, 0x40,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
+
 static struct pci_operations lops_pci = {
 	.set_subsystem = lpci_set_subsystem,
 };
 
-static struct device_operations ht_ops  = {
+static struct device_operations ht_ops = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
@@ -32,4 +34,3 @@
 	.vendor = PCI_VENDOR_ID_NVIDIA,
 	.device = PCI_DEVICE_ID_NVIDIA_CK804_HT,
 };
-

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -13,61 +13,61 @@
 static void ide_init(struct device *dev)
 {
 	struct southbridge_nvidia_ck804_config *conf;
-	/* Enable ide devices so the linux ide driver will work */
 	uint32_t dword;
 	uint16_t word;
 	uint8_t byte;
+
 	conf = dev->chip_info;
 
 	word = pci_read_config16(dev, 0x50);
-	/* Ensure prefetch is disabled */
+	/* Ensure prefetch is disabled. */
 	word &= ~((1 << 15) | (1 << 13));
 	if (conf->ide1_enable) {
-		/* Enable secondary ide interface */
-		word |= (1<<0);
+		/* Enable secondary IDE interface. */
+		word |= (1 << 0);
 		printk_debug("IDE1 \t");
 	}
 	if (conf->ide0_enable) {
-		/* Enable primary ide interface */
-		word |= (1<<1);
+		/* Enable primary IDE interface. */
+		word |= (1 << 1);
 		printk_debug("IDE0\n");
 	}
 
-	word |= (1<<12);
-	word |= (1<<14);
+	word |= (1 << 12);
+	word |= (1 << 14);
 
 	pci_write_config16(dev, 0x50, word);
 
-
-	byte = 0x20 ; // Latency: 64-->32
+	byte = 0x20;		/* Latency: 64 --> 32 */
 	pci_write_config8(dev, 0xd, byte);
 
 	dword = pci_read_config32(dev, 0xf8);
 	dword |= 12;
 	pci_write_config32(dev, 0xf8, dword);
+
 #if CONFIG_PCI_ROM_RUN == 1
 	pci_dev_init(dev);
 #endif
-
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, 0x40,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
+
 static struct pci_operations lops_pci = {
 	.set_subsystem = lpci_set_subsystem,
 };
 
-static struct device_operations ide_ops  = {
+static struct device_operations ide_ops = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init	     = ide_init,
-	.scan_bus	 = 0,
-//	.enable	   = ck804_enable,
-	.ops_pci	  = &lops_pci,
+	.init             = ide_init,
+	.scan_bus         = 0,
+	// .enable        = ck804_enable,
+	.ops_pci          = &lops_pci,
 };
 
 static const struct pci_driver ide_driver __pci_driver = {
@@ -75,4 +75,3 @@
 	.vendor = PCI_VENDOR_ID_NVIDIA,
 	.device = PCI_DEVICE_ID_NVIDIA_CK804_IDE,
 };
-

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -4,6 +4,7 @@
  *  by yhlu at tyan.com
  *  2006.1 yhlu add dest apicid for IRQ0
  */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -44,30 +45,30 @@
 #define INT		(1 << 8)
 	/* IO-APIC virtual wire mode configuration */
 	/* mask, trigger, polarity, destination, delivery, vector */
-	{   0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
-	{   1, DISABLED, NONE},
-	{   2, DISABLED, NONE},
-	{   3, DISABLED, NONE},
-	{   4, DISABLED, NONE},
-	{   5, DISABLED, NONE},
-	{   6, DISABLED, NONE},
-	{   7, DISABLED, NONE},
-	{   8, DISABLED, NONE},
-	{   9, DISABLED, NONE},
-	{  10, DISABLED, NONE},
-	{  11, DISABLED, NONE},
-	{  12, DISABLED, NONE},
-	{  13, DISABLED, NONE},
-	{  14, DISABLED, NONE},
-	{  15, DISABLED, NONE},
-	{  16, DISABLED, NONE},
-	{  17, DISABLED, NONE},
-	{  18, DISABLED, NONE},
-	{  19, DISABLED, NONE},
-	{  20, DISABLED, NONE},
-	{  21, DISABLED, NONE},
-	{  22, DISABLED, NONE},
-	{  23, DISABLED, NONE},
+	{0,  ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
+	{1,  DISABLED, NONE},
+	{2,  DISABLED, NONE},
+	{3,  DISABLED, NONE},
+	{4,  DISABLED, NONE},
+	{5,  DISABLED, NONE},
+	{6,  DISABLED, NONE},
+	{7,  DISABLED, NONE},
+	{8,  DISABLED, NONE},
+	{9,  DISABLED, NONE},
+	{10, DISABLED, NONE},
+	{11, DISABLED, NONE},
+	{12, DISABLED, NONE},
+	{13, DISABLED, NONE},
+	{14, DISABLED, NONE},
+	{15, DISABLED, NONE},
+	{16, DISABLED, NONE},
+	{17, DISABLED, NONE},
+	{18, DISABLED, NONE},
+	{19, DISABLED, NONE},
+	{20, DISABLED, NONE},
+	{21, DISABLED, NONE},
+	{22, DISABLED, NONE},
+	{23, DISABLED, NONE},
 	/* Be careful and don't write past the end... */
 };
 
@@ -75,23 +76,22 @@
 {
 	int i;
 	unsigned long value_low, value_high;
-//	unsigned long ioapic_base = 0xfec00000;
+	/* unsigned long ioapic_base = 0xfec00000; */
 	volatile unsigned long *l;
 	struct ioapicreg *a = ioapicregvalues;
 
-	ioapicregvalues[0].value_high = lapicid()<<(56-32);
+	ioapicregvalues[0].value_high = lapicid() << (56 - 32);
 
-	l = (unsigned long *) ioapic_base;
+	l = (unsigned long *)ioapic_base;
 
-	for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
-	     i++, a++) {
+	for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) {
 		l[0] = (a->reg * 2) + 0x10;
 		l[4] = a->value_low;
 		value_low = l[4];
-		l[0] = (a->reg *2) + 0x11;
+		l[0] = (a->reg * 2) + 0x11;
 		l[4] = a->value_high;
 		value_high = l[4];
-		if ((i==0) && (value_low == 0xffffffff)) {
+		if ((i == 0) && (value_low == 0xffffffff)) {
 			printk_warning("IO APIC not responding.\n");
 			return;
 		}
@@ -117,20 +117,19 @@
 	uint8_t byte;
 	uint32_t dword;
 
-	/* IO APIC initialization */
+	/* I/O APIC initialization */
 	byte = pci_read_config8(dev, 0x74);
-	byte |= (1<<0); // enable APIC
+	byte |= (1 << 0);	/* Enable APIC. */
 	pci_write_config8(dev, 0x74, byte);
-	dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
+	dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1);	/* 0x14 */
 
 	setup_ioapic(dword);
 
 #if 1
 	dword = pci_read_config32(dev, 0xe4);
-	dword |= (1<<23);
+	dword |= (1 << 23);
 	pci_write_config32(dev, 0xe4, dword);
 #endif
-
 }
 
 static void lpc_slave_init(device_t dev)
@@ -138,132 +137,123 @@
 	lpc_common_init(dev);
 }
 
-static void rom_dummy_write(device_t dev){
+static void rom_dummy_write(device_t dev)
+{
 	uint8_t old, new;
 	uint8_t *p;
 
 	old = pci_read_config8(dev, 0x88);
 	new = old | 0xc0;
-	if (new != old) {
+	if (new != old)
 		pci_write_config8(dev, 0x88, new);
-	}
-	//  enable write
+	/* Enable write. */
 	old = pci_read_config8(dev, 0x6d);
 	new = old | 0x01;
-	if (new != old) {
+	if (new != old)
 		pci_write_config8(dev, 0x6d, new);
-	}
 
-	/* dummy write */
-	p = (uint8_t *)0xffffffe0;
+	/* Dummy write. */
+	p = (uint8_t *) 0xffffffe0;
 	old = 0;
 	*p = old;
 	old = *p;
 
-	//  disable write
+	/* Disable write. */
 	old = pci_read_config8(dev, 0x6d);
 	new = old & 0xfe;
-	if (new != old) {
+	if (new != old)
 		pci_write_config8(dev, 0x6d, new);
-
-	}
-
 }
+
 #if 0
 static void enable_hpet(struct device *dev)
 {
 	unsigned long hpet_address;
 
-	pci_write_config32(dev,0x44, 0xfed00001);
-	hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
-	printk_debug("enabling HPET @0x%x\n", hpet_address);
+	pci_write_config32(dev, 0x44, 0xfed00001);
+	hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
+	printk_debug("Enabling HPET @0x%x\n", hpet_address);
 }
 #endif
 
 static void lpc_init(device_t dev)
 {
-	uint8_t byte;
-	uint8_t byte_old;
-	int on;
-	int nmi_option;
+	uint8_t byte, byte_old;
+	int on, nmi_option;
 
 	lpc_common_init(dev);
 
 #if CK804_CHIP_REV==1
-	if(dev->bus->secondary!=1) return;
+	if (dev->bus->secondary != 1)
+		return;
 #endif
 
 #if 0
-	/* posted memory write enable */
+	/* Posted memory write enable */
 	byte = pci_read_config8(dev, 0x46);
-	pci_write_config8(dev, 0x46, byte | (1<<0));
-
+	pci_write_config8(dev, 0x46, byte | (1 << 0));
 #endif
-	/* power after power fail */
 
+	/* power after power fail */
 	on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 	get_option(&on, "power_on_after_fail");
 	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 	byte &= ~0x40;
-	if (!on) {
+	if (!on)
 		byte |= 0x40;
-	}
 	pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
-	printk_info("set power %s after power fail\n", on?"on":"off");
+	printk_info("set power %s after power fail\n", on ? "on" : "off");
 
-	/* Throttle the CPU speed down for testing */
+	/* Throttle the CPU speed down for testing. */
 	on = SLOW_CPU_OFF;
 	get_option(&on, "slow_cpu");
-	if(on) {
+	if (on) {
 		uint16_t pm10_bar;
 		uint32_t dword;
-		pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
-		outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
+		pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00);
+		outl(((on << 1) + 0x10), (pm10_bar + 0x10));
 		dword = inl(pm10_bar + 0x10);
-		on = 8-on;
+		on = 8 - on;
 		printk_debug("Throttling CPU %2d.%1.1d percent.\n",
-				(on*12)+(on>>1),(on&1)*5);
+			     (on * 12) + (on >> 1), (on & 1) * 5);
 	}
-
 #if 0
 // default is enabled
-	/* Enable Port 92 fast reset */
+	/* Enable Port 92 fast reset. */
 	byte = pci_read_config8(dev, 0xe8);
 	byte |= ~(1 << 3);
 	pci_write_config8(dev, 0xe8, byte);
 #endif
 
-	/* Enable Error reporting */
-	/* Set up sync flood detected */
+	/* Enable Error reporting. */
+	/* Set up sync flood detected. */
 	byte = pci_read_config8(dev, 0x47);
 	byte |= (1 << 1);
 	pci_write_config8(dev, 0x47, byte);
 
-	/* Set up NMI on errors */
-	byte = inb(0x70); // RTC70
+	/* Set up NMI on errors. */
+	byte = inb(0x70);		/* RTC70 */
 	byte_old = byte;
 	nmi_option = NMI_OFF;
 	get_option(&nmi_option, "nmi");
 	if (nmi_option) {
-		byte &= ~(1 << 7); /* set NMI */
+		byte &= ~(1 << 7); /* Set NMI. */
 	} else {
-		byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
+		byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
 	}
-	if( byte != byte_old) {
+	if (byte != byte_old)
 		outb(0x70, byte);
-	}
 
-	/* Initialize the real time clock */
+	/* Initialize the real time clock (RTC). */
 	rtc_init(0);
 
-	/* Initialize isa dma */
+	/* Initialize ISA DMA. */
 	isa_dma_init();
 
-	/* Initialize the High Precision Event Timers */
-//	enable_hpet(dev);
+	/* Initialize the High Precision Event Timers (HPET). */
+	/* enable_hpet(dev); */
 
 	rom_dummy_write(dev);
-
 }
 
 static void ck804_lpc_read_resources(device_t dev)
@@ -271,43 +261,43 @@
 	struct resource *res;
 	unsigned long index;
 
-	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
+	/* Get the normal PCI resources of this device. */
+	/* We got one for APIC, or one more for TRAP. */
+	pci_dev_read_resources(dev);
 
-	/* Get Resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL */
-	for (index = 0x60; index <= 0x68; index+=4) { // We got another 3.
+	/* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */
+	for (index = 0x60; index <= 0x68; index += 4)	/* We got another 3. */
 		pci_get_resource(dev, index);
-	}
 	compact_resources(dev);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->flags =
+	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
+	res->flags =
+	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 }
 
 /**
- * @brief Enable resources for children devices
+ * Enable resources for children devices.
  *
- * @param dev the device whos children's resources are to be enabled
- *
- * This function is call by the global enable_resources() indirectly via the
+ * This function is called by the global enable_resources() indirectly via the
  * device_operation::enable_resources() method of devices.
  *
  * Indirect mutual recursion:
  *      enable_childrens_resources() -> enable_resources()
  *      enable_resources() -> device_operation::enable_resources()
  *      device_operation::enable_resources() -> enable_children_resources()
+ *
+ * @param dev The device whose children's resources are to be enabled.
  */
 static void ck804_lpc_enable_childrens_resources(device_t dev)
 {
 	unsigned link;
 	uint32_t reg, reg_var[4];
-	int i;
-	int var_num = 0;
+	int i, var_num = 0;
 
 	reg = pci_read_config32(dev, 0xa0);
 
@@ -315,44 +305,49 @@
 		device_t child;
 		for (child = dev->link[link].children; child; child = child->sibling) {
 			enable_resources(child);
-			if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
-				for(i=0;i<child->resources;i++) {
+			if (child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
+				for (i = 0; i < child->resources; i++) {
 					struct resource *res;
-					unsigned long base, end; // don't need long long
+					unsigned long base, end;	// don't need long long
 					res = &child->resource[i];
-					if(!(res->flags & IORESOURCE_IO)) continue;
+					if (!(res->flags & IORESOURCE_IO))
+						continue;
 					base = res->base;
 					end = resource_end(res);
-					printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end);
-					switch(base) {
-					case 0x3f8: // COM1
-						reg |= (1<<0); 	break;
-					case 0x2f8: // COM2
-						reg |= (1<<1);  break;
-					case 0x378: // Parallal 1
-						reg |= (1<<24); break;
-					case 0x3f0: // FD0
-						reg |= (1<<20); break;
-					case 0x220:  // Aduio 0
-						reg |= (1<<8); 	break;
-					case 0x300:  // Midi 0
-						reg |= (1<<12);	break;
+					printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n", dev_path(child), base, end);
+					switch (base) {
+					case 0x3f8:	// COM1
+						reg |= (1 << 0);
+						break;
+					case 0x2f8:	// COM2
+						reg |= (1 << 1);
+						break;
+					case 0x378:	// Parallel 1
+						reg |= (1 << 24);
+						break;
+					case 0x3f0:	// FD0
+						reg |= (1 << 20);
+						break;
+					case 0x220:	// Audio 0
+						reg |= (1 << 8);
+						break;
+					case 0x300:	// Midi 0
+						reg |= (1 << 12);
+						break;
 					}
-					if( base == 0x290 || base >= 0x400) {
-						if(var_num>=4) continue; // only 4 var ; compact them ?
-						reg |= (1<<(28+var_num));
-						reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
+					if (base == 0x290 || base >= 0x400) {
+						if (var_num >= 4)
+							continue;	// only 4 var ; compact them ?
+						reg |= (1 << (28 + var_num));
+						reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16);
 					}
 				}
 			}
 		}
 	}
 	pci_write_config32(dev, 0xa0, reg);
-	for(i=0;i<var_num;i++) {
-		pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
-	}
-
-
+	for (i = 0; i < var_num; i++)
+		pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]);
 }
 
 static void ck804_lpc_enable_resources(device_t dev)
@@ -364,22 +359,23 @@
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, 0x40,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
 static struct pci_operations lops_pci = {
 	.set_subsystem = lpci_set_subsystem,
 };
 
-static struct device_operations lpc_ops  = {
+static struct device_operations lpc_ops = {
 	.read_resources   = ck804_lpc_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = ck804_lpc_enable_resources,
 	.init             = lpc_init,
 	.scan_bus         = scan_static_bus,
-//	.enable           = ck804_enable,
+	// .enable        = ck804_enable,
 	.ops_pci          = &lops_pci,
 };
+
 static const struct pci_driver lpc_driver __pci_driver = {
 	.ops    = &lpc_ops,
 	.vendor = PCI_VENDOR_ID_NVIDIA,
@@ -399,12 +395,12 @@
 	.device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
 };
 #else
-static struct device_operations lpc_slave_ops  = {
+static struct device_operations lpc_slave_ops = {
 	.read_resources   = ck804_lpc_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = lpc_slave_init,
-//	.enable           = ck804_enable,
+	// .enable        = ck804_enable,
 	.ops_pci          = &lops_pci,
 };
 

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@
  * Copyright 2004 Tyan Computer
  *  by yhlu at tyan.com
  */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/smbus.h>
@@ -11,21 +12,16 @@
 #include <arch/io.h>
 #include "ck804.h"
 
-
 static void nic_init(struct device *dev)
 {
-	uint32_t dword, old;
-	uint32_t mac_h, mac_l;
+	uint32_t dword, old, mac_h, mac_l;
 	int eeprom_valid = 0;
 	struct southbridge_nvidia_ck804_config *conf;
-
 	static uint32_t nic_index = 0;
-
 	uint8_t *base;
 	struct resource *res;
 
 	res = find_resource(dev, 0x10);
-
 	base = res->base;
 
 #define NvRegPhyInterface  0xC0
@@ -36,37 +32,37 @@
 	old = dword = pci_read_config32(dev, 0x30);
 	dword &= ~(0xf);
 	dword |= 0xf;
-	if(old != dword) {
-		pci_write_config32(dev, 0x30 , dword);
-	}
+	if (old != dword)
+		pci_write_config32(dev, 0x30, dword);
 
 	conf = dev->chip_info;
 
-	if(conf->mac_eeprom_smbus != 0) {
-//      read MAC address from EEPROM at first
+	if (conf->mac_eeprom_smbus != 0) {
+		/* Read MAC address from EEPROM at first. */
 		struct device *dev_eeprom;
-		dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
+		dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus,
+					   conf->mac_eeprom_addr);
 
-		if(dev_eeprom) {
-		//	if that is valid we will use that
+		if (dev_eeprom) {
+			/* If that is valid we will use that. */
 			unsigned char dat[6];
-			int status;
-			int i;
-			for(i=0;i<6;i++) {
+			int i, status;
+			for (i = 0; i < 6; i++) {
 				status = smbus_read_byte(dev_eeprom, i);
-				if(status < 0) break;
+				if (status < 0)
+					break;
 				dat[i] = status & 0xff;
 			}
-			if(status >= 0) {
+			if (status >= 0) {
 				mac_l = 0;
-				for(i=3;i>=0;i--) {
+				for (i = 3; i >= 0; i--) {
 					mac_l <<= 8;
 					mac_l += dat[i];
 				}
-				if(mac_l != 0xffffffff) {
+				if (mac_l != 0xffffffff) {
 					mac_l += nic_index;
 					mac_h = 0;
-					for(i=5;i>=4;i--) {
+					for (i = 5; i >= 4; i--) {
 						mac_h <<= 8;
 						mac_h += dat[i];
 					}
@@ -75,21 +71,22 @@
 			}
 		}
 	}
-//	if that is invalid we will read that from romstrap
-	if(!eeprom_valid) {
+
+	/* If that is invalid we will read that from romstrap. */
+	if (!eeprom_valid) {
 		unsigned long mac_pos;
-		mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
+		mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */
 		mac_l = readl(mac_pos) + nic_index;
 		mac_h = readl(mac_pos + 4);
 	}
 #if 1
-//      set that into NIC MMIO
+	/* Set that into NIC MMIO. */
 #define NvRegMacAddrA  0xA8
 #define NvRegMacAddrB  0xAC
 	writel(mac_l, base + NvRegMacAddrA);
 	writel(mac_h, base + NvRegMacAddrB);
 #else
-//	set that into NIC
+	/* Set that into NIC. */
 	pci_write_config32(dev, 0xa8, mac_l);
 	pci_write_config32(dev, 0xac, mac_h);
 #endif
@@ -97,35 +94,36 @@
 	nic_index++;
 
 #if CONFIG_PCI_ROM_RUN == 1
-	pci_dev_init(dev);// it will init option rom
+	pci_dev_init(dev);	/* It will init Option ROM. */
 #endif
-
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, 0x40,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
 static struct pci_operations lops_pci = {
 	.set_subsystem = lpci_set_subsystem,
 };
 
-static struct device_operations nic_ops  = {
+static struct device_operations nic_ops = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = nic_init,
 	.scan_bus         = 0,
-//	.enable           = ck804_enable,
+	// .enable        = ck804_enable,
 	.ops_pci          = &lops_pci,
 };
+
 static const struct pci_driver nic_driver __pci_driver = {
 	.ops    = &nic_ops,
 	.vendor = PCI_VENDOR_ID_NVIDIA,
 	.device = PCI_DEVICE_ID_NVIDIA_CK804_NIC,
 };
+
 static const struct pci_driver nic_bridge_driver __pci_driver = {
 	.ops    = &nic_ops,
 	.vendor = PCI_VENDOR_ID_NVIDIA,

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -12,70 +12,72 @@
 
 static void pci_init(struct device *dev)
 {
-
 	uint32_t dword;
 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 	device_t pci_domain_dev;
 	struct resource *mem1, *mem2;
 #endif
 
-	/* System error enable */
 	dword = pci_read_config32(dev, 0x04);
-	dword |= (1<<8); /* System error enable */
-	dword |= (1<<30); /* Clear possible errors */
+	dword |= (1 << 8);	/* System error enable */
+	dword |= (1 << 30);	/* Clear possible errors */
 	pci_write_config32(dev, 0x04, dword);
 
 #if 0
 	word = pci_read_config16(dev, 0x48);
-	word |= (1<<0); /* MRL2MRM */
-	word |= (1<<2); /* MR2MRM */
+	word |= (1 << 0);	/* MRL2MRM */
+	word |= (1 << 2);	/* MR2MRM */
 	pci_write_config16(dev, 0x48, word);
 #endif
 
 #if 1
 	dword = pci_read_config32(dev, 0x4c);
-	dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
+	dword |= 0x00440000;	/* TABORT_SER_ENABLE Park Last Enable. */
 	pci_write_config32(dev, 0x4c, dword);
 #endif
 
 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 	pci_domain_dev = dev->bus->dev;
-	while(pci_domain_dev) {
-		if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break;
+	while (pci_domain_dev) {
+		if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)
+			break;
 		pci_domain_dev = pci_domain_dev->bus->dev;
 	}
 
-	if(!pci_domain_dev) return; // impossiable
-	mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit
-	mem2 = find_resource(pci_domain_dev, 2); // mem
-	if(mem1->base > mem2->base) {
-		dword = mem2->base  & (0xffff0000UL);
+	if (!pci_domain_dev)
+		return;		/* Impossible */
+
+	mem1 = find_resource(pci_domain_dev, 1);	// prefmem, it could be 64bit
+	mem2 = find_resource(pci_domain_dev, 2);	// mem
+	if (mem1->base > mem2->base) {
+		dword = mem2->base & (0xffff0000UL);
 		printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base);
 	} else {
-		dword = mem1->base  & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base);
+		dword = mem1->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n",
+			     mem1->base);
 	}
 #else
 	dword = dev_root.resource[1].base & (0xffff0000UL);
-	printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base);
+	printk_debug("dev_root mem base = 0x%010Lx\n",
+		     dev_root.resource[1].base);
 #endif
 
 	printk_debug("[0x50] <-- 0x%08x\n", dword);
-	pci_write_config32(dev, 0x50, dword); //TOM
-
+	pci_write_config32(dev, 0x50, dword);	/* TOM */
 }
 
 static struct pci_operations lops_pci = {
 	.set_subsystem = 0,
 };
 
-static struct device_operations pci_ops  = {
+static struct device_operations pci_ops = {
 	.read_resources   = pci_bus_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_bus_enable_resources,
 	.init             = pci_init,
 	.scan_bus         = pci_scan_bridge,
-//	.enable           = ck804_enable,
+	// .enable        = ck804_enable,
 	.ops_pci          = &lops_pci,
 };
 
@@ -84,4 +86,3 @@
 	.vendor = PCI_VENDOR_ID_NVIDIA,
 	.device = PCI_DEVICE_ID_NVIDIA_CK804_PCI,
 };
-

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -12,29 +12,26 @@
 
 static void pcie_init(struct device *dev)
 {
-
-	/* Enable pci error detecting */
 	uint32_t dword;
 
-	/* System error enable */
+	/* Enable PCI error detecting. */
 	dword = pci_read_config32(dev, 0x04);
-	dword |= (1<<8); /* System error enable */
-	dword |= (1<<30); /* Clear possible errors */
+	dword |= (1 << 8);	/* System error enable */
+	dword |= (1 << 30);	/* Clear possible errors */
 	pci_write_config32(dev, 0x04, dword);
-
 }
 
 static struct pci_operations lops_pci = {
 	.set_subsystem = 0,
 };
 
-static struct device_operations pcie_ops  = {
+static struct device_operations pcie_ops = {
 	.read_resources   = pci_bus_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_bus_enable_resources,
 	.init             = pcie_init,
 	.scan_bus         = pci_scan_bridge,
-//	.enable           = ck804_enable,
+	// .enable        = ck804_enable,
 	.ops_pci          = &lops_pci,
 };
 
@@ -43,4 +40,3 @@
 	.vendor = PCI_VENDOR_ID_NVIDIA,
 	.device = PCI_DEVICE_ID_NVIDIA_CK804_PCI_E,
 };
-

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -15,7 +15,7 @@
 static void pci_write_config32(device_t dev, unsigned where, unsigned value)
 {
 	unsigned addr;
-	addr = (dev>>4) | where;
+	addr = (dev >> 4) | where;
 	outl(0x80000000 | (addr & ~3), 0xCF8);
 	outl(value, 0xCFC);
 }
@@ -23,7 +23,7 @@
 static unsigned pci_read_config32(device_t dev, unsigned where)
 {
 	unsigned addr;
-	addr = (dev>>4) | where;
+	addr = (dev >> 4) | where;
 	outl(0x80000000 | (addr & ~3), 0xCF8);
 	return inl(0xCFC);
 }
@@ -33,8 +33,7 @@
 void hard_reset(void)
 {
 	set_bios_reset();
-	/* Try rebooting through port 0xcf9 */
-	outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
-      	outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+	/* Try rebooting through port 0xcf9. */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
 }
-

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@
  * Copyright 2004 Tyan Computer
  *  by yhlu at tyan.com
  */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <delay.h>
@@ -10,7 +11,6 @@
 #include <device/pci_ops.h>
 #include "ck804.h"
 
-
 static void sata_com_reset(struct device *dev, unsigned reset)
 // reset = 1 : reset
 // reset = 0 : clear
@@ -23,12 +23,12 @@
 
 	printk_debug("base = %08x\r\n", base);
 
-	if(reset) {
-	        *(base + 4) = 0xffffffff;
-	        *(base + 0x44) = 0xffffffff;
+	if (reset) {
+		*(base + 4) = 0xffffffff;
+		*(base + 0x44) = 0xffffffff;
 	}
 
-	dword = *(base +8);
+	dword = *(base + 8);
 	dword &= ~(0xf);
 	dword |= reset;
 
@@ -42,87 +42,89 @@
 	*(base + 0x48) = dword;
 #endif
 
-	if(reset) return;
+	if (reset)
+		return;
 
-	dword = *(base+ 0);
-	printk_debug("*(base+0)=%08x\r\n",dword);
-	if(dword == 0x113) {
-		loop = 200000;// 2
+	dword = *(base + 0);
+	printk_debug("*(base+0)=%08x\r\n", dword);
+	if (dword == 0x113) {
+		loop = 200000;	// 2
 		do {
-		        dword = *(base + 4);
-			if((dword & 0x10000)!=0) break;
+			dword = *(base + 4);
+			if ((dword & 0x10000) != 0)
+				break;
 			udelay(10);
-		} while (--loop>0);
-		printk_debug("loop=%d, *(base+4)=%08x\r\n",loop,  dword);
+		} while (--loop > 0);
+		printk_debug("loop=%d, *(base+4)=%08x\r\n", loop, dword);
 	}
 
-	dword = *(base+ 0x40);
-	printk_debug("*(base+0x40)=%08x\r\n",dword);
-	if(dword == 0x113) {
-	        loop = 200000;//2
-	        do {
-		        dword = *(base + 0x44);
-		        if((dword & 0x10000)!=0) break;
+	dword = *(base + 0x40);
+	printk_debug("*(base+0x40)=%08x\r\n", dword);
+	if (dword == 0x113) {
+		loop = 200000;	//2
+		do {
+			dword = *(base + 0x44);
+			if ((dword & 0x10000) != 0)
+				break;
 			udelay(10);
-		} while (--loop>0);
-		printk_debug("loop=%d, *(base+0x44)=%08x\r\n",loop,  dword);
+		} while (--loop > 0);
+		printk_debug("loop=%d, *(base+0x44)=%08x\r\n", loop, dword);
 	}
 }
 
 static void sata_init(struct device *dev)
 {
-
 	uint32_t dword;
+	struct southbridge_nvidia_ck804_config *conf;
 
-	struct southbridge_nvidia_ck804_config *conf;
 	conf = dev->chip_info;
 
 	dword = pci_read_config32(dev, 0x50);
-	/* Ensure prefetch is disabled */
+	/* Ensure prefetch is disabled. */
 	dword &= ~((1 << 15) | (1 << 13));
 	if (conf->sata1_enable) {
-	        /* Enable secondary SATA interface */
-	        dword |= (1<<0);
-	        printk_debug("SATA S \t");
+		/* Enable secondary SATA interface. */
+		dword |= (1 << 0);
+		printk_debug("SATA S \t");
 	}
 	if (conf->sata0_enable) {
-	        /* Enable primary SATA interface */
-	        dword |= (1<<1);
-	        printk_debug("SATA P \n");
+		/* Enable primary SATA interface. */
+		dword |= (1 << 1);
+		printk_debug("SATA P \n");
 	}
 #if 0
-//	write back
-	dword |= (1<<12);
-	dword |= (1<<14);
+	/* Write back */
+	dword |= (1 << 12);
+	dword |= (1 << 14);
 #endif
 
 #if 0
-//	ADMA
-	dword |= (1<<16);
-	dword |= (1<<17);
+	/* ADMA */
+	dword |= (1 << 16);
+	dword |= (1 << 17);
 #endif
 
 #if 1
-//DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT.
-	dword &= ~(0x1f<<24);
-	dword |= (0x15<<24);
+	/* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */
+	dword &= ~(0x1f << 24);
+	dword |= (0x15 << 24);
 #endif
 	pci_write_config32(dev, 0x50, dword);
 
 #if 0
-//SLUMBER_DURING_D3.
+	/* SLUMBER_DURING_D3 */
 	dword = pci_read_config32(dev, 0x7c);
-	dword &=  ~(1<<4);
+	dword &= ~(1 << 4);
 	pci_write_config32(dev, 0x7c, dword);
 
 	dword = pci_read_config32(dev, 0xd0);
-	dword &=  ~(0xff<<24);
-	dword |= (0x68<<24);
+	dword &= ~(0xff << 24);
+	dword |= (0x68 << 24);
 	pci_write_config32(dev, 0xd0, dword);
 
 	dword = pci_read_config32(dev, 0xe0);
-	dword &=  ~(0xff<<24);
-	dword |= (0x68<<24);
+	dword &= ~(0xff << 24);
+	dword |= (0x68 << 24);
 	pci_write_config32(dev, 0xe0, dword);
 #endif
 
@@ -132,11 +134,11 @@
 
 #if 0
 	dword = pci_read_config32(dev, 0xac);
-	dword &= ~((1<<13)|(1<<14));
-	dword |= (1<<13)|(0<<14);
+	dword &= ~((1 << 13) | (1 << 14));
+	dword |= (1 << 13) | (0 << 14);
 	pci_write_config32(dev, 0xac, dword);
 
-	sata_com_reset(dev, 1); // for discover some s-atapi device
+	sata_com_reset(dev, 1);	/* For discover some s-atapi device. */
 #endif
 
 }
@@ -144,17 +146,18 @@
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, 0x40,
-	        ((device & 0xffff) << 16) | (vendor & 0xffff));
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
+
 static struct pci_operations lops_pci = {
 	.set_subsystem = lpci_set_subsystem,
 };
 
-static struct device_operations sata_ops  = {
+static struct device_operations sata_ops = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-//	.enable           = ck804_enable,
+	// .enable        = ck804_enable,
 	.init             = sata_init,
 	.scan_bus         = 0,
 	.ops_pci          = &lops_pci,

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@
  * Copyright 2004 Tyan Computer
  *  by yhlu at tyan.com
  */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -68,6 +69,7 @@
 
 	return do_smbus_write_byte(res->base, device, address, val);
 }
+
 static struct smbus_bus_operations lops_smbus_bus = {
 	.recv_byte  = lsmbus_recv_byte,
 	.send_byte  = lsmbus_send_byte,
@@ -78,25 +80,26 @@
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, 0x40,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
 static struct pci_operations lops_pci = {
 	.set_subsystem = lpci_set_subsystem,
 };
+
 static struct device_operations smbus_ops = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = 0,
 	.scan_bus         = scan_static_bus,
-//	.enable           = ck804_enable,
+	// .enable        = ck804_enable,
 	.ops_pci          = &lops_pci,
 	.ops_smbus_bus    = &lops_smbus_bus,
 };
+
 static const struct pci_driver smbus_driver __pci_driver = {
 	.ops    = &smbus_ops,
 	.vendor = PCI_VENDOR_ID_NVIDIA,
 	.device = PCI_DEVICE_ID_NVIDIA_CK804_SM,
 };
-

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.h	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.h	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,19 +2,21 @@
  * Copyright 2004 Tyan Computer
  *  by yhlu at tyan.com
  */
+
 #include <device/smbus_def.h>
 
-#define SMBHSTSTAT 0x1
-#define SMBHSTPRTCL  0x0
-#define SMBHSTCMD  0x3
-#define SMBXMITADD 0x2
-#define SMBHSTDAT0 0x4
-#define SMBHSTDAT1 0x5
+#define SMBHSTSTAT  0x1
+#define SMBHSTPRTCL 0x0
+#define SMBHSTCMD   0x3
+#define SMBXMITADD  0x2
+#define SMBHSTDAT0  0x4
+#define SMBHSTDAT1  0x5
 
-/* Between 1-10 seconds, We should never timeout normally
+/*
+ * Between 1-10 seconds, We should never timeout normally.
  * Longer than this is just painful when a timeout condition occurs.
  */
-#define SMBUS_TIMEOUT (100*1000*10)
+#define SMBUS_TIMEOUT (100 * 1000 * 10)
 
 static inline void smbus_delay(void)
 {
@@ -30,11 +32,10 @@
 		smbus_delay();
 		val = inb(smbus_io_base + SMBHSTSTAT);
 		val &= 0x1f;
-		if (val == 0) {
+		if (val == 0)
 			return 0;
-		}
-		outb(val,smbus_io_base + SMBHSTSTAT);
-	} while(--loops);
+		outb(val, smbus_io_base + SMBHSTSTAT);
+	} while (--loops);
 	return -2;
 }
 
@@ -45,158 +46,164 @@
 	do {
 		unsigned char val;
 		smbus_delay();
-
 		val = inb(smbus_io_base + SMBHSTSTAT);
-		if ( (val & 0xff) != 0) {
+		if ((val & 0xff) != 0)
 			return 0;
-		}
-	} while(--loops);
+	} while (--loops);
 	return -3;
 }
+
 static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
 {
-	unsigned char global_status_register;
-	unsigned char byte;
+	unsigned char global_status_register, byte;
+
 #if 0
-// Don't need, when you write to PRTCL, the status will be cleared automatically
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+	/* Not needed, upon write to PRTCL, the status will be auto-cleared. */
+	if (smbus_wait_until_ready(smbus_io_base) < 0)
 		return -2;
-	}
 #endif
 
-	/* set the device I'm talking too */
-	outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
+	/* Set the device I'm talking to. */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
 	smbus_delay();
-	/* set the command/address... */
+
+	/* Set the command/address. */
 	outb(0, smbus_io_base + SMBHSTCMD);
 	smbus_delay();
-	/* byte data recv */
+
+	/* Byte data recv */
 	outb(0x05, smbus_io_base + SMBHSTPRTCL);
 	smbus_delay();
 
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
+	/* Poll for transaction completion. */
+	if (smbus_wait_until_done(smbus_io_base) < 0)
 		return -3;
-	}
 
-	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
+	/* Lose check */
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
 
-	/* read results of transaction */
+	/* Read results of transaction. */
 	byte = inb(smbus_io_base + SMBHSTDAT0);
 
-	if (global_status_register != 0x80) { // lose check, otherwise it should be 0
+	/* Lose check, otherwise it should be 0. */
+	if (global_status_register != 0x80)
 		return -1;
-	}
+
 	return byte;
 }
-static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
+
+static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device,
+			      unsigned char val)
 {
 	unsigned global_status_register;
 
 #if 0
-// Don't need, when you write to PRTCL, the status will be cleared automatically
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+	/* Not needed, upon write to PRTCL, the status will be auto-cleared. */
+	if (smbus_wait_until_ready(smbus_io_base) < 0)
 		return -2;
-	}
 #endif
 
 	outb(val, smbus_io_base + SMBHSTDAT0);
 	smbus_delay();
 
-	/* set the device I'm talking too */
+	/* Set the device I'm talking to. */
 	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
 	smbus_delay();
 
 	outb(0, smbus_io_base + SMBHSTCMD);
 	smbus_delay();
 
-	/* set up for a byte data write */
+	/* Set up for a byte data write. */
 	outb(0x04, smbus_io_base + SMBHSTPRTCL);
 	smbus_delay();
 
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
+	/* Poll for transaction completion. */
+	if (smbus_wait_until_done(smbus_io_base) < 0)
 		return -3;
-	}
-	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
 
-	if (global_status_register != 0x80) {
+	/* Lose check */
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
+
+	if (global_status_register != 0x80)
 		return -1;
-	}
+
 	return 0;
 }
-static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+
+static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
+			      unsigned address)
 {
-	unsigned char global_status_register;
-	unsigned char byte;
+	unsigned char global_status_register, byte;
+
 #if 0
-// Don't need, when you write to PRTCL, the status will be cleared automatically
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+	/* Not needed, upon write to PRTCL, the status will be auto-cleared. */
+	if (smbus_wait_until_ready(smbus_io_base) < 0)
 		return -2;
-	}
 #endif
 
-	/* set the device I'm talking too */
-	outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
+	/* Set the device I'm talking to. */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
 	smbus_delay();
-	/* set the command/address... */
+
+	/* Set the command/address. */
 	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
 	smbus_delay();
-	/* byte data read */
+
+	/* Byte data read */
 	outb(0x07, smbus_io_base + SMBHSTPRTCL);
 	smbus_delay();
 
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
+	/* Poll for transaction completion. */
+	if (smbus_wait_until_done(smbus_io_base) < 0)
 		return -3;
-	}
 
-	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
+	/* Lose check */
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
 
-	/* read results of transaction */
+	/* Read results of transaction. */
 	byte = inb(smbus_io_base + SMBHSTDAT0);
 
-	if (global_status_register != 0x80) { // lose check, otherwise it should be 0
+	/* Lose check, otherwise it should be 0. */
+	if (global_status_register != 0x80)
 		return -1;
-	}
+
 	return byte;
 }
 
-
-static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
+static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device,
+			       unsigned address, unsigned char val)
 {
 	unsigned global_status_register;
 
 #if 0
-// Don't need, when you write to PRTCL, the status will be cleared automatically
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+	/* Not needed, upon write to PRTCL, the status will be auto-cleared. */
+	if (smbus_wait_until_ready(smbus_io_base) < 0)
 		return -2;
-	}
 #endif
 
 	outb(val, smbus_io_base + SMBHSTDAT0);
 	smbus_delay();
 
-	/* set the device I'm talking too */
+	/* Set the device I'm talking to. */
 	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
 	smbus_delay();
 
 	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
 	smbus_delay();
 
-	/* set up for a byte data write */
+	/* Set up for a byte data write. */
 	outb(0x06, smbus_io_base + SMBHSTPRTCL);
 	smbus_delay();
 
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
+	/* Poll for transaction completion. */
+	if (smbus_wait_until_done(smbus_io_base) < 0)
 		return -3;
-	}
-	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
 
-	if (global_status_register != 0x80) {
+	/* Lose check */
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
+
+	if (global_status_register != 0x80)
 		return -1;
-	}
+
 	return 0;
 }
-

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@
  * Copyright 2004 Tyan Computer
  *  by yhlu at tyan.com
  */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -9,34 +10,41 @@
 #include <device/pci_ops.h>
 #include "ck804.h"
 
-static void usb1_init(struct device *dev) {
-	struct southbridge_nvidia_ck804_config const * conf=dev->chip_info;
+static void usb1_init(struct device *dev)
+{
+	struct southbridge_nvidia_ck804_config const *conf = dev->chip_info;
 	if (conf->usb1_hc_reset) {
-		//Somehow the warm reset does not really resets the USB controller.
-		//Later, during boot, when the Bus Master bit is set, the USB
-		//controller trashes the memory, causing weird misbehavior.
-		//Was detected on Sun Ultra40, where mptable was damaged.
-		uint32_t bar0=pci_read_config32(dev,0x10);
-		uint32_t* regs=(uint32_t*)(bar0&~0xfff);
-		regs[2]|=1;	//OHCI USB HCCommandStatus Register, HostControllerReset bit
+		/*
+		 * Somehow the warm reset does not really reset the USB
+		 * controller. Later, during boot, when the Bus Master bit is
+		 * set, the USB controller trashes the memory, causing weird
+		 * misbehavior. Was detected on Sun Ultra40, where mptable
+		 * was damaged.
+		 */
+		uint32_t bar0 = pci_read_config32(dev, 0x10);
+		uint32_t *regs = (uint32_t *) (bar0 & ~0xfff);
+
+		/* OHCI USB HCCommandStatus Register, HostControllerReset bit */
+		regs[2] |= 1;
 	}
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, 0x40,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
+
 static struct pci_operations lops_pci = {
 	.set_subsystem = lpci_set_subsystem,
 };
 
-static struct device_operations usb_ops  = {
+static struct device_operations usb_ops = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = usb1_init,
-//	.enable           = ck804_enable,
+	// .enable        = ck804_enable,
 	.scan_bus         = 0,
 	.ops_pci          = &lops_pci,
 };
@@ -46,4 +54,3 @@
 	.vendor = PCI_VENDOR_ID_NVIDIA,
 	.device = PCI_DEVICE_ID_NVIDIA_CK804_USB,
 };
-

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@
  * Copyright 2004 Tyan Computer
  *  by yhlu at tyan.com
  */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -11,7 +12,6 @@
 
 static void usb2_init(struct device *dev)
 {
-
 	uint32_t dword;
 	dword = pci_read_config32(dev, 0xf8);
 	dword |= 40;
@@ -21,18 +21,19 @@
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, 0x40,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
+
 static struct pci_operations lops_pci = {
 	.set_subsystem = lpci_set_subsystem,
 };
 
-static struct device_operations usb2_ops  = {
+static struct device_operations usb2_ops = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = usb2_init,
-//	.enable           = ck804_enable,
+	// .enable        = ck804_enable,
 	.scan_bus         = 0,
 	.ops_pci          = &lops_pci,
 };

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc	2008-10-02 18:19:17 UTC (rev 3631)
@@ -1,4 +1,3 @@
-
 	.section ".id", "a", @progbits
 
 	.globl __id_start
@@ -7,9 +6,9 @@
 	.asciz MAINBOARD_VENDOR
 part:
 	.asciz MAINBOARD_PART_NUMBER
-.long __id_end + 0x80 - vendor  /* Reverse offset to the vendor id */
-.long __id_end + 0x80 - part    /* Reverse offset to the part number */
-.long PAYLOAD_SIZE + ROM_IMAGE_SIZE  /* Size of this romimage */
+.long __id_end + 0x80 - vendor       /* Reverse offset to the vendor ID */
+.long __id_end + 0x80 - part         /* Reverse offset to the part number */
+.long PAYLOAD_SIZE + ROM_IMAGE_SIZE  /* Size of this ROM image */
 	.globl __id_end
 
 __id_end:

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/romstrap.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/romstrap.inc	2008-10-02 15:42:14 UTC (rev 3630)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/romstrap.inc	2008-10-02 18:19:17 UTC (rev 3631)
@@ -2,6 +2,7 @@
  * Copyright 2004 Tyan Computer
  *  by yhlu at tyan.com
  */
+
 	.section ".romstrap", "a", @progbits
 
 




From info at coresystems.de  Thu Oct  2 20:53:52 2008
From: info at coresystems.de (coreboot information)
Date: Thu, 02 Oct 2008 20:53:52 +0200
Subject: [coreboot] r3631 build service
Message-ID: <E1KlTJA-0004KA-Bo@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "uwe" checked in revision 3631 to
the coreboot source repository and caused the following 
changes:

Change Log:
CK804 coding-style fixed based on an 'indent' run (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of amd:dbm690t is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3631&device=dbm690t&vendor=amd
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3631&device=j7f24&vendor=jetway
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3631&device=epia-cn&vendor=via


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From jordan.crouse at amd.com  Thu Oct  2 21:13:54 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 2 Oct 2008 13:13:54 -0600
Subject: [coreboot] lpgcc calling itself
In-Reply-To: <48E481CD.3020409@ampltd.com>
References: <48E481CD.3020409@ampltd.com>
Message-ID: <20081002191354.GB21465@cosmic.amd.com>

On 02/10/08 09:09 +0100, Stephen Crocker wrote:
> I have noticed a problem with lpgcc under Fedora Core 9 when building 
> Tint.  Instead of calling gcc, it calls itself.  Looking at the Makefile 
> and the script itself, I think I can see why:
> 
>  From lpgcc:
> if [ "$CC" != "" ]; then
> DEFAULT_CC=$CC
> else
> DEFAULT_CC=gcc
> fi
> 
>  From the tint Makefile:
> CC := $(LIBPAYLOAD_DIR)/bin/lpgcc
> 
> Is this a bug in tint or a bug in libpayload?

Attached is a patch to libpayload to fix that problem.  This
patch just removes the entire if statement for now, but we do
need some way to pass a compiler that isn't named 'gcc' to the 
script - options for doing that are welcome.

Also, this patch includes a -ldscript option for bayou and
FILO to pass a custom ldscript to the process while retaining
the other lpgcc benefits.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.
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From svn at coreboot.org  Thu Oct  2 21:20:22 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Oct 2008 21:20:22 +0200
Subject: [coreboot] r3632 - trunk/coreboot-v2/src/northbridge/amd/amdk8
Message-ID: <mailman.2161.1355071391.16123.coreboot@coreboot.org>

Author: myles
Date: 2008-10-02 21:20:22 +0200 (Thu, 02 Oct 2008)
New Revision: 3632

Modified:
   trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb
   trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h
   trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f_pci.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/early_ht.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/reset_test.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/setup_resource_map.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/spd_ddr2.h
   trunk/coreboot-v2/src/northbridge/amd/amdk8/ssdt.dsl
Log:
Whitespace cleanup (trivial).

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb	2008-10-02 19:20:22 UTC (rev 3632)
@@ -19,13 +19,13 @@
 
 if HAVE_ACPI_TABLES
 	object amdk8_acpi.o
-        makerule ssdt.c
-                depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
-                action  "iasl -p $(PWD)/ssdt -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
-                action  "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex"
-                action  "mv ssdt.hex ssdt.c"
-        end
-        object ./ssdt.o
+	makerule ssdt.c
+		depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
+		action  "iasl -p $(PWD)/ssdt -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
+		action  "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex"
+		action  "mv ssdt.hex ssdt.c"
+	end
+	object ./ssdt.o
 end
 
 

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c	2008-10-02 19:20:22 UTC (rev 3632)
@@ -49,133 +49,131 @@
 
 unsigned long acpi_create_madt_lapics(unsigned long current)
 {
-        device_t cpu;
-        int cpu_index = 0;
+	device_t cpu;
+	int cpu_index = 0;
 
-        for(cpu = all_devices; cpu; cpu = cpu->next) {
-                if ((cpu->path.type != DEVICE_PATH_APIC) ||
-                        (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
-                {
-                        continue;
-                }
-                if (!cpu->enabled) {
-                        continue;
-                }
-                current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.u.apic.apic_id);
-                cpu_index++;
+	for(cpu = all_devices; cpu; cpu = cpu->next) {
+		if ((cpu->path.type != DEVICE_PATH_APIC) ||
+			(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
+		{
+			continue;
+		}
+		if (!cpu->enabled) {
+			continue;
+		}
+		current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.u.apic.apic_id);
+		cpu_index++;
 
-        }
+	}
 
-        return current;
+	return current;
 }
 
 unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint)
 {
-        device_t cpu;
-        int cpu_index = 0;
+	device_t cpu;
+	int cpu_index = 0;
 
-        for(cpu = all_devices; cpu; cpu = cpu->next) {
-                if ((cpu->path.type != DEVICE_PATH_APIC) ||
-                        (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
-                {
-                        continue;
-                }
-                if (!cpu->enabled) {
-                        continue;
-                }
-                current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint);
-                cpu_index++;
+	for(cpu = all_devices; cpu; cpu = cpu->next) {
+		if ((cpu->path.type != DEVICE_PATH_APIC) ||
+			(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
+		{
+			continue;
+		}
+		if (!cpu->enabled) {
+			continue;
+		}
+		current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint);
+		cpu_index++;
 
-        }
+	}
 
-        return current;
+	return current;
 }
+
 unsigned long acpi_create_srat_lapics(unsigned long current)
 {
-        device_t cpu;
-        int cpu_index = 0;
+	device_t cpu;
+	int cpu_index = 0;
 
-        for(cpu = all_devices; cpu; cpu = cpu->next) {
-                if ((cpu->path.type != DEVICE_PATH_APIC) ||
-                        (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
-                {
-                        continue;
-                }
-                if (!cpu->enabled) {
-                        continue;
-                }
-                printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id);
-                current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id);
-                cpu_index++;
+	for(cpu = all_devices; cpu; cpu = cpu->next) {
+		if ((cpu->path.type != DEVICE_PATH_APIC) ||
+			(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
+		{
+			continue;
+		}
+		if (!cpu->enabled) {
+			continue;
+		}
+		printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id);
+		current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id);
+		cpu_index++;
 
-        }
+	}
 
-        return current;
+	return current;
 }
 
-
-
 static unsigned long resk(uint64_t value)
 {
-        unsigned long resultk;
-        if (value < (1ULL << 42)) {
-                resultk = value >> 10;
-        }
-        else {
-                resultk = 0xffffffff;
-        }
-        return resultk;
+	unsigned long resultk;
+	if (value < (1ULL << 42)) {
+		resultk = value >> 10;
+	}
+	else {
+		resultk = 0xffffffff;
+	}
+	return resultk;
 }
 
-
 struct acpi_srat_mem_state {
-        unsigned long current;
+	unsigned long current;
 };
 
 void set_srat_mem(void *gp, struct device *dev, struct resource *res)
 {
-        struct acpi_srat_mem_state *state = gp;
-        unsigned long basek, sizek;
-        basek = resk(res->base);
-        sizek = resk(res->size);
+	struct acpi_srat_mem_state *state = gp;
+	unsigned long basek, sizek;
+	basek = resk(res->base);
+	sizek = resk(res->size);
 
-        printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",
-                     dev_path(dev), res->index, basek, sizek);
-        /*
-                0-640K must be on node 0
-                next range is from 1M---
-                So will cut off before 1M in the mem range
-        */
-        if((basek+sizek)<1024) return;
+	printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",
+		     dev_path(dev), res->index, basek, sizek);
+	/*
+		0-640K must be on node 0
+		next range is from 1M---
+		So will cut off before 1M in the mem range
+	*/
+	if((basek+sizek)<1024) return;
 
-        if(basek<1024) {
-                sizek -= 1024 - basek;
-                basek = 1024;
-        }
+	if(basek<1024) {
+		sizek -= 1024 - basek;
+		basek = 1024;
+	}
 
-        state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); // need to figure out NV
+	state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); // need to figure out NV
 }
 
 unsigned long acpi_fill_srat(unsigned long current)
 {
-        struct acpi_srat_mem_state srat_mem_state;
+	struct acpi_srat_mem_state srat_mem_state;
 
-        /* create all subtables for processors */
-        current = acpi_create_srat_lapics(current);
+	/* create all subtables for processors */
+	current = acpi_create_srat_lapics(current);
 
-        /* create all subteble for memory range */
+	/* create all subteble for memory range */
 
-        /* 0-640K must be on node 0 */
-        current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable
-#if 1
-        srat_mem_state.current = current;
-        search_global_resources(
-                IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
-                set_srat_mem, &srat_mem_state);
+	/* 0-640K must be on node 0 */
+	current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable
 
-        current = srat_mem_state.current;
-#endif
-        return current;
+	srat_mem_state.current = current;
+	search_global_resources(
+		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
+		set_srat_mem, &srat_mem_state);
+
+	current = srat_mem_state.current;
+
+	return current;
 }
 
 
@@ -184,7 +182,7 @@
 	/* need to find out the node num at first */
 	/* fill the first 8 byte with that num */
 	/* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */
-	
+
 	/* because We has assume that we know the topology of the HT connection, So we can have set if we know the node_num */
 	static uint8_t hops_8[] = {   0, 1, 1, 2, 2, 3, 3, 4,
 				      1, 0, 2, 1, 3, 2, 4, 3,
@@ -192,7 +190,7 @@
 				      2, 1, 1, 0, 2, 1, 3, 2,
 				      2, 3, 1, 2, 0, 1, 1, 2,
 				      3, 2, 2, 1, 1, 0, 2, 1,
-				      3, 4, 2, 3, 1, 2, 0, 1, 	 
+				      3, 4, 2, 3, 1, 2, 0, 1,
 				      4, 4, 3, 2, 2, 1, 1, 0 };
 
 //	uint8_t outer_node[8];
@@ -208,10 +206,10 @@
 #if 0
 	for(i=0;i<sysconf.hc_possible_num;i++) {
 		if((sysconf.pci1234[i]&1) !=1 ) continue;
-		outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node		
+		outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node
 	}
 #endif
-	
+
 	for(i=0;i<nodes;i++) {
 		for(j=0;j<nodes; j++) {
 			if(i==j) { p[i*nodes+j] = 10; }
@@ -234,7 +232,7 @@
 					}
 				}
 				p[i*nodes+j] = hops_8[i*nodes+j] * 2 + latency_factor + 10;
-#else	
+#else
 				p[i*nodes+j] = hops_8[i*nodes+j] * 2 + 10;
 #endif
 
@@ -243,9 +241,9 @@
 		}
 	}
 
-        current += 8+nodes*nodes;
+	current += 8+nodes*nodes;
 
-        return current;
+	return current;
 }
 
 
@@ -255,10 +253,10 @@
 // moved from mb acpi_tables.c
 static void int_to_stream(uint32_t val, uint8_t *dest)
 {
-        int i;
-        for(i=0;i<4;i++) {
-                *(dest+i) = (val >> (8*i)) & 0xff;
-        }
+	int i;
+	for(i=0;i<4;i++) {
+		*(dest+i) = (val >> (8*i)) & 0xff;
+	}
 }
 
 
@@ -266,60 +264,60 @@
 
 void update_ssdt(void *ssdt)
 {
-        uint8_t *BUSN;
-        uint8_t *MMIO;
-        uint8_t *PCIO;
-        uint8_t *SBLK;
-        uint8_t *TOM1;
-        uint8_t *SBDN;
-        uint8_t *HCLK;
-        uint8_t *HCDN;
+	uint8_t *BUSN;
+	uint8_t *MMIO;
+	uint8_t *PCIO;
+	uint8_t *SBLK;
+	uint8_t *TOM1;
+	uint8_t *SBDN;
+	uint8_t *HCLK;
+	uint8_t *HCDN;
 	uint8_t *CBST;
 
-        int i;
-        device_t dev;
-        uint32_t dword;
-        msr_t msr;
+	int i;
+	device_t dev;
+	uint32_t dword;
+	msr_t msr;
 
-        BUSN = ssdt+0x3a; //+5 will be next BUSN
-        MMIO = ssdt+0x57; //+5 will be next MMIO
-        PCIO = ssdt+0xaf; //+5 will be next PCIO
-        SBLK = ssdt+0xdc; // one byte
-        TOM1 = ssdt+0xe3; //
-        SBDN = ssdt+0xed;//
-        HCLK = ssdt+0xfa; //+5 will be next HCLK
-        HCDN = ssdt+0x12a; //+5 will be next HCDN
+	BUSN = ssdt+0x3a; //+5 will be next BUSN
+	MMIO = ssdt+0x57; //+5 will be next MMIO
+	PCIO = ssdt+0xaf; //+5 will be next PCIO
+	SBLK = ssdt+0xdc; // one byte
+	TOM1 = ssdt+0xe3; //
+	SBDN = ssdt+0xed; //
+	HCLK = ssdt+0xfa; //+5 will be next HCLK
+	HCDN = ssdt+0x12a; //+5 will be next HCDN
 	CBST = ssdt+0x157; //
 
-        dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
-        for(i=0;i<4;i++) {
-                dword = pci_read_config32(dev, 0xe0+i*4);
-                int_to_stream(dword, BUSN+i*5);
-        }
-        for(i=0;i<0x10;i++) {
-                dword = pci_read_config32(dev, 0x80+i*4);
-                int_to_stream(dword, MMIO+i*5);
-        }
-        for(i=0;i<0x08;i++) {
-                dword = pci_read_config32(dev, 0xc0+i*4);
-                int_to_stream(dword, PCIO+i*5);
-        }
+	dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+	for(i=0;i<4;i++) {
+		dword = pci_read_config32(dev, 0xe0+i*4);
+		int_to_stream(dword, BUSN+i*5);
+	}
+	for(i=0;i<0x10;i++) {
+		dword = pci_read_config32(dev, 0x80+i*4);
+		int_to_stream(dword, MMIO+i*5);
+	}
+	for(i=0;i<0x08;i++) {
+		dword = pci_read_config32(dev, 0xc0+i*4);
+		int_to_stream(dword, PCIO+i*5);
+	}
 
-        *SBLK = (uint8_t)(sysconf.sblk);
+	*SBLK = (uint8_t)(sysconf.sblk);
 
-        msr = rdmsr(TOP_MEM);
-        int_to_stream(msr.lo, TOM1);
+	msr = rdmsr(TOP_MEM);
+	int_to_stream(msr.lo, TOM1);
 
-        for(i=0;i<sysconf.hc_possible_num;i++) {
-                int_to_stream(sysconf.pci1234[i], HCLK + i*5);
-                int_to_stream(sysconf.hcdn[i],    HCDN + i*5);
-        }
-        for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
-                int_to_stream(0x00000000, HCLK + i*5);
-                int_to_stream(0x20202020, HCDN + i*5);
-        }
+	for(i=0;i<sysconf.hc_possible_num;i++) {
+		int_to_stream(sysconf.pci1234[i], HCLK + i*5);
+		int_to_stream(sysconf.hcdn[i],    HCDN + i*5);
+	}
+	for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+		int_to_stream(0x00000000, HCLK + i*5);
+		int_to_stream(0x20202020, HCDN + i*5);
+	}
 
-        int_to_stream(sysconf.sbdn, SBDN);
+	int_to_stream(sysconf.sbdn, SBDN);
 
 	if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on  other than bus 0
 		*CBST = (uint8_t) (0x0f);

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h	2008-10-02 19:20:22 UTC (rev 3632)
@@ -461,48 +461,48 @@
 //struct definitions
 
 struct dimm_size {
-        uint8_t per_rank; // it is rows + col + bank_lines + data lines */
-        uint8_t rows;
-        uint8_t col;
-        uint8_t bank; //1, 2, 3 mean 2, 4, 8
-        uint8_t rank;
+	uint8_t per_rank; // it is rows + col + bank_lines + data lines */
+	uint8_t rows;
+	uint8_t col;
+	uint8_t bank; //1, 2, 3 mean 2, 4, 8
+	uint8_t rank;
 } __attribute__((packed));
 
 struct mem_info { // pernode
-        uint32_t dimm_mask;
-        struct dimm_size sz[DIMM_SOCKETS];
-        uint32_t x4_mask;
-        uint32_t x16_mask;
+	uint32_t dimm_mask;
+	struct dimm_size sz[DIMM_SOCKETS];
+	uint32_t x4_mask;
+	uint32_t x16_mask;
 	uint32_t single_rank_mask;
-        uint32_t page_1k_mask;
-//        uint32_t ecc_mask;
-//        uint32_t registered_mask;
-        uint8_t is_opteron;
-        uint8_t is_registered;
-        uint8_t is_ecc;
-        uint8_t is_Width128;
+	uint32_t page_1k_mask;
+//	uint32_t ecc_mask;
+//	uint32_t registered_mask;
+	uint8_t is_opteron;
+	uint8_t is_registered;
+	uint8_t is_ecc;
+	uint8_t is_Width128;
 	uint8_t is_64MuxMode;
-        uint8_t memclk_set; // we need to use this to retrieve the mem param
+	uint8_t memclk_set; // we need to use this to retrieve the mem param
 	uint8_t rsv[2];
 } __attribute__((packed));
 
 struct link_pair_st {
-        device_t udev;
-        uint32_t upos;
-        uint32_t uoffs;
-        device_t dev;
-        uint32_t pos;
-        uint32_t offs;
+	device_t udev;
+	uint32_t upos;
+	uint32_t uoffs;
+	device_t dev;
+	uint32_t pos;
+	uint32_t offs;
 
 } __attribute__((packed));
 
 struct sys_info {
-        uint8_t ctrl_present[NODE_NUMS];
-        struct mem_info meminfo[NODE_NUMS];
+	uint8_t ctrl_present[NODE_NUMS];
+	struct mem_info meminfo[NODE_NUMS];
 	struct mem_controller ctrl[NODE_NUMS];
 	uint8_t mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail
-        uint32_t tom_k;
-        uint32_t tom2_k;
+	uint32_t tom_k;
+	uint32_t tom2_k;
 
 	uint32_t mem_base[NODE_NUMS];
 	uint32_t cs_base[NODE_NUMS*8]; //8 cs_idx
@@ -511,9 +511,9 @@
 	uint8_t dqs_delay_a[NODE_NUMS*2*2*9]; //8 node channel 2, direction 2 , bytelane *9
 	uint8_t dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8
 	uint32_t nodes;
-        struct link_pair_st link_pair[16];// enough? only in_conherent
-        uint32_t link_pair_num;
-        uint32_t ht_c_num;
+	struct link_pair_st link_pair[16];// enough? only in_conherent
+	uint32_t link_pair_num;
+	uint32_t ht_c_num;
 	uint32_t sbdn;
 	uint32_t sblk;
 	uint32_t sbbusn;
@@ -526,38 +526,38 @@
 static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 {
 
-        int i;
-        uint32_t mask = 0;
+	int i;
+	uint32_t mask = 0;
 	unsigned needs_reset = 0;
 
 
 	if(sysinfo->nodes == 1) return; // in case only one cpu installed	
 
-        for(i=1; i<sysinfo->nodes; i++) {
-                /* Skip everything if I don't have any memory on this controller */
-                if(sysinfo->mem_trained[i]==0x00) continue;
+	for(i=1; i<sysinfo->nodes; i++) {
+		/* Skip everything if I don't have any memory on this controller */
+		if(sysinfo->mem_trained[i]==0x00) continue;
 
-                mask |= (1<<i);
+		mask |= (1<<i);
 
-        }
+	}
 
-        i = 1;
-        while(1) {
+	i = 1;
+	while(1) {
 		if(mask & (1<<i)) {
 			if((sysinfo->mem_trained[i])!=0x80) {
 				mask &= ~(1<<i);
 			}
 		}
 
-                if(!mask) break;
+		if(!mask) break;
 
 #if 0
 		/* cpu_relax */
 		__asm__ __volatile__("rep;nop": : :"memory");
 #endif
 
-                i++;
-                i%=sysinfo->nodes;
+		i++;
+		i%=sysinfo->nodes;
 	}
 
 	for(i=0; i<sysinfo->nodes; i++) {
@@ -566,7 +566,7 @@
 #else
 		printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); 
 #endif
-                switch(sysinfo->mem_trained[i]) {
+		switch(sysinfo->mem_trained[i]) {
 		case 0: //don't need train
 		case 1: //trained
 			break;

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f_pci.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f_pci.c	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f_pci.c	2008-10-02 19:20:22 UTC (rev 3632)
@@ -4,53 +4,53 @@
 /* bit [10,8] are dev func, bit[1,0] are dev index */
 static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32_t index)
 {
-        uint32_t dword;
+	uint32_t dword;
 
-        pci_write_config32(dev, index_reg, index);
+	pci_write_config32(dev, index_reg, index);
 
-        dword = pci_read_config32(dev, index_reg+0x4);
+	dword = pci_read_config32(dev, index_reg+0x4);
 
-        return dword;
+	return dword;
 }
 
 static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data)
 {
 
-        pci_write_config32(dev, index_reg, index);
+	pci_write_config32(dev, index_reg, index);
 
-        pci_write_config32(dev, index_reg + 0x4, data);
+	pci_write_config32(dev, index_reg + 0x4, data);
 
 }
 
 static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index)
 {
 
-        uint32_t dword;
+	uint32_t dword;
 
-        index &= ~(1<<30);
-        pci_write_config32(dev, index_reg, index);
+	index &= ~(1<<30);
+	pci_write_config32(dev, index_reg, index);
 
-        do {
-                dword = pci_read_config32(dev, index_reg);
-        } while (!(dword & (1<<31)));
+	do {
+		dword = pci_read_config32(dev, index_reg);
+	} while (!(dword & (1<<31)));
 
-        dword = pci_read_config32(dev, index_reg+0x4);
+	dword = pci_read_config32(dev, index_reg+0x4);
 
-        return dword;
+	return dword;
 }
 
 static void pci_write_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data)
 {
 
-        uint32_t dword;
+	uint32_t dword;
 
-        pci_write_config32(dev, index_reg + 0x4, data);
+	pci_write_config32(dev, index_reg + 0x4, data);
 
-        index |= (1<<30);
-        pci_write_config32(dev, index_reg, index);
-        do {
-                dword = pci_read_config32(dev, index_reg);
-        } while (!(dword & (1<<31)));
+	index |= (1<<30);
+	pci_write_config32(dev, index_reg, index);
+	do {
+		dword = pci_read_config32(dev, index_reg);
+	} while (!(dword & (1<<31)));
 
 }
 

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c	2008-10-02 19:20:22 UTC (rev 3632)
@@ -1,5 +1,5 @@
-/* coherent hypertransport initialization for AMD64 
- * 
+/* coherent hypertransport initialization for AMD64
+ *
  * written by Stefan Reinauer <stepan at openbios.org>
  * (c) 2003-2004 by SuSE Linux AG
  *
@@ -16,51 +16,51 @@
  * nodes :  1    2    4    6    8
  * org.  :  1x1  2x1  2x2  2x3  2x4
  Ladder:
-			CPU7-------------CPU6 
-			|                |    
+			CPU7-------------CPU6
 			|                |
-			|                | 
-			|                |     
-			|                |        
-			|                |    
-			CPU5-------------CPU4                    
-			|                |    
-			|                |   
-			|                |  
-			|                |    
-			|                |         
-			|                |       
-			CPU3-------------CPU2              
-			|                |    
-			|                | 
 			|                |
 			|                |
-			|                | 
-			|                |    
-			CPU1-------------CPU0    
+			|                |
+			|                |
+			|                |
+			CPU5-------------CPU4
+			|                |
+			|                |
+			|                |
+			|                |
+			|                |
+			|                |
+			CPU3-------------CPU2
+			|                |
+			|                |
+			|                |
+			|                |
+			|                |
+			|                |
+			CPU1-------------CPU0
  CROSS_BAR_47_56:
-			CPU7-------------CPU6 
-			|  \____    ___/ |    
+			CPU7-------------CPU6
+			|  \____    ___/ |
 			|       \  /     |
-			|        \/      | 
-			|        /\      |     
-			|       /  \     |        
-			|  ____/    \___ |    
-			CPU5             CPU4                    
-			|                |    
-			|                |   
-			|                |  
-			|                |    
-			|                |         
-			|                |       
-			CPU3-------------CPU2              
-			|                |    
-			|                | 
+			|        \/      |
+			|        /\      |
+			|       /  \     |
+			|  ____/    \___ |
+			CPU5             CPU4
 			|                |
 			|                |
-			|                | 
-			|                |    
-			CPU1-------------CPU0     	
+			|                |
+			|                |
+			|                |
+			|                |
+			CPU3-------------CPU2
+			|                |
+			|                |
+			|                |
+			|                |
+			|                |
+			|                |
+			CPU1-------------CPU0
  */
 
 #include <device/pci_def.h>
@@ -105,15 +105,15 @@
 #endif
 
 #ifndef ENABLE_APIC_EXT_ID
-        #define ENABLE_APIC_EXT_ID 0
+	#define ENABLE_APIC_EXT_ID 0
 #endif
 
 
-static inline void print_linkn (const char *strval, uint8_t byteval) 
+static inline void print_linkn (const char *strval, uint8_t byteval)
 {
 #if 1
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("%s%02x\r\n", strval, byteval); 
+	printk_debug("%s%02x\r\n", strval, byteval);
 #else
 	print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
 #endif
@@ -126,7 +126,7 @@
 	 * they don't make sense if only one cpu is available
 	 */
 
-	/* Hypetransport Transaction Control Register 
+	/* Hypetransport Transaction Control Register
 	 * F0:0x68
 	 * [ 0: 0] Disable read byte probe
 	 *         0 = Probes issues
@@ -151,7 +151,7 @@
 
 	val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL);
 	val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C |
-		HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P | 
+		HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P |
 		HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
 	pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);
 
@@ -159,16 +159,16 @@
 
 }
 
-static void enable_apic_ext_id(u8 node) 
+static void enable_apic_ext_id(u8 node)
 {
 #if ENABLE_APIC_EXT_ID==1
 #warning "FIXME Is the right place to enable apic ext id here?"
 
       u32 val;
 
-        val = pci_read_config32(NODE_HT(node), 0x68);
-        val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
-        pci_write_config32(NODE_HT(node), 0x68, val);
+	val = pci_read_config32(NODE_HT(node), 0x68);
+	val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
+	pci_write_config32(NODE_HT(node), 0x68, val);
 #endif
 }
 
@@ -228,7 +228,7 @@
 	if (ldt&0x08) return 0x40;
 	if (ldt&0x04) return 0x20;
 	if (ldt&0x02) return 0x00;
-	
+
 	/* we should never get here */
 	print_spew("Unknown Link\n");
 	return 0;
@@ -253,7 +253,7 @@
 
 	val=pci_read_config32(NODE_HT(7), 0x60);
 	val &= (~7);  /* clear low bits. */
-        val |= node;   /* new node        */
+	val |= node;  /* new node        */
 	pci_write_config32(NODE_HT(7), 0x60, val);
 
 	print_spew(" done.\r\n");
@@ -263,12 +263,12 @@
 {
 	/* See if we have a valid connection to dest */
 	u32 val;
-	
+
 	/* Verify that the coherent hypertransport link is
 	 * established and actually working by reading the
 	 * remode node's vendor/device id
 	 */
-        val = pci_read_config32(NODE_HT(dest),0);
+	val = pci_read_config32(NODE_HT(dest),0);
 	if(val != 0x11001022)
 		return 0;
 
@@ -287,7 +287,7 @@
 #if K8_HT_FREQ_1G_SUPPORT == 1
     #if K8_REV_F_SUPPORT == 0
 	if (!is_cpu_pre_e0())
-    #endif 
+    #endif
 	{
 		return freq_cap;
 	}
@@ -299,7 +299,7 @@
 	if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
 		freq_cap &= ~(1 << HT_FREQ_1000Mhz);
 	}
-	
+
 	return freq_cap;
 }
 
@@ -353,10 +353,10 @@
 		ln_width1 = ln_width2;
 	}
 	width |= pow2_to_link_width[ln_width1] << 4;
-	
+
 	/* See if I am changing node1's width */
 	old_width = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1);
-	old_width &= 0x77;	
+	old_width &= 0x77;
 	needs_reset |= old_width != width;
 
 	/* Set node1's widths */
@@ -378,27 +378,27 @@
 
 static uint8_t get_linkn_first(uint8_t byte)
 {
-        if(byte & 0x02) { byte = 0; }
-        else if(byte & 0x04) { byte = 1; }
-        else if(byte & 0x08) { byte = 2; }
-        return byte;
+	if(byte & 0x02) { byte = 0; }
+	else if(byte & 0x04) { byte = 1; }
+	else if(byte & 0x08) { byte = 2; }
+	return byte;
 }
 
 static uint8_t get_linkn_last(uint8_t byte)
 {
-        if(byte & 0x02) { byte &= 0x0f; byte |= 0x00;  }
-        if(byte & 0x04) { byte &= 0x0f; byte |= 0x10;  }
-        if(byte & 0x08) { byte &= 0x0f; byte |= 0x20;  }
-        return byte>>4;
+	if(byte & 0x02) { byte &= 0x0f; byte |= 0x00;  }
+	if(byte & 0x04) { byte &= 0x0f; byte |= 0x10;  }
+	if(byte & 0x08) { byte &= 0x0f; byte |= 0x20;  }
+	return byte>>4;
 }
 
 static uint8_t get_linkn_last_count(uint8_t byte)
 {
-        byte &= 0x0f;
-        if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; }
-        if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; }
-        if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
-        return byte>>4;
+	byte &= 0x0f;
+	if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; }
+	if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; }
+	if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
+	return byte>>4;
 }
 
 static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/
@@ -406,13 +406,13 @@
 	uint8_t linkn;
 	uint32_t val;
 	val = 1;
-	for(linkn = 0; linkn<3; linkn++) { 
-		uint8_t regpos; 
+	for(linkn = 0; linkn<3; linkn++) {
+		uint8_t regpos;
 		uint32_t reg;
 		regpos = 0x98 + 0x20 * linkn;
 		reg = pci_read_config32(NODE_HT(source), regpos);
 		if ((reg & 0x17) != 3) continue; /* it is not conherent or not connected*/
-		val |= 1<<(linkn+1); 
+		val |= 1<<(linkn+1);
 	}
 	val <<= 16;
 	val |= 0x0101;
@@ -426,17 +426,17 @@
 	val = 1<<(linkn+1);
 	val |= 1<<(linkn+1+8); /*for direct connect response route should equal to request table*/
 
-	if(((source &1)!=(dest &1)) 
+	if(((source &1)!=(dest &1))
 #if CROSS_BAR_47_56
 		&& ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here
-					       //(6,5) (7,4) should be here	
+					       //(6,5) (7,4) should be here
 #endif
 	){
 		val |= (1<<16);
 	} else {
 		/*for CROSS_BAR_47_56  47, 56, should be here too
-			and for 47, 56, 57, 75, 46, 64 we need to substract another link to 
-				6,  7,  6,  6,  7,  7 
+			and for 47, 56, 57, 75, 46, 64 we need to substract another link to
+				6,  7,  6,  6,  7,  7
 		*/
 		val_s = get_row(temp, source);
 		val |= ((val_s>>16) - (1<<(linkn+1)))<<16;
@@ -454,26 +454,26 @@
 }
 
 static void opt_broadcast_rt_group(const u8 *conn, int num) {
-        int i;
+	int i;
 
-        for(i=0; i<num; i+=3) {
-                opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
-        }
+	for(i=0; i<num; i+=3) {
+		opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
+	}
 }
 static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) {
-        uint32_t val;
-        val = get_row(source, dest);
-        val += link_connection(source, kickout)<<16;
-        fill_row(source, dest, val);
-}       
-        
+	uint32_t val;
+	val = get_row(source, dest);
+	val += link_connection(source, kickout)<<16;
+	fill_row(source, dest, val);
+}
+
 static void opt_broadcast_rt_plus_group(const u8 *conn, int num) {
-        int i;  
-                
-        for(i=0; i<num; i+=3) {
-                opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]);
-        }       
-} 
+	int i;
+
+	for(i=0; i<num; i+=3) {
+		opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]);
+	}
+}
 #endif
 
 static void setup_row_direct(u8 source, u8 dest, u8 linkn){
@@ -497,8 +497,8 @@
 
 static void setup_remote_node(u8 node)
 {
-	static const uint8_t pci_reg[] = { 
-		0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c, 
+	static const uint8_t pci_reg[] = {
+		0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c,
 		0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78,
 		0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc,
 		0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8,
@@ -535,7 +535,7 @@
 	/*for indirect connection, we need to compute the val from val_s(source, source), and val_g(source, gateway) */
 	uint32_t val_s;
 	uint32_t val;
-#if !CROSS_BAR_47_56	
+#if !CROSS_BAR_47_56
 	u8 gateway;
 	u8 diff;
 	if(source<dest) {
@@ -546,11 +546,11 @@
 #endif
 	val_s = get_row(temp, source);
 	val = get_row(temp, gateway);
-	
+
 	val &= 0xffff;
 	val_s >>= 16;
 	val_s &= 0xfe;
-	
+
 #if !CROSS_BAR_47_56
 	diff = ((source&1)!=(dest &1));
 #endif
@@ -568,32 +568,32 @@
 			if(source<dest) {
 				val_s-=link_connection(temp, source-2); /* -down*/
 			} else {
-#if CROSS_BAR_47_56		
-				#if 0		
+#if CROSS_BAR_47_56
+				#if 0
 				if(source==7) {
 					val_s-=link_connection(temp, 6);  // for 7,2 via 5
 				} else if (source==6){
 					val_s-=link_connection(temp, 7);  // for 6,3 via 4
-				} else 
+				} else
 				#endif
 				if (source < gateway) { // for 5, 4 via 7
 				  	val_s-=link_connection(temp, source-2);
 				} else
-#endif					
+#endif
 					val_s-=link_connection(temp, source+2); /* -up*/
 			}
 		}
 #endif
 		val &= 0xff;
 		val |= (val_s<<8);
-	} 
+	}
 
 	if(diff) { /* cross rung?*/
 		val |= (1<<16);
 	}
 	else {
 		val_s = get_row(temp, source);
-		val |= ((val_s>>16) - link_connection(temp, gateway))<<16; 
+		val |= ((val_s>>16) - link_connection(temp, gateway))<<16;
 	}
 
 	fill_row(temp, dest, val);
@@ -602,15 +602,15 @@
 
 #if !CROSS_BAR_47_56
 static void setup_row_indirect(u8 source, u8 dest)
-{	
+{
 	setup_row_indirect_x(source, source, dest);
 }
-#else           
+#else
 static void setup_row_indirect(u8 source, u8 dest, u8 gateway, u8 diff)
 {
 	setup_row_indirect_x(source, source, dest, gateway, diff);
 }
-#endif   
+#endif
 
 static void setup_row_indirect_group(const u8 *conn, int num)
 {
@@ -674,9 +674,9 @@
 		needs_reset = optimize_connection(
 			NODE_HT(opt_conn[i]), 0x80 + link_to_register(link_connection(opt_conn[i],opt_conn[i+1])),
 			NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])) );
-	}               
+	}
 	return needs_reset;
-}  
+}
 #endif
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
@@ -688,7 +688,7 @@
 	nodes = 2;
 
 	setup_row_local(0, 0); /* it will update the broadcast RT*/
-	
+
 	val = get_row(0,0);
 	byte = (val>>16) & 0xfe;
 	if(byte<0x2) { /* no coherent connection so get out.*/
@@ -705,7 +705,7 @@
 	print_linkn("(0,1) link=", byte);
 	setup_row_direct(0,1, byte);
 	setup_temp_row(0, 1);
-	
+
 	verify_connection(7);
 
 	/* We found 2 nodes so far */
@@ -715,7 +715,7 @@
 	setup_row_local(7,1);
 	setup_remote_row_direct(1, 0, byte);
 
-#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)	
+#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
 	val = get_row(7,1);
 	byte = (val>>16) & 0xfe;
 	byte = get_linkn_last_count(byte);
@@ -730,18 +730,18 @@
 		print_linkn("\t-->(0,1) link=", byte);
 		setup_row_direct(0,1, byte);
 		setup_temp_row(0, 1);
-	
+
 		verify_connection(7);
-			
+
 		/* We found 2 nodes so far */
 		val = pci_read_config32(NODE_HT(7), 0x6c);
 		byte = (val>>2) & 0x3; /* get default link on node7 to node0*/
-		print_linkn("\t-->(1,0) link=", byte); 
+		print_linkn("\t-->(1,0) link=", byte);
 		setup_row_local(7,1);
 		setup_remote_row_direct(1, 0, byte);
 	}
 #endif
-	
+
 	setup_remote_node(1);  /* Setup the regs on the remote node */
 	rename_temp_node(1);    /* Rename Node 7 to Node 1  */
 	enable_routing(1);      /* Enable routing on Node 1 */
@@ -775,7 +775,7 @@
 	}
 
 	byte &= 3; /* bit [3,2] is count-1*/
-	print_linkn("(0,2) link=", byte); 
+	print_linkn("(0,2) link=", byte);
 	setup_row_direct(0, 2, byte);  /*(0,2) direct link done*/
 
 	/* We found 3 nodes so far. Now setup a temporary
@@ -786,7 +786,7 @@
 	val = get_row(1,1);
 	byte = ((val>>16) & 0xfe) - link_connection(1,0);
 	byte = get_linkn_first(byte);
-	print_linkn("(1,3) link=", byte); 
+	print_linkn("(1,3) link=", byte);
 	setup_row_direct(1,3,byte);  /* (1, 3) direct link done*/
 
 	/* We found 4 nodes so far. Now setup all nodes for 4p */
@@ -795,7 +795,7 @@
 	static const u8 conn4_1[] = {
 		0,3,
 		1,2,
-	};	
+	};
 #else
 	static const u8 conn4_1[] = {
 		0,3,2,1,
@@ -809,7 +809,7 @@
 	verify_connection(7);
 	val = pci_read_config32(NODE_HT(7), 0x6c);
 	byte = (val>>2) & 0x3; /* get default link on 7 to 0*/
-	print_linkn("(2,0) link=", byte); 
+	print_linkn("(2,0) link=", byte);
 
 	setup_row_local(7,2);
 	setup_remote_row_direct(2, 0, byte);  /* node 2 to node 0 direct link done */
@@ -824,7 +824,7 @@
 
 	val = pci_read_config32(NODE_HT(7), 0x6c);
 	byte = (val>>2) & 0x3; /* get default link on 7 to 1*/
-	print_linkn("(3,1) link=", byte); 
+	print_linkn("(3,1) link=", byte);
 
 	setup_row_local(7,3);
 	setup_remote_row_direct(3, 1, byte); /* node 3 to node 1 direct link done */
@@ -835,7 +835,7 @@
 	byte = ((val>>16) & 0xfe) - link_connection(2,0);
 	byte = get_linkn_last_count(byte);
 	print_linkn("(2,3) link=", byte & 3);
-	
+
 	setup_row_direct(2,3, byte & 0x3);
 	setup_temp_row(0,2);
 	setup_temp_row(2,3);
@@ -849,68 +849,68 @@
 			val = get_row(2,2);
 			byte = ((val>>16) & 0xfe) - link_connection(2,0);
 			byte = get_linkn_first(byte);
-			print_linkn("\t-->(2,3) link=", byte); 
+			print_linkn("\t-->(2,3) link=", byte);
 			setup_row_direct(2,3,byte);
 			setup_temp_row(2,3);
 			verify_connection(7); /* to 3*/
 		}
-	} 
+	}
 #endif
 
 	val = pci_read_config32(NODE_HT(7), 0x6c);
 	byte = (val>>2) & 0x3; /* get default link on 7 to 2*/
-	print_linkn("(3,2) link=", byte); 
+	print_linkn("(3,2) link=", byte);
 	setup_remote_row_direct(3,2, byte);
 
 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
 	/* set link from 3 to 5 before enable it*/
-        val = get_row(7,3);
-        byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1);
-        byte = get_linkn_last_count(byte);
-        if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/
-        	byte &= 3; /*bit [3,2] is count-2*/
-	        print_linkn("(3,5) link=", byte);
-	        setup_remote_row_direct(3, 5, byte);
+	val = get_row(7,3);
+	byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1);
+	byte = get_linkn_last_count(byte);
+	if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/
+		byte &= 3; /*bit [3,2] is count-2*/
+		print_linkn("(3,5) link=", byte);
+		setup_remote_row_direct(3, 5, byte);
 	}
-	
-        val = get_row(2,2);
-        byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
-        byte = get_linkn_last_count(byte);
 
-        if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/
-	        byte &= 3; /* bit [3,2] is count-2*/
-	        print_linkn("(2,4) link=", byte);
-	        setup_row_direct(2, 4, byte);
-	}	
+	val = get_row(2,2);
+	byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
+	byte = get_linkn_last_count(byte);
+
+	if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/
+		byte &= 3; /* bit [3,2] is count-2*/
+		print_linkn("(2,4) link=", byte);
+		setup_row_direct(2, 4, byte);
+	}
 #endif
 
 	//Beside 3, 1 is set, We need to make sure 3, 5 is set already in case has three link in 3
 #if !CROSS_BAR_47_56
-        static const u8 conn4_3[] = {
-                3,0,
-        };
+	static const u8 conn4_3[] = {
+		3,0,
+	};
 #else
-        static const u8 conn4_3[] = {
-                3,0,1,1,
-        };
+	static const u8 conn4_3[] = {
+		3,0,1,1,
+	};
 #endif
-        setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3));
+	setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3));
 
 /* ready to enable RT for Node 3 */
 	rename_temp_node(3);
 	enable_routing(3);      /* enable routing on node 3 (temp.) */
 
 	// beside 2, 0 is set, We need to make sure 2, 4 link is set already in case has three link in 2
-#if !CROSS_BAR_47_56    
-        static const u8 conn4_2[] = {
-                2,1,  
-        };      
-#else   
-        static const u8 conn4_2[] = {
-                2,1,0,1,
-        };      
-#endif          
-        setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2));
+#if !CROSS_BAR_47_56
+	static const u8 conn4_2[] = {
+		2,1,
+	};
+#else
+	static const u8 conn4_2[] = {
+		2,1,0,1,
+	};
+#endif
+	setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2));
 
 #if 0
 	/*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */
@@ -936,27 +936,27 @@
 	nodes=6;
 
 	/* Setup and check temporary connection from Node 0 to Node 4  through 2*/
-        val = get_row(2,2);
-        byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
-        byte = get_linkn_last_count(byte);
+	val = get_row(2,2);
+	byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
+	byte = get_linkn_last_count(byte);
 
-        if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
-                nodes = 4;
-                return nodes;
-        }
+	if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
+		nodes = 4;
+		return nodes;
+	}
 
 	/* Setup and check temporary connection from Node 0 to Node 5  through 1, 3*/
-        /* set link from 3 to 5 before enable it*/
-        val = get_row(3,3);
-        byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
-        byte = get_linkn_last_count(byte);
-        if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
-                nodes = 4;
-                return nodes;
-        }
-	
+	/* set link from 3 to 5 before enable it*/
+	val = get_row(3,3);
+	byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
+	byte = get_linkn_last_count(byte);
+	if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
+		nodes = 4;
+		return nodes;
+	}
+
 	/* We found 6 nodes so far. Now setup all nodes for 6p */
-#warning "FIXME we need to find out the correct gateway for 6p"	
+#warning "FIXME we need to find out the correct gateway for 6p"
 	static const u8 conn6_1[] = {
 #if !CROSS_BAR_47_56
 		0, 4,
@@ -973,22 +973,22 @@
 		2, 5, 3, 0,
 		3, 4, 2, 0,
 #endif
-	}; 
+	};
 
 	setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1));
-	
+
 	for(byte=0; byte<4; byte+=2) {
 		setup_temp_row(byte,byte+2);
 	}
 	verify_connection(7);
 	val = pci_read_config32(NODE_HT(7), 0x6c);
 	byte = (val>>2) & 0x3; /*get default link on 7 to 2*/
-	print_linkn("(4,2) link=", byte); 
-	
+	print_linkn("(4,2) link=", byte);
+
 	setup_row_local(7,4);
 	setup_remote_row_direct(4, 2, byte);
 	setup_remote_node(4);  /* Setup the regs on the remote node */
-	
+
 	/* Set indirect connection to 0, to 3 */
 	//we only need to set 4,0 here
 	static const u8 conn6_2[] = {
@@ -997,10 +997,10 @@
 #else
 		4, 0, 2, 0,
 #endif
-	};      
-	
+	};
+
 	setup_remote_row_indirect_group(conn6_2, ARRAY_SIZE(conn6_2));
-	
+
 	rename_temp_node(4);
 	enable_routing(4);
 
@@ -1012,18 +1012,18 @@
 
 	val = pci_read_config32(NODE_HT(7), 0x6c);
 	byte = (val>>2) & 0x3; /* get default link on 7 to 3*/
-	print_linkn("(5,3) link=", byte); 
+	print_linkn("(5,3) link=", byte);
 	setup_row_local(7,5);
 	setup_remote_row_direct(5, 3, byte);
 	setup_remote_node(5);  /* Setup the regs on the remote node */
-	
+
 #if !CROSS_BAR_47_56
 	/* We need to init link between 4, and 5 direct link */
 	val = get_row(4,4);
 	byte = ((val>>16) & 0xfe) - link_connection(4,2);
 	byte = get_linkn_last_count(byte);
 	print_linkn("(4,5) link=", byte & 3);
-	
+
 	setup_row_direct(4,5, byte & 0x3);
 	setup_temp_row(0,2);
 	setup_temp_row(2,4);
@@ -1032,7 +1032,7 @@
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 6
 	/* We need to find out which link is to node5 */
-	
+
 	if((byte>>2)==2) { /* one to node5, one to node2, one to node6*/
 		val = get_row(7,5);
 		if((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/
@@ -1044,37 +1044,37 @@
 			setup_temp_row(4,5);
 			verify_connection(7); /* to 5*/
 		}
-	} 
+	}
 #endif
 
 	val = pci_read_config32(NODE_HT(7), 0x6c);
 	byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
-	print_linkn("(5,4) link=", byte); 
+	print_linkn("(5,4) link=", byte);
 	setup_remote_row_direct(5,4, byte);
-	
+
 	//init 5, 7 here
-        val = get_row(7,5);
-        byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3);
-        byte = get_linkn_last_count(byte);
-        if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/
-        	byte &= 3; /*bit [3,2] is count-2*/
-	        print_linkn("(5,7) link=", byte);
-	        setup_remote_row_direct(5, 7, byte);
+	val = get_row(7,5);
+	byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3);
+	byte = get_linkn_last_count(byte);
+	if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/
+		byte &= 3; /*bit [3,2] is count-2*/
+		print_linkn("(5,7) link=", byte);
+		setup_remote_row_direct(5, 7, byte);
 	}
-	
+
 	//init 4,6 here
-        val = get_row(4,4);
-        byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
-        byte = get_linkn_last_count(byte);
+	val = get_row(4,4);
+	byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
+	byte = get_linkn_last_count(byte);
 
-        if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/
-	        byte &= 3; /* bit [3,2] is count-2*/
-	        print_linkn("(4,6) link=", byte);
-	        setup_row_direct(4, 6, byte);
-	}	
-	
-#endif	
-	
+	if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/
+		byte &= 3; /* bit [3,2] is count-2*/
+		print_linkn("(4,6) link=", byte);
+		setup_row_direct(4, 6, byte);
+	}
+
+#endif
+
 	//We need to set 5,0 here only, We need to set up 5, 7 to make 5,0
 	/* Set indirect connection to 0, to 3  for indirect we will use clockwise routing */
 	static const u8 conn6_3[] = {
@@ -1083,8 +1083,8 @@
 #else
 		5, 0, 3, 0,
 #endif
-	};      
-	
+	};
+
 	setup_remote_row_indirect_group(conn6_3, ARRAY_SIZE(conn6_3));
 
 /* ready to enable RT for 5 */
@@ -1095,27 +1095,27 @@
 #if !CROSS_BAR_47_56
 		4, 1,
 		4, 3,
-		
+
 		5, 2,
 		5, 1,
-		
+
 #else
 		4, 1, 2, 0,
 		4, 3, 2, 0,
 		4, 5, 2, 0,
-		
+
 		5, 2, 3, 0,
 		5, 1, 3, 0,
 		5, 4, 3, 0,
-		
+
 #endif
-	};      
-	
+	};
+
 	setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4));
 
 #if 0
 	/* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5)
-	 * It will be done by clear_dead_links 
+	 * It will be done by clear_dead_links
 	 */
 	for(byte=0; byte<4; byte++) {
 		clear_temp_row(byte);
@@ -1140,18 +1140,18 @@
 
 	/* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */
 	val = get_row(4,4);
-#if CROSS_BAR_47_56 
+#if CROSS_BAR_47_56
 	byte = ((val>>16) & 0xfe) - link_connection(4,2);
 #else
 	byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
-        byte = get_linkn_last_count(byte); /* Max link to 6*/
-        if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
-                nodes = 6;
-                return nodes;
-        }
+	byte = get_linkn_last_count(byte); /* Max link to 6*/
+	if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
+		nodes = 6;
+		return nodes;
+	}
 #endif
 
-#if CROSS_BAR_47_56 
+#if CROSS_BAR_47_56
 	byte = get_linkn_last_count(byte); /* Max link to 6*/
 	if((byte>>2)<2) { /* We should have two or three coherent links on node 4 for 8p*/
 		nodes = 6;
@@ -1169,13 +1169,13 @@
 
 #if !CROSS_BAR_47_56
 	/* Setup and check temporary connection from Node 0 to Node 7  through 1, 3, 5*/
-        val = get_row(5,5);
-        byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
-        byte = get_linkn_last_count(byte);
-        if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
-                nodes = 6;
-                return nodes;
-        }
+	val = get_row(5,5);
+	byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
+	byte = get_linkn_last_count(byte);
+	if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
+		nodes = 6;
+		return nodes;
+	}
 #endif
 
 	/* We found 8 nodes so far. Now setup all nodes for 8p */
@@ -1212,12 +1212,12 @@
 	val = pci_read_config32(NODE_HT(7), 0x6c);
 	byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
 	print_linkn("(6,4) link=", byte);
-	
+
 	setup_row_local(7,6);
 	setup_remote_row_direct(6, 4, byte);
 	setup_remote_node(6);  /* Setup the regs on the remote node */
 	/* Set indirect connection to 0, to 3   */
-#warning "FIXME we need to find out the correct gateway for 8p"		
+#warning "FIXME we need to find out the correct gateway for 8p"
 	static const u8 conn8_2[] = {
 #if !CROSS_BAR_47_56
 		6, 0,
@@ -1230,55 +1230,55 @@
 
 #if CROSS_BAR_47_56
 	//init 5, 6 here
-        /* here init 5, 6 */
-        /* Setup and check temporary connection from Node 0 to Node 5  through 1, 3, 5*/
-        val = get_row(5,5);
-        byte = ((val>>16) & 0xfe) - link_connection(5,3);
+	/* here init 5, 6 */
+	/* Setup and check temporary connection from Node 0 to Node 5  through 1, 3, 5*/
+	val = get_row(5,5);
+	byte = ((val>>16) & 0xfe) - link_connection(5,3);
 #if TRY_HIGH_FIRST == 1
 	byte = get_linkn_first(byte);
 #else
-        byte = get_linkn_last(byte);        
+	byte = get_linkn_last(byte);
 #endif
-        print_linkn("(5,6) link=", byte);
-        setup_row_direct(5, 6, byte);
+	print_linkn("(5,6) link=", byte);
+	setup_row_direct(5, 6, byte);
 
-        setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
-        for(byte=0; byte<4; byte+=2) {
-                setup_temp_row(byte+1,byte+3);
-        }
+	setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
+	for(byte=0; byte<4; byte+=2) {
+		setup_temp_row(byte+1,byte+3);
+	}
 	setup_temp_row(5,6);
 
-        verify_connection(7);
+	verify_connection(7);
 
 	val = get_row(7,6); // to chect it if it is node6 before renaming
 	if( (val>>16) == 1) { // it is real node 7 so swap it
-                /* We need to recompute link to 6 */
-       	        val = get_row(5,5);
-               	byte = ((val>>16) & 0xfe) - link_connection(5,3);
+		/* We need to recompute link to 6 */
+       		val = get_row(5,5);
+	       	byte = ((val>>16) & 0xfe) - link_connection(5,3);
 #if TRY_HIGH_FIRST == 1
-                byte = get_linkn_first(byte);
+		byte = get_linkn_first(byte);
 #else
-       	        byte = get_linkn_last(byte);
+       		byte = get_linkn_last(byte);
 #endif
-               	print_linkn("\t-->(5,6) link=", byte);
-                setup_row_direct(5, 6, byte);
+	       	print_linkn("\t-->(5,6) link=", byte);
+		setup_row_direct(5, 6, byte);
 #if 0
-               	setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
-                for(byte=0; byte<4; byte+=2) {
-       	                setup_temp_row(byte+1,byte+3); 
-               	}
+	       	setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
+		for(byte=0; byte<4; byte+=2) {
+       			setup_temp_row(byte+1,byte+3);
+	       	}
 #endif
 		setup_temp_row(5,6);
 
-       	        verify_connection(7);
+       		verify_connection(7);
 	}
-        val = pci_read_config32(NODE_HT(7), 0x6c);
-        byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
-        print_linkn("(6,5) link=", byte);
-        setup_remote_row_direct(6, 5, byte);
-        /*Till now 56, 65 done */
+	val = pci_read_config32(NODE_HT(7), 0x6c);
+	byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
+	print_linkn("(6,5) link=", byte);
+	setup_remote_row_direct(6, 5, byte);
+	/*Till now 56, 65 done */
 #endif
-	
+
 	rename_temp_node(6);
 	enable_routing(6);
 
@@ -1292,27 +1292,27 @@
 
 	val = pci_read_config32(NODE_HT(7), 0x6c);
 	byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
-	print_linkn("(7,5) link=", byte); 
+	print_linkn("(7,5) link=", byte);
 	setup_row_local(7,7);
 	setup_remote_row_direct(7, 5, byte);
 
 #else
-        val = get_row(4,4);
-        byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6);
-        byte = get_linkn_first(byte); 
-        print_linkn("(4,7) link=", byte); 
-        setup_row_direct(4, 7, byte);
+	val = get_row(4,4);
+	byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6);
+	byte = get_linkn_first(byte);
+	print_linkn("(4,7) link=", byte);
+	setup_row_direct(4, 7, byte);
 
-        /* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/
+	/* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/
 	for(byte=0; byte<4; byte+=2) {
 		setup_temp_row(byte,byte+2);
 	}
 
-        verify_connection(7);
+	verify_connection(7);
 
 	val = pci_read_config32(NODE_HT(7), 0x6c);
 	byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
-	print_linkn("(7,4) link=", byte); 
+	print_linkn("(7,4) link=", byte);
 	setup_row_local(7,7);
 	setup_remote_row_direct(7, 4, byte);
 	/* till now 4-7, 7-4 done. */
@@ -1325,12 +1325,12 @@
 	val = get_row(5,5);
 	byte = ((val>>16) & 0xfe) - link_connection(5,3) - link_connection(5,6);
 	byte = get_linkn_first(byte);
-	print_linkn("(5,7) link=", byte); 
+	print_linkn("(5,7) link=", byte);
 	setup_row_direct(5, 7, byte);
-	
+
 	setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
 	for(byte=0; byte<4; byte+=2) {
-		setup_temp_row(byte+1,byte+3); 
+		setup_temp_row(byte+1,byte+3);
 	}
 
 	verify_connection(7);
@@ -1340,7 +1340,7 @@
 	print_linkn("(7,5) link=", byte);
 	setup_remote_row_direct(7, 5, byte);
 	/*Till now 57, 75 done */
-	
+
 #endif
 
 	/* We need to init link between 6, and 7 direct link */
@@ -1372,12 +1372,12 @@
 		2, 7,
 		3, 7,
 		4, 7,
-		
+
 		6, 1,
 		6, 2,
 		6, 3,
 		6, 5,
-		
+
 		7, 0,
 		7, 1,
 		7, 2,
@@ -1385,68 +1385,68 @@
 		7, 4,
 #else
 
-		
-                4, 5, 6, 1,
-                5, 4, 7, 1,
 
-                6, 1, 5, 0, // or 4, 1
-                6, 2, 4, 0,
-                6, 3, 5, 0, // or 4, 1
+		4, 5, 6, 1,
+		5, 4, 7, 1,
 
-                7, 0, 4, 0, // or 5, 1
-                7, 1, 5, 0,
-                7, 2, 4, 0, // or 5, 1
-                7, 3, 5, 0,
+		6, 1, 5, 0, // or 4, 1
+		6, 2, 4, 0,
+		6, 3, 5, 0, // or 4, 1
 
+		7, 0, 4, 0, // or 5, 1
+		7, 1, 5, 0,
+		7, 2, 4, 0, // or 5, 1
+		7, 3, 5, 0,
+
 		0, 7, 2, 0, /* restore it*/
 		1, 7, 3, 0,
 		2, 7, 4, 1,
 		3, 7, 5, 0,
 
-                2, 5, 4, 1, /* reset it */
-                3, 4, 5, 1,
+		2, 5, 4, 1, /* reset it */
+		3, 4, 5, 1,
 
 		4, 1, 2, 1, /* reset it */
 		4, 3, 2, 1,
 
 		5, 2, 3, 1, /* reset it */
 		5, 0, 3, 1,
-		
+
 #endif
 	};
 
 	setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3));
 
 #if CROSS_BAR_47_56
-        /* for 47, 56, 57, 75, 46, 64 we need to substract another link to 
-               6,  7,  6,  6,  7,  7 */
-        static const u8 conn8_4[] = {
+	/* for 47, 56, 57, 75, 46, 64 we need to substract another link to
+	       6,  7,  6,  6,  7,  7 */
+	static const u8 conn8_4[] = {
 //direct
-                4, 7, 6,
-                5, 6, 7, 
-		5, 7, 6, 
-		7, 5, 6,  
-		4, 6, 7, 
-		6, 4, 7, 
+		4, 7, 6,
+		5, 6, 7,
+		5, 7, 6,
+		7, 5, 6,
+		4, 6, 7,
+		6, 4, 7,
 
 //in direct
-		0, 6, 1, 
-		0, 7, 1, 
-		
-		1, 6, 0, 
-		1, 7, 0, 
+		0, 6, 1,
+		0, 7, 1,
 
-		2, 6, 3, 
+		1, 6, 0,
+		1, 7, 0,
+
+		2, 6, 3,
 //		2, 7, 3, +
-		
+
 //		3, 6, 1, +
 		3, 7, 2,
- 
+
 		6, 0, 7,
 		6, 1, 7, // needed for via 5
 			6, 1, 4, // ???
 		6, 2, 7,
-		6, 3, 7, // needed for via 5 
+		6, 3, 7, // needed for via 5
 			6, 3, 4, //???
 		7, 0, 6, // needed for via 4
 			7, 0, 5, //???
@@ -1454,21 +1454,21 @@
 		7, 2, 6, // needed for via 4
 			7, 2, 5, //???
 		7, 3, 6,
-        };
+	};
 
-        opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4));
+	opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4));
 
-        static const u8 conn8_5[] = {
-                2, 7, 0, 
+	static const u8 conn8_5[] = {
+		2, 7, 0,
 
-                3, 6, 1, 
-        };      
-                
-        opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5));
+		3, 6, 1,
+	};
+
+	opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5));
 #endif
 
 
-	
+
 /* ready to enable RT for Node 7 */
 	enable_routing(7);      /* enable routing on node 7 (temp.) */
 
@@ -1485,20 +1485,20 @@
 	unsigned nodes;
 
 	print_spew("Enabling SMP settings\r\n");
-		
+
 	nodes = setup_smp2();
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
-	if(nodes == 2) 
+	if(nodes == 2)
 		nodes = setup_smp4();
 #endif
-	
+
 #if CONFIG_MAX_PHYSICAL_CPUS > 4
 	if(nodes == 4)
 		nodes = setup_smp6();
 #endif
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 6
-	if(nodes == 6) 
+	if(nodes == 6)
 		nodes = setup_smp8();
 #endif
 
@@ -1508,20 +1508,20 @@
 	print_debug_hex8(nodes);
 	print_debug(" nodes initialized.\r\n");
 #endif
-	
+
 	return nodes;
 }
 
 static unsigned verify_mp_capabilities(unsigned nodes)
 {
 	unsigned node, mask;
-	
+
 	mask = 0x06; /* BigMPCap */
 
 	for (node=0; node<nodes; node++) {
 		mask &= pci_read_config32(NODE_MC(node), 0xe8);
 	}
-	
+
 	switch(mask) {
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 	case 0x02: /* MPCap    */
@@ -1538,7 +1538,7 @@
 		}
 		break;
 	}
-	
+
 	return nodes;
 
 }
@@ -1560,14 +1560,14 @@
 			fill_row(node, row, DEFAULT);
 		}
 	}
-	
+
 	/* Update the local row */
 	for( node=0; node<nodes; node++) {
 		uint32_t val = 0;
 		for(row =0; row<nodes; row++) {
 			val |= get_row(node, row);
 		}
-		fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101); 
+		fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101);
 	}
 }
 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
@@ -1584,7 +1584,7 @@
 	}
 
 	return totalcpus;
-		
+
 }
 #endif
 
@@ -1604,7 +1604,7 @@
 		total_cpus = nodes;
 	}
 #endif
-	
+
 	/* set up cpu count and node count and enable Limit
 	 * Config Space Range for all available CPUs.
 	 * Also clear non coherent hypertransport bus range
@@ -1631,13 +1631,13 @@
 		pci_write_config32(dev, 0x60, val);
 
 		/* Only respond to real cpu pci configuration cycles
-		 * and optimize the HT settings 
+		 * and optimize the HT settings
 		 */
 		val=pci_read_config32(dev, HT_TRANSACTION_CONTROL);
 		val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) |
 			(HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) |
 			(HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT));
-		val |= HTTC_LIMIT_CLDT_CFG | 
+		val |= HTTC_LIMIT_CLDT_CFG |
 			(HTTC_BUF_REL_PRI_8 << HTTC_BUF_REL_PRI_SHIFT) |
 			(3 << HTTC_MED_PRI_BYP_CNT_SHIFT) |
 			(3 << HTTC_HI_PRI_BYP_CNT_SHIFT);
@@ -1667,7 +1667,7 @@
 		if (is_cpu_pre_c0()) {
 
 			/* Errata 66
-			 * Limit the number of downstream posted requests to 1 
+			 * Limit the number of downstream posted requests to 1
 			 */
 			cmd = pci_read_config32(dev, 0x70);
 			if ((cmd & (3 << 0)) != 2) {
@@ -1694,7 +1694,7 @@
 		}
 		else if (is_cpu_pre_d0()) { // d0 later don't need it
 			uint32_t cmd_ref;
-			/* Errata 98 
+			/* Errata 98
 			 * Set Clk Ramp Hystersis to 7
 			 * Clock Power/Timing Low
 			 */
@@ -1728,8 +1728,8 @@
 			reg = 0x98 + (link * 0x20);
 			link_type = pci_read_config32(f0_dev, reg);
 			/* Only handle coherent links */
-			if ((link_type & (LinkConnected | InitComplete|NonCoherent)) == 
-				(LinkConnected|InitComplete)) 
+			if ((link_type & (LinkConnected | InitComplete|NonCoherent)) ==
+				(LinkConnected|InitComplete))
 			{
 				cmd &= ~(0xff << (link *8));
 				cmd |= 0x25 << (link *8);
@@ -1745,70 +1745,70 @@
 
 static inline unsigned get_nodes(void)
 {
-        return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
+	return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
 }
 
 static int optimize_link_coherent_ht(void)
 {
-        int needs_reset = 0;
+	int needs_reset = 0;
 
-        unsigned nodes;
+	unsigned nodes;
 
-        nodes = get_nodes();
+	nodes = get_nodes();
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-        if(nodes>1) {
-                needs_reset |= optimize_connection(
-                        NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
-                        NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
-        }
+	if(nodes>1) {
+		needs_reset |= optimize_connection(
+			NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
+			NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
+	}
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
-        if(nodes>2) {
-        /* optimize physical connections - by LYH */
-                static const u8 opt_conn4[] = {
-                        0,2,
-                        1,3,
-                        2,3,
-                };
-                needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4));
-        }
+	if(nodes>2) {
+	/* optimize physical connections - by LYH */
+		static const u8 opt_conn4[] = {
+			0,2,
+			1,3,
+			2,3,
+		};
+		needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4));
+	}
 #endif
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 4
-        if(nodes>4) {
-                static const uint8_t opt_conn6[] ={
-                        2, 4,
-                        3, 5,
-        #if !CROSS_BAR_47_56
-                        4, 5,
-        #endif
-                };
-                needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6));
-        }
+	if(nodes>4) {
+		static const uint8_t opt_conn6[] ={
+			2, 4,
+			3, 5,
+	#if !CROSS_BAR_47_56
+			4, 5,
+	#endif
+		};
+		needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6));
+	}
 #endif
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 6
-        if(nodes>6) {
-               static const uint8_t opt_conn8[] ={
-                       4, 6,
-        #if CROSS_BAR_47_56
-                       4, 7,
-                       5, 6,
-        #endif
-                       5, 7,
-                       6, 7,
-               };
-                needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8));
-        }
+	if(nodes>6) {
+	       static const uint8_t opt_conn8[] ={
+		       4, 6,
+	#if CROSS_BAR_47_56
+		       4, 7,
+		       5, 6,
+	#endif
+		       5, 7,
+		       6, 7,
+	       };
+		needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8));
+	}
 #endif
 
 #endif
 
-        needs_reset |= apply_cpu_errata_fixes(nodes);
-        needs_reset |= optimize_link_read_pointers(nodes);
+	needs_reset |= apply_cpu_errata_fixes(nodes);
+	needs_reset |= optimize_link_read_pointers(nodes);
 
-        return needs_reset;
+	return needs_reset;
 }
 
 #if RAMINIT_SYSINFO == 1
@@ -1823,9 +1823,9 @@
 	enable_bsp_routing();
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-        nodes = setup_smp();
-        nodes = verify_mp_capabilities(nodes);
-        clear_dead_routes(nodes);
+	nodes = setup_smp();
+	nodes = verify_mp_capabilities(nodes);
+	clear_dead_routes(nodes);
 #endif
 
 	if (nodes == 1) {

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c	2008-10-02 19:20:22 UTC (rev 3632)
@@ -7,10 +7,10 @@
 {
 #if CACHE_AS_RAM_ADDRESS_DEBUG == 1
 	#if CONFIG_USE_PRINTK_IN_CAR
-                printk_debug("------Address debug: %s%x------\r\n", str, val);
-        #else
+		printk_debug("------Address debug: %s%x------\r\n", str, val);
+	#else
 		print_debug ("------Address debug: "); print_debug(str); print_debug_hex32(val); print_debug("------\r\n");
-        #endif
+	#endif
 #endif
 }
 
@@ -32,8 +32,8 @@
 static void print_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0); 
-		dev <= PCI_DEV(0xff, 0x1f, 0x7); 
+	for(dev = PCI_DEV(0, 0, 0);
+		dev <= PCI_DEV(0xff, 0x1f, 0x7);
 		dev += PCI_DEV(0,0,1)) {
 		uint32_t id;
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
@@ -64,12 +64,12 @@
 {
 	int i;
 	print_debug_pci_dev(dev);
-	
+
 	for(i = 0; i < 256; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
 #if CONFIG_USE_PRINTK_IN_CAR
-                        printk_debug("\r\n%02x:",i);
+			printk_debug("\r\n%02x:",i);
 #else
 			print_debug("\r\n");
 			print_debug_hex8(i);
@@ -91,40 +91,40 @@
 static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index);
 static void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
 {
-        int i;
-        print_debug_pci_dev(dev);
-	print_debug(" -- index_reg="); print_debug_hex32(index_reg); 
+	int i;
+	print_debug_pci_dev(dev);
+	print_debug(" -- index_reg="); print_debug_hex32(index_reg);
 
-        for(i = 0; i < 0x40; i++) {
-                uint32_t val;
+	for(i = 0; i < 0x40; i++) {
+		uint32_t val;
 		int j;
 #if CONFIG_USE_PRINTK_IN_CAR
-                printk_debug("\r\n%02x:",i);
+		printk_debug("\r\n%02x:",i);
 #else
-                print_debug("\r\n");
-                print_debug_hex8(i);
-                print_debug_char(':');
+		print_debug("\r\n");
+		print_debug_hex8(i);
+		print_debug_char(':');
 #endif
-                val = pci_read_config32_index_wait(dev, index_reg, i);
+		val = pci_read_config32_index_wait(dev, index_reg, i);
 		for(j=0;j<4;j++) {
 #if CONFIG_USE_PRINTK_IN_CAR
-	                printk_debug(" %02x", val & 0xff);
+			printk_debug(" %02x", val & 0xff);
 #else
-	                print_debug_char(' '); print_debug_hex8(val&0xff);
+			print_debug_char(' '); print_debug_hex8(val&0xff);
 #endif
 			val >>= 8;
 		}
 
-        }
-        print_debug("\r\n");
+	}
+	print_debug("\r\n");
 }
 #endif
 
 static void dump_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0); 
-		dev <= PCI_DEV(0xff, 0x1f, 0x7); 
+	for(dev = PCI_DEV(0, 0, 0);
+		dev <= PCI_DEV(0xff, 0x1f, 0x7);
 		dev += PCI_DEV(0,0,1)) {
 		uint32_t id;
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
@@ -135,39 +135,39 @@
 		}
 		dump_pci_device(dev);
 
-                if(((dev>>12) & 0x07) == 0) {
-                        uint8_t hdr_type;
-                        hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        if((hdr_type & 0x80) != 0x80) {
-                                dev += PCI_DEV(0,0,7);
-                        }
-                }
+		if(((dev>>12) & 0x07) == 0) {
+			uint8_t hdr_type;
+			hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
+			if((hdr_type & 0x80) != 0x80) {
+				dev += PCI_DEV(0,0,7);
+			}
+		}
 	}
 }
 
 static void dump_pci_devices_on_bus(unsigned busn)
 {
-        device_t dev;
-        for(dev = PCI_DEV(busn, 0, 0);
-                dev <= PCI_DEV(busn, 0x1f, 0x7);
-                dev += PCI_DEV(0,0,1)) {
-                uint32_t id;
-                id = pci_read_config32(dev, PCI_VENDOR_ID);
-                if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
-                        (((id >> 16) & 0xffff) == 0xffff) ||
-                        (((id >> 16) & 0xffff) == 0x0000)) {
-                        continue;
-                }
-                dump_pci_device(dev);
+	device_t dev;
+	for(dev = PCI_DEV(busn, 0, 0);
+		dev <= PCI_DEV(busn, 0x1f, 0x7);
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		dump_pci_device(dev);
 
-                if(((dev>>12) & 0x07) == 0) {
-                        uint8_t hdr_type;
-                        hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        if((hdr_type & 0x80) != 0x80) {
-                                dev += PCI_DEV(0,0,7);
-                        }
-                }
-        }
+		if(((dev>>12) & 0x07) == 0) {
+			uint8_t hdr_type;
+			hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
+			if((hdr_type & 0x80) != 0x80) {
+				dev += PCI_DEV(0,0,7);
+			}
+		}
+	}
 }
 
 #ifndef DEBUG_SMBUS
@@ -187,8 +187,8 @@
 #if CONFIG_USE_PRINTK_IN_CAR
 			printk_debug("dimm: %02x.0: %02x", i, device);
 #else
-			print_debug("dimm: "); 
-			print_debug_hex8(i); 
+			print_debug("dimm: ");
+			print_debug_hex8(i);
 			print_debug(".0: ");
 			print_debug_hex8(device);
 #endif
@@ -222,10 +222,10 @@
 		if (device) {
 			int j;
 #if CONFIG_USE_PRINTK_IN_CAR
-                        printk_debug("dimm: %02x.1: %02x", i, device);
+			printk_debug("dimm: %02x.1: %02x", i, device);
 #else
-			print_debug("dimm: "); 
-			print_debug_hex8(i); 
+			print_debug("dimm: ");
+			print_debug_hex8(i);
 			print_debug(".1: ");
 			print_debug_hex8(device);
 #endif
@@ -234,7 +234,7 @@
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
 #if CONFIG_USE_PRINTK_IN_CAR
-                                        printk_debug("\r\n%02x: ", j);
+					printk_debug("\r\n%02x: ", j);
 #else
 					print_debug("\r\n");
 					print_debug_hex8(j);
@@ -247,7 +247,7 @@
 				}
 				byte = status & 0xff;
 #if CONFIG_USE_PRINTK_IN_CAR
-                                printk_debug("%02x ", byte);
+				printk_debug("%02x ", byte);
 #else
 				print_debug_hex8(byte);
 				print_debug_char(' ');
@@ -260,89 +260,89 @@
 static void dump_smbus_registers(void)
 {
 	unsigned device;
-        print_debug("\r\n");
-        for(device = 1; device < 0x80; device++) {
-                int j;
+	print_debug("\r\n");
+	for(device = 1; device < 0x80; device++) {
+		int j;
 		if( smbus_read_byte(device, 0) < 0 ) continue;
 #if CONFIG_USE_PRINTK_IN_CAR
 		printk_debug("smbus: %02x", device);
 #else
-                print_debug("smbus: ");
-                print_debug_hex8(device);
+		print_debug("smbus: ");
+		print_debug_hex8(device);
 #endif
-                for(j = 0; j < 256; j++) {
-                	int status; 
-                        unsigned char byte;
-                        status = smbus_read_byte(device, j);
-                        if (status < 0) {
+		for(j = 0; j < 256; j++) {
+			int status;
+			unsigned char byte;
+			status = smbus_read_byte(device, j);
+			if (status < 0) {
 				break;
-                        }
-                        if ((j & 0xf) == 0) {
+			}
+			if ((j & 0xf) == 0) {
 #if CONFIG_USE_PRINTK_IN_CAR
 				printk_debug("\r\n%02x: ",j);
 #else
-                	        print_debug("\r\n");
-                                print_debug_hex8(j);
-                                print_debug(": ");
+				print_debug("\r\n");
+				print_debug_hex8(j);
+				print_debug(": ");
 #endif
-                        }
-                        byte = status & 0xff;
+			}
+			byte = status & 0xff;
 #if CONFIG_USE_PRINTK_IN_CAR
-                        printk_debug("%02x ", byte);
+			printk_debug("%02x ", byte);
 #else
-                        print_debug_hex8(byte);
-                        print_debug_char(' ');
+			print_debug_hex8(byte);
+			print_debug_char(' ');
 #endif
-                }
-                print_debug("\r\n");
-	}	
+		}
+		print_debug("\r\n");
+	}
 }
 #endif
 
-static void dump_io_resources(unsigned port) 
+static void dump_io_resources(unsigned port)
 {
 
 	int i;
-        udelay(2000);
+	udelay(2000);
 #if CONFIG_USE_PRINTK_IN_CAR
 	printk_debug("%04x:\r\n", port);
 #else
-        print_debug_hex16(port);
-        print_debug(":\r\n");
+	print_debug_hex16(port);
+	print_debug(":\r\n");
 #endif
-        for(i=0;i<256;i++) {
-                uint8_t val;
-                if ((i & 0x0f) == 0) {
+	for(i=0;i<256;i++) {
+		uint8_t val;
+		if ((i & 0x0f) == 0) {
 #if CONFIG_USE_PRINTK_IN_CAR
 			printk_debug("%02x:", i);
 #else
-                        print_debug_hex8(i);
-                        print_debug_char(':');
+			print_debug_hex8(i);
+			print_debug_char(':');
 #endif
-                }
-                val = inb(port);
+		}
+		val = inb(port);
 #if CONFIG_USE_PRINTK_IN_CAR
 		printk_debug(" %02x",val);
 #else
-                print_debug_char(' ');
-                print_debug_hex8(val);
+		print_debug_char(' ');
+		print_debug_hex8(val);
 #endif
-                if ((i & 0x0f) == 0x0f) {
-                        print_debug("\r\n");
-                }
+		if ((i & 0x0f) == 0x0f) {
+			print_debug("\r\n");
+		}
 		port++;
-        }
+	}
 }
 
 static void dump_mem(unsigned start, unsigned end)
 {
-        unsigned i;
+	unsigned i;
 	print_debug("dump_mem:");
-        for(i=start;i<end;i++) {
+	for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
 #if CONFIG_USE_PRINTK_IN_CAR
 			printk_debug("\r\n%08x:", i);
-#else	
+#else
 			print_debug("\r\n");
 			print_debug_hex32(i);
 			print_debug(":");
@@ -352,9 +352,9 @@
 		printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
 #else
 		print_debug(" ");
-             	print_debug_hex8((unsigned char)*((unsigned char *)i));
+	     	print_debug_hex8((unsigned char)*((unsigned char *)i));
 #endif
-        }
-        print_debug("\r\n");
+	}
+	print_debug("\r\n");
  }
 #endif

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/early_ht.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/early_ht.c	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/early_ht.c	2008-10-02 19:20:22 UTC (rev 3632)
@@ -1,11 +1,11 @@
-/*  
+/*
 	2005.11 yhlu add let the real sb to use small unitid
 */
 // only for sb ht chain
 static void enumerate_ht_chain(void)
 {
-#if HT_CHAIN_UNITID_BASE != 0 
-/* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain  */ 
+#if HT_CHAIN_UNITID_BASE != 0
+/* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain  */
 
 	/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
 	 * On most boards this just happens.  If a cpu has multiple
@@ -43,7 +43,7 @@
 		hdr_type &= 0x7f;
 
 		if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
-			(hdr_type == PCI_HEADER_TYPE_BRIDGE)) 
+			(hdr_type == PCI_HEADER_TYPE_BRIDGE))
 		{
 			pos = pci_read_config8(dev, PCI_CAPABILITY_LIST);
 		}
@@ -71,7 +71,7 @@
 						} else {
 							goto out;
 						}
-					} 
+					}
 					real_last_unitid = next_unitid;
 					real_last_pos = pos;
 					ht_dev_num++;
@@ -115,7 +115,7 @@
 							}
 						}
 					} while((ctrl & (1 << 5)) == 0);
-	
+
 					break;
 				}
 			}
@@ -130,9 +130,9 @@
 	if((ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used) {
 		uint16_t flags;
 		dev = PCI_DEV(0,real_last_unitid, 0);
-		flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS); 
-                flags &= ~0x1f;
-                flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
+		flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS);
+	        flags &= ~0x1f;
+	        flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
 		pci_write_config16(dev, real_last_pos + PCI_CAP_FLAGS, flags);
 	}
 #endif

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c	2008-10-02 19:20:22 UTC (rev 3632)
@@ -35,36 +35,36 @@
 #if 0
 unsigned node_link_to_bus(unsigned node, unsigned link)
 {
-        device_t dev;
-        unsigned reg;
+	device_t dev;
+	unsigned reg;
 
-        dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
-        if (!dev) {
-                return 0;
-        }
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                uint32_t config_map;
-                unsigned dst_node;
-                unsigned dst_link;
-                unsigned bus_base;
-                config_map = pci_read_config32(dev, reg);
-                if ((config_map & 3) != 3) {
-                        continue;
-                }
-                dst_node = (config_map >> 4) & 7;
-                dst_link = (config_map >> 8) & 3;
-                bus_base = (config_map >> 16) & 0xff;
+	dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+	if (!dev) {
+		return 0;
+	}
+	for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+		uint32_t config_map;
+		unsigned dst_node;
+		unsigned dst_link;
+		unsigned bus_base;
+		config_map = pci_read_config32(dev, reg);
+		if ((config_map & 3) != 3) {
+			continue;
+		}
+		dst_node = (config_map >> 4) & 7;
+		dst_link = (config_map >> 8) & 3;
+		bus_base = (config_map >> 16) & 0xff;
 #if 0
-                printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
-                        dst_node, dst_link, bus_base,
-                        reg, config_map);
+		printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+			dst_node, dst_link, bus_base,
+			reg, config_map);
 #endif
-                if ((dst_node == node) && (dst_link == link))
-                {
-                        return bus_base;
-                }
-        }
-        return 0;
+		if ((dst_node == node) && (dst_link == link))
+		{
+			return bus_base;
+		}
+	}
+	return 0;
 }
 #endif
 
@@ -87,8 +87,8 @@
  * So we need to make sure that the south bridge link will always be on
  * pci1234[0].
  *
- * Imagine a scenario with multiple HT I/O cards, where you don't install HT I/O 1, 
- * but you only install HT I/O 2 and HT I/O 3. The HT I/Os  will end up in registers 
+ * Imagine a scenario with multiple HT I/O cards, where you don't install HT I/O 1,
+ * but you only install HT I/O 2 and HT I/O 3. The HT I/Os  will end up in registers
  * 0xE4 and 0xE8.
  *
  * But we want to leave pci1234[1] to HT I/O 1 (even though it is disabled),
@@ -119,7 +119,7 @@
  *     };
  *
  *
- * For 4p+htio(n1)+htio(n2)+htio(n3),4p+htio(n1)+4p+htio(n6)+htio(n7):  
+ * For 4p+htio(n1)+htio(n2)+htio(n3),4p+htio(n1)+4p+htio(n6)+htio(n7):
  * You need an array pci1234[6]:
  *
  *     unsigned pci1234[] = {
@@ -130,10 +130,10 @@
  *             0x0000f60, // HT IO 4 card always on node 6
  *             0x0000f70  // HT IO 5 card always on node 7
  *     };
- * 
- * 
- * For 2p + htio(n1) + htio(n0_1) + htio(n1_1), 2P + htio(n1) + 2P + 
- * htio(n2) + htio(n3), 2P + htio(n1) + 4P + htio(n4) + htio(n5), 
+ *
+ *
+ * For 2p + htio(n1) + htio(n0_1) + htio(n1_1), 2P + htio(n1) + 2P +
+ * htio(n2) + htio(n3), 2P + htio(n1) + 4P + htio(n4) + htio(n5),
  * you need an array pci1234[8]:
  *
  *     unsigned pci1234[] = {
@@ -146,10 +146,10 @@
  *             0x0000f40, // HT IO 6 card always on node 4
  *             0x0000f50  // HT IO 7 card always on node 5
  *     };
- * 
- * 
+ *
+ *
  * For 4P + htio(n1) + htio(n2) + htio(n3), 4p + htio(n1) + 2p + htio(n4) +
- * htio(n5), 4p + htio(n1) + 4p + htio(n6) + htio(n7), 
+ * htio(n5), 4p + htio(n1) + 4p + htio(n6) + htio(n7),
  * you need an array pci1234[8]:
  *
  *     unsigned pci1234[] = {
@@ -162,53 +162,53 @@
  *             0x0000f60, // HT IO 6 card always on node 6
  *             0x0000f70  // HT IO 7 card always on node 7
  *     };
- * 
- * 
+ *
+ *
  * So the maximum posible value of HC_POSSIBLE_NUM is 8. (FIXME Why?)
- * 
+ *
  *     1n:       3
  *     2n: 2x2 - 1
- *     4n: 1x4 - 2 
- *     6n:       2 
- *     8n:       2 
- *  Total:      12 
- * 
- * Just put all the possible HT Node/link to the list tp pci1234[] in 
+ *     4n: 1x4 - 2
+ *     6n:       2
+ *     8n:       2
+ *  Total:      12
+ *
+ * Just put all the possible HT Node/link to the list tp pci1234[] in
  * src/mainboard/<vendor>/<mainboard>get_bus_conf.c
- * 
+ *
  * Also don't forget to increase the ACPI_SSDTX_NUM etc (FIXME what else) if
  * you have too many SSDTs
- * 
+ *
  * What about co-processor in socket 1 on a 2 way system? Or socket 2 and
  * socket 3 on a 4 way system? Treat that as an HC, too!
- * 
+ *
  */
 
 void get_sblk_pci1234(void)
 {
 
-        device_t dev;
-        int i,j;
-        uint32_t dword;
+	device_t dev;
+	int i,j;
+	uint32_t dword;
 
-        /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
-        dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
-        dword = pci_read_config32(dev, 0x64);
-        sysconf.sblk = (dword>>8) & 0x3;
+	/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
+	dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
+	dword = pci_read_config32(dev, 0x64);
+	sysconf.sblk = (dword>>8) & 0x3;
 
-        dword &=0x0300;
-        dword |= 1;
-        sysconf.pci1234[0] = dword;
+	dword &=0x0300;
+	dword |= 1;
+	sysconf.pci1234[0] = dword;
 	sysconf.hcid[0] = 0;
 
-        /* About hardcoded numbering for HT_IO support
+	/* About hardcoded numbering for HT_IO support
 	 *
 	 * Set the node_id and link_id that could have a HT chain in the one
 	 * array, (FIXME: which one?) then check if is enabled. Then update
-	 * final value 
-         */
+	 * final value
+	 */
 
-        /* Here we need to set hcdn
+	/* Here we need to set hcdn
 	 *
 	 * 1. hypertransport.c needs to record hcdn_reg together with 0xe0,
 	 *    0xe4, 0xe8, 0xec when are set (FIXME: when WHAT is set?)
@@ -216,48 +216,48 @@
 	 * 2. So at the same time we need update hcdn with hcdn_reg here. FIXME: Why?
 	 */
 
-        dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+	dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
 
-        for(j=0;j<4;j++) {
-                uint32_t dwordx;
-                dwordx = pci_read_config32(dev, 0xe0 + j*4);
-                dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */
-                if((dwordx & 0xff1) == dword) { /* SBLINK */
-                        sysconf.pci1234[0] = dwordx;
+	for(j=0;j<4;j++) {
+		uint32_t dwordx;
+		dwordx = pci_read_config32(dev, 0xe0 + j*4);
+		dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */
+		if((dwordx & 0xff1) == dword) { /* SBLINK */
+			sysconf.pci1234[0] = dwordx;
 			sysconf.hcdn[0] = sysconf.hcdn_reg[j];
-                        continue;
-                }
+			continue;
+		}
 
-                if((dwordx & 1) == 1) {
-                        /* We need to find out the number of HC
-                         * for exact match
+		if((dwordx & 1) == 1) {
+			/* We need to find out the number of HC
+			 * for exact match
 			 */
-                        for(i=1;i<sysconf.hc_possible_num;i++) {
-                                if((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) {
-                                        sysconf.pci1234[i] = dwordx;
+			for(i=1;i<sysconf.hc_possible_num;i++) {
+				if((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) {
+					sysconf.pci1234[i] = dwordx;
 					sysconf.hcdn[i] = sysconf.hcdn_reg[j];
-                                        break;
-                                }
-                        }
+					break;
+				}
+			}
 
-                        /* For 0xff0 match or same node */
-                        for(i=1;i<sysconf.hc_possible_num;i++) {
-                                if((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) {
-                                        sysconf.pci1234[i] = dwordx;
+			/* For 0xff0 match or same node */
+			for(i=1;i<sysconf.hc_possible_num;i++) {
+				if((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) {
+					sysconf.pci1234[i] = dwordx;
 					sysconf.hcdn[i] = sysconf.hcdn_reg[j];
-                                        break;
-                                }
-                        }
-                }
-        }
+					break;
+				}
+			}
+		}
+	}
 
-        for(i=1;i<sysconf.hc_possible_num;i++) {
-                if((sysconf.pci1234[i] & 1) != 1) {
-                        sysconf.pci1234[i] = 0;
+	for(i=1;i<sysconf.hc_possible_num;i++) {
+		if((sysconf.pci1234[i] & 1) != 1) {
+			sysconf.pci1234[i] = 0;
 			sysconf.hcdn[i] = 0x20202020;
-                }
+		}
 		sysconf.hcid[i] = 0;
-        }
+	}
 
 }
 

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c	2008-10-02 19:20:22 UTC (rev 3632)
@@ -8,7 +8,7 @@
 #include <device/hypertransport_def.h>
 
 #ifndef K8_HT_FREQ_1G_SUPPORT
-        #define K8_HT_FREQ_1G_SUPPORT 0
+	#define K8_HT_FREQ_1G_SUPPORT 0
 #endif
 
 #ifndef K8_SCAN_PCI_BUS
@@ -16,20 +16,20 @@
 #endif
 
 #ifndef K8_ALLOCATE_IO_RANGE
-        #define K8_ALLOCATE_IO_RANGE 0
+	#define K8_ALLOCATE_IO_RANGE 0
 #endif
 
-// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM 
+// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
 #ifndef K8_ALLOCATE_MMIO_RANGE
-        #define K8_ALLOCATE_MMIO_RANGE 0
+	#define K8_ALLOCATE_MMIO_RANGE 0
 #endif
 
 static inline void print_linkn_in (const char *strval, uint8_t byteval)
 {
 #if CONFIG_USE_PRINTK_IN_CAR
-        printk_debug("%s%02x\r\n", strval, byteval); 
+	printk_debug("%s%02x\r\n", strval, byteval);
 #else
-        print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
+	print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
 #endif
 }
 
@@ -67,13 +67,13 @@
 }
 
 static uint8_t ht_lookup_slave_capability(device_t dev)
-{          
+{
 	return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format
 }
 
 static uint8_t ht_lookup_host_capability(device_t dev)
 {
-        return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format
+	return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format
 }
 
 static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid)
@@ -91,12 +91,12 @@
 	/* Check if is already collapsed */
 	if((!offset_unitid) || (offset_unitid && (!((HT_CHAIN_END_UNITID_BASE == 0) && (HT_CHAIN_END_UNITID_BASE <HT_CHAIN_UNITID_BASE))))) {
 		dev = PCI_DEV(bus, 0, 0);
-        	id = pci_read_config32(dev, PCI_VENDOR_ID);
-	        if ( ! ( (id == 0xffffffff) || (id == 0x00000000) ||
-        	    (id == 0x0000ffff) || (id == 0xffff0000) ) ) {
-	                     return;
-        	}
-	} 
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (!((id == 0xffffffff) || (id == 0x00000000) ||
+		      (id == 0x0000ffff) || (id == 0xffff0000))) {
+			return;
+		}
+	}
 
 	/* Spin through the devices and collapse any previous
 	 * hypertransport enumeration.
@@ -105,13 +105,13 @@
 		uint32_t id;
 		uint8_t pos;
 		uint16_t flags;
-		
+
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
 		if ((id == 0xffffffff) || (id == 0x00000000) ||
 		    (id == 0x0000ffff) || (id == 0xffff0000)) {
 			continue;
 		}
-		
+
 		pos = ht_lookup_slave_capability(dev);
 		if (!pos) {
 			continue;
@@ -145,23 +145,24 @@
 	if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8151_SYSCTRL << 16))) {
 		freq_cap &= ~(1 << HT_FREQ_800Mhz);
 		return freq_cap;
-	} 
-	
+	}
+
 	/* AMD K8 Unsupported 1Ghz? */
 	if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
-	#if K8_HT_FREQ_1G_SUPPORT == 1 
-		#if K8_REV_F_SUPPORT == 0 
-	        if (is_cpu_pre_e0()) {  // only E0 later support 1GHz
+	#if K8_HT_FREQ_1G_SUPPORT == 1
+		#if K8_REV_F_SUPPORT == 0
+		if (is_cpu_pre_e0()) {  // only E0 later support 1GHz
 			freq_cap &= ~(1 << HT_FREQ_1000Mhz);
 		}
 		#endif
-	#else	
-                freq_cap &= ~(1 << HT_FREQ_1000Mhz);
+	#else
+		freq_cap &= ~(1 << HT_FREQ_1000Mhz);
 	#endif
 	}
 
 	return freq_cap;
 }
+
 static uint8_t ht_read_width_cap(device_t dev, uint8_t pos)
 {
 	uint8_t width_cap = pci_read_config8(dev, pos);
@@ -176,12 +177,13 @@
 			width_cap &= 0x88;
 		}
 	}
-	
+
 	return width_cap;
-	
+
 }
+
 #define LINK_OFFS(CTRL, WIDTH,FREQ,FREQ_CAP) \
-      (((CTRL & 0xff) << 24) | ((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
+	(((CTRL & 0xff) << 24) | ((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
 
 #define LINK_CTRL(OFFS)     ((OFFS >> 24) & 0xFF)
 #define LINK_WIDTH(OFFS)    ((OFFS >> 16) & 0xFF)
@@ -189,19 +191,19 @@
 #define LINK_FREQ_CAP(OFFS) ((OFFS) & 0xFF)
 
 #define PCI_HT_HOST_OFFS LINK_OFFS(		\
-		PCI_HT_CAP_HOST_CTRL,           \
+		PCI_HT_CAP_HOST_CTRL,		\
 		PCI_HT_CAP_HOST_WIDTH,		\
 		PCI_HT_CAP_HOST_FREQ,		\
 		PCI_HT_CAP_HOST_FREQ_CAP)
 
 #define PCI_HT_SLAVE0_OFFS LINK_OFFS(		\
-		PCI_HT_CAP_SLAVE_CTRL0,         \
+		PCI_HT_CAP_SLAVE_CTRL0,		\
 		PCI_HT_CAP_SLAVE_WIDTH0,	\
 		PCI_HT_CAP_SLAVE_FREQ0,		\
 		PCI_HT_CAP_SLAVE_FREQ_CAP0)
 
 #define PCI_HT_SLAVE1_OFFS LINK_OFFS(		\
-		PCI_HT_CAP_SLAVE_CTRL1,         \
+		PCI_HT_CAP_SLAVE_CTRL1,		\
 		PCI_HT_CAP_SLAVE_WIDTH1,	\
 		PCI_HT_CAP_SLAVE_FREQ1,		\
 		PCI_HT_CAP_SLAVE_FREQ_CAP1)
@@ -280,22 +282,23 @@
 
 	return needs_reset;
 }
+
 #if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1)
 
 #if RAMINIT_SYSINFO == 1
 static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo);
-static int scan_pci_bus( unsigned bus , struct sys_info *sysinfo) 
+static int scan_pci_bus( unsigned bus , struct sys_info *sysinfo)
 #else
 static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid);
 static int scan_pci_bus( unsigned bus)
 #endif
 {
-        /*      
-                here we already can access PCI_DEV(bus, 0, 0) to PCI_DEV(bus, 0x1f, 0x7)
-                So We can scan these devices to find out if they are bridge 
-                If it is pci bridge, We need to set busn in bridge, and go on
-                For ht bridge, We need to set the busn in bridge and ht_setup_chainx, and the scan_pci_bus
-        */    
+	/*
+		here we already can access PCI_DEV(bus, 0, 0) to PCI_DEV(bus, 0x1f, 0x7)
+		So We can scan these devices to find out if they are bridge
+		If it is pci bridge, We need to set busn in bridge, and go on
+		For ht bridge, We need to set the busn in bridge and ht_setup_chainx, and the scan_pci_bus
+	*/
 	unsigned int devfn;
 	unsigned new_bus;
 	unsigned max_bus;
@@ -314,85 +317,85 @@
 
 	new_bus = bus;
 
-	for (devfn = 0; devfn <= 0xff; devfn++) { 
-	        uint8_t hdr_type;
-	        uint16_t class;
+	for (devfn = 0; devfn <= 0xff; devfn++) {
+		uint8_t hdr_type;
+		uint16_t class;
 		uint32_t buses;
 		device_t dev;
 		uint16_t cr;
 		dev = PCI_DEV((bus & 0xff), ((devfn>>3) & 0x1f), (devfn & 0x7));
-                hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
-                class = pci_read_config16(dev, PCI_CLASS_DEVICE);
+		hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
+		class = pci_read_config16(dev, PCI_CLASS_DEVICE);
 
 		switch(hdr_type & 0x7f) {  /* header type */
-		        case PCI_HEADER_TYPE_BRIDGE:
-		                if (class  != PCI_CLASS_BRIDGE_PCI) goto bad;
+			case PCI_HEADER_TYPE_BRIDGE:
+				if (class  != PCI_CLASS_BRIDGE_PCI) goto bad;
 				/* set the bus range dev */
 
-			        /* Clear all status bits and turn off memory, I/O and master enables. */
-			        cr = pci_read_config16(dev, PCI_COMMAND);
-			        pci_write_config16(dev, PCI_COMMAND, 0x0000);
-			        pci_write_config16(dev, PCI_STATUS, 0xffff);
+				/* Clear all status bits and turn off memory, I/O and master enables. */
+				cr = pci_read_config16(dev, PCI_COMMAND);
+				pci_write_config16(dev, PCI_COMMAND, 0x0000);
+				pci_write_config16(dev, PCI_STATUS, 0xffff);
 
-			        buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
 
-			        buses &= 0xff000000;
+				buses &= 0xff000000;
 				new_bus++;
-			        buses |= (((unsigned int) (bus & 0xff) << 0) |
-			                ((unsigned int) (new_bus & 0xff) << 8) |
-			                ((unsigned int) max_bus << 16));
-			        pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
-				
+				buses |= (((unsigned int) (bus & 0xff) << 0) |
+					((unsigned int) (new_bus & 0xff) << 8) |
+					((unsigned int) max_bus << 16));
+				pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
+
 				/* here we need to figure out if dev is a ht bridge
 					if it is ht bridge, we need to call ht_setup_chainx at first
-				   Not verified --- yhlu
+					Not verified --- yhlu
 				*/
 				uint8_t upos;
-		                upos = ht_lookup_host_capability(dev); // one func one ht sub
-		                if (upos) { // sub ht chain
+				upos = ht_lookup_host_capability(dev); // one func one ht sub
+				if (upos) { // sub ht chain
 					uint8_t busn;
 					busn = (new_bus & 0xff);
-			                /* Make certain the HT bus is not enumerated */
-			                ht_collapse_previous_enumeration(busn, 0);
+					/* Make certain the HT bus is not enumerated */
+					ht_collapse_previous_enumeration(busn, 0);
 					/* scan the ht chain */
 					#if RAMINIT_SYSINFO == 1
-			                ht_setup_chainx(dev,upos,busn, 0, sysinfo); // don't need offset unitid
+					ht_setup_chainx(dev,upos,busn, 0, sysinfo); // don't need offset unitid
 					#else
 					new_bus |= (ht_setup_chainx(dev, upos, busn, 0)<<16); // store reset_needed to upword
 					#endif
-		                }
-				
-				#if RAMINIT_SYSINFO == 1				
+				}
+
+				#if RAMINIT_SYSINFO == 1
 				new_bus = scan_pci_bus(new_bus, sysinfo);
 				#else
 				new_bus = scan_pci_bus(new_bus);
 				#endif
 				/* set real max bus num in that */
 
-			        buses = (buses & 0xff00ffff) |
-			                ((unsigned int) (new_bus & 0xff) << 16);
-			        pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
+				buses = (buses & 0xff00ffff) |
+					((unsigned int) (new_bus & 0xff) << 16);
+				pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
 
 				pci_write_config16(dev, PCI_COMMAND, cr);
 
-                		break;  
-        		default:
-		        bad:
+				break;
+			default:
+			bad:
 				;
-        	}
+		}
 
-                /* if this is not a multi function device, 
-                 * or the device is not present don't waste
-                 * time probing another function. 
-                 * Skip to next device. 
-                 */
-                if ( ((devfn & 0x07) == 0x00) && ((hdr_type & 0x80) != 0x80))
-                {
-                        devfn += 0x07;
-                }
-        }
-	
-	return new_bus; 
+		/* if this is not a multi function device,
+		 * or the device is not present don't waste
+		 * time probing another function.
+		 * Skip to next device.
+		 */
+		if ( ((devfn & 0x07) == 0x00) && ((hdr_type & 0x80) != 0x80))
+		{
+			devfn += 0x07;
+		}
+	}
+
+	return new_bus;
 }
 #endif
 
@@ -412,9 +415,9 @@
 #endif
 
 #if HT_CHAIN_END_UNITID_BASE != 0x20
-        //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE
-        unsigned real_last_unitid;
-        uint8_t real_last_pos;
+	//let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE
+	unsigned real_last_unitid;
+	uint8_t real_last_pos;
 	int ht_dev_num = 0;
 	uint8_t end_used = 0;
 #endif
@@ -428,50 +431,50 @@
 		uint16_t flags, ctrl;
 		uint8_t count;
 		unsigned offs;
-	
+
 		/* Wait until the link initialization is complete */
 		do {
 			ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
 			/* Is this the end of the hypertransport chain? */
 			if (ctrl & (1 << 6)) {
-				goto end_of_chain;	
+				goto end_of_chain;
 			}
 
 			if (ctrl & ((1 << 4) | (1 << 8))) {
-                               /*
-				* Either the link has failed, or we have
-                                * a CRC error.
-                                * Sometimes this can happen due to link
-                                * retrain, so lets knock it down and see
-                                * if its transient
-                                */
+				/*
+				 * Either the link has failed, or we have
+				 * a CRC error.
+				 * Sometimes this can happen due to link
+				 * retrain, so lets knock it down and see
+				 * if its transient
+				 */
 				ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
-                                pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl);
-                                ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
-                                if (ctrl & ((1 << 4) | (1 << 8))) {
-                                	print_err("Detected error on Hypertransport Link\n");
+				pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl);
+				ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
+				if (ctrl & ((1 << 4) | (1 << 8))) {
+					print_err("Detected error on Hypertransport Link\n");
 					break;
-                                }
+				}
 			}
 		} while((ctrl & (1 << 5)) == 0);
-	
+
 		device_t dev = PCI_DEV(bus, 0, 0);
 		last_unitid = next_unitid;
 
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
 
 		/* If the chain is enumerated quit */
-		if (    (id == 0xffffffff) || (id == 0x00000000) ||
-			(id == 0x0000ffff) || (id == 0xffff0000))
+		if ((id == 0xffffffff) || (id == 0x00000000) ||
+		    (id == 0x0000ffff) || (id == 0xffff0000))
 		{
 			break;
 		}
 
 		pos = ht_lookup_slave_capability(dev);
 		if (!pos) {
-                        print_err("udev="); print_err_hex32(udev);
-                        print_err("\tupos="); print_err_hex32(upos);
-                        print_err("\tuoffs="); print_err_hex32(uoffs);
+			print_err("udev="); print_err_hex32(udev);
+			print_err("\tupos="); print_err_hex32(upos);
+			print_err("\tuoffs="); print_err_hex32(uoffs);
 			print_err("\tHT link capability not found\r\n");
 			break;
 		}
@@ -481,17 +484,17 @@
 		if(offset_unitid) {
 			if(next_unitid>= (bus ? 0x20:0x18) ) {
 				if(!end_used) {
-			                next_unitid = HT_CHAIN_END_UNITID_BASE;
+					next_unitid = HT_CHAIN_END_UNITID_BASE;
 					end_used = 1;
 				} else {
 					goto out;
 				}
-				
-			} 
-        	        real_last_pos = pos;
+
+			}
+			real_last_pos = pos;
 			real_last_unitid = next_unitid;
 			ht_dev_num++;
-		} 
+		}
 #endif
 		/* Update the Unitid of the current device */
 		flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
@@ -499,23 +502,23 @@
 		flags |= next_unitid & 0x1f;
 		pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
 
-                /* Compute the number of unitids consumed */
-                count = (flags >> 5) & 0x1f;
+		/* Compute the number of unitids consumed */
+		count = (flags >> 5) & 0x1f;
 
 		/* Note the change in device number */
 		dev = PCI_DEV(bus, next_unitid, 0);
 
-                next_unitid += count;
+		next_unitid += count;
 
 		/* Find which side of the ht link we are on,
 		 * by reading which direction our last write to PCI_CAP_FLAGS
 		 * came from.
 		 */
 		flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
-                offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
-               
+		offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
+
 		#if RAMINIT_SYSINFO == 1
-                /* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */
+		/* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */
 		{
 			struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num];
 			link_pair->udev = udev;
@@ -539,32 +542,32 @@
 
 out:
 end_of_chain: ;
-	
+
 #if HT_CHAIN_END_UNITID_BASE != 0x20
-        if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used ) {
-                uint16_t flags;
+	if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used ) {
+		uint16_t flags;
 		int i;
-                flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
-                flags &= ~0x1f;
-                flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
-                pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
+		flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
+		flags &= ~0x1f;
+		flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
+		pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
 
-                #if RAMINIT_SYSINFO == 1
+		#if RAMINIT_SYSINFO == 1
 		// Here need to change the dev in the array
 		for(i=0;i<sysinfo->link_pair_num;i++)
-                {
-                        struct link_pair_st *link_pair = &sysinfo->link_pair[i];
-                        if(link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) {
+		{
+			struct link_pair_st *link_pair = &sysinfo->link_pair[i];
+			if(link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) {
 				link_pair->udev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0);
 				continue;
 			}
-                        if(link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) {
-                                link_pair->dev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0);
-                        }
-                }
+			if(link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) {
+				link_pair->dev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0);
+			}
+		}
 		#endif
 
-        }
+	}
 #endif
 
 #if RAMINIT_SYSINFO == 0
@@ -581,55 +584,55 @@
 {
 	unsigned offset_unitid = 0;
 #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
-        offset_unitid = 1;
+	offset_unitid = 1;
 #endif
 
-        /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
-         * On most boards this just happens.  If a cpu has multiple
-         * non Coherent links the appropriate bus registers for the
-         * links needs to be programed to point at bus 0.
-         */
+	/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
+	 * On most boards this just happens.  If a cpu has multiple
+	 * non Coherent links the appropriate bus registers for the
+	 * links needs to be programed to point at bus 0.
+	 */
 
-        /* Make certain the HT bus is not enumerated */
-        ht_collapse_previous_enumeration(0, 0);
+	/* Make certain the HT bus is not enumerated */
+	ht_collapse_previous_enumeration(0, 0);
 
 #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
-        offset_unitid = 1;
+	offset_unitid = 1;
 #endif
 
 #if RAMINIT_SYSINFO == 1
 	ht_setup_chainx(udev, upos, 0, offset_unitid, sysinfo);
 #else
-        return ht_setup_chainx(udev, upos, 0, offset_unitid);
+	return ht_setup_chainx(udev, upos, 0, offset_unitid);
 #endif
 }
 static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val)
 {
 	uint32_t dword, dword_old;
 	uint8_t link_type;
-	
+
 	/* This works on an Athlon64 because unimplemented links return 0 */
 	dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20));
 	link_type = dword & 0xff;
-	
-	
+
+
 	if ( (link_type & 7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
 		dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,3), 0xdc);
 		dword &= ~( 0xff<<(linkn *8) );
 		dword |= val << (linkn *8);
-	
+
 		if (dword != dword_old) {
 			pci_write_config32(PCI_DEV(0,0x18+node,3), 0xdc, dword);
 			return 1;
 		}
 	}
-	
+
 	return 0;
 }
 
 static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
 {
-	int reset_needed; 
+	int reset_needed;
 	uint8_t i;
 
 	reset_needed = 0;
@@ -642,14 +645,14 @@
 		unsigned devn = 1;
 
 	#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
-                #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
-                if(i==0) // to check if it is sb ht chain
-                #endif
-                        devn = HT_CHAIN_UNITID_BASE;
-        #endif
+		#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+		if(i==0) // to check if it is sb ht chain
+		#endif
+			devn = HT_CHAIN_UNITID_BASE;
+	#endif
 
 		reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
-		
+
 		nodeid = ((reg & 0xf0)>>4); // nodeid
 		linkn = ((reg & 0xf00)>>8); // link n
 		busn = (reg & 0xff0000)>>16; //busn
@@ -672,59 +675,59 @@
 
 static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
 {
-        uint32_t dword;
-        uint8_t link_type;
+	uint32_t dword;
+	uint8_t link_type;
 	unsigned regpos;
 	device_t dev;
 
-        /* This works on an Athlon64 because unimplemented links return 0 */
+	/* This works on an Athlon64 because unimplemented links return 0 */
 	regpos = 0x98 + (linkn * 0x20);
 	dev = PCI_DEV(0,0x18+node,0);
-        dword = pci_read_config32(dev, regpos);
-        link_type = dword & 0xff;
+	dword = pci_read_config32(dev, regpos);
+	link_type = dword & 0xff;
 
-        if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
+	if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
 		regpos = 0x90 + (linkn * 0x20);
-        	dword = pci_read_config32(dev, regpos );
+		dword = pci_read_config32(dev, regpos );
 
-	        if (dword != val) {
-        	        pci_write_config32(dev, regpos, val);
-	                return 1;
-        	}
+		if (dword != val) {
+			pci_write_config32(dev, regpos, val);
+			return 1;
+		}
 	}
 
-        return 0;
+	return 0;
 }
 static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid,  unsigned val)
 {
-        int reset_needed;
-        uint8_t i;
+	int reset_needed;
+	uint8_t i;
 
-        reset_needed = 0;
+	reset_needed = 0;
 
-        for (i = 0; i < ht_c_num; i++) {
-                uint32_t reg;
-                uint8_t nodeid, linkn;
-                uint8_t busn;
-                unsigned devn;
+	for (i = 0; i < ht_c_num; i++) {
+		uint32_t reg;
+		uint8_t nodeid, linkn;
+		uint8_t busn;
+		unsigned devn;
 
-                reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
-                if((reg & 3) != 3) continue; // not enabled
+		reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
+		if((reg & 3) != 3) continue; // not enabled
 
-                nodeid = ((reg & 0xf0)>>4); // nodeid
-                linkn = ((reg & 0xf00)>>8); // link n
-                busn = (reg & 0xff0000)>>16; //busn
+		nodeid = ((reg & 0xf0)>>4); // nodeid
+		linkn = ((reg & 0xf00)>>8); // link n
+		busn = (reg & 0xff0000)>>16; //busn
 
 		for(devn = 0; devn < 0x20; devn++) {
-	                reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
-        	        if ( (reg & 0xffff) == vendorid ) {
-                	        reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
+			reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
+			if ( (reg & 0xffff) == vendorid ) {
+				reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
 				break;
-                	}
+			}
 		}
-        }
+	}
 
-        return reset_needed;
+	return reset_needed;
 }
 
 
@@ -734,13 +737,13 @@
 static int ht_setup_chains(uint8_t ht_c_num)
 #endif
 {
-	/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. 
+	/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
 	 * On most boards this just happens.  If a cpu has multiple
 	 * non Coherent links the appropriate bus registers for the
 	 * links needs to be programed to point at bus 0.
 	 */
-        uint8_t upos;
-        device_t udev;
+	uint8_t upos;
+	device_t udev;
 	uint8_t i;
 
 #if RAMINIT_SYSINFO == 0
@@ -760,30 +763,30 @@
 		unsigned bus;
 		#endif
 		unsigned offset_unitid = 0;
-		
+
 		reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
 
 		//We need setup 0x94, 0xb4, and 0xd4 according to the reg
 		devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19
 		regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4;
 		busn = (reg & 0xff0000)>>16;
-		
+
 		dword = pci_read_config32( PCI_DEV(0, devpos, 0), regpos) ;
 		dword &= ~(0xffff<<8);
 		dword |= (reg & 0xffff0000)>>8;
 		pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword);
-	
 
+
 	#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
-                #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
-                if(i==0) // to check if it is sb ht chain
-                #endif
-                        offset_unitid = 1;
-        #endif
-	
-	        /* Make certain the HT bus is not enumerated */
-        	ht_collapse_previous_enumeration(busn, offset_unitid);
+		#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+		if(i==0) // to check if it is sb ht chain
+		#endif
+			offset_unitid = 1;
+	#endif
 
+		/* Make certain the HT bus is not enumerated */
+		ht_collapse_previous_enumeration(busn, offset_unitid);
+
 		upos = ((reg & 0xf00)>>8) * 0x20 + 0x80;
 		udev =  PCI_DEV(0, devpos, 0);
 
@@ -794,10 +797,10 @@
 #endif
 
 		#if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1)
-	        /* You can use use this in romcc, because there is function call in romcc, recursive will kill you */
-		bus = busn; // we need 32 bit 
+		/* You can use use this in romcc, because there is function call in romcc, recursive will kill you */
+		bus = busn; // we need 32 bit
 #if RAMINIT_SYSINFO == 1
-        	scan_pci_bus(bus, sysinfo);
+		scan_pci_bus(bus, sysinfo);
 #else
 		reset_needed |= (scan_pci_bus(bus)>>16); // take out reset_needed that stored in upword
 #endif
@@ -821,30 +824,30 @@
 #else
 static int ht_setup_chains_x(void)
 #endif
-{               
-        uint8_t nodeid;
-        uint32_t reg; 
+{
+	uint8_t nodeid;
+	uint32_t reg;
 	uint32_t tempreg;
-        uint8_t next_busn;
-        uint8_t ht_c_num;
+	uint8_t next_busn;
+	uint8_t ht_c_num;
 	uint8_t nodes;
-#if K8_ALLOCATE_IO_RANGE == 1	
+#if K8_ALLOCATE_IO_RANGE == 1
 	unsigned next_io_base;
 #endif
 
-	nodes = get_nodes();     
- 
-        /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
-        reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
-        /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */
+	nodes = get_nodes();
+
+	/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
+	reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
+	/* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */
 	print_linkn_in("SBLink=", ((reg>>8) & 3) );
 #if RAMINIT_SYSINFO == 1
 	sysinfo->sblk = (reg>>8) & 3;
 	sysinfo->sbbusn = 0;
 	sysinfo->nodes = nodes;
 #endif
-        tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24);
-        pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg);
+	tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24);
+	pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg);
 
 	next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
 
@@ -858,95 +861,95 @@
 #endif
 
 	/* clean others */
-        for(ht_c_num=1;ht_c_num<4; ht_c_num++) {
-                pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
+	for(ht_c_num=1;ht_c_num<4; ht_c_num++) {
+		pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
 
 #if K8_ALLOCATE_IO_RANGE == 1
 		/* io range allocation */
 		pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0);
 		pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0);
 #endif
-        }
- 
-        for(nodeid=0; nodeid<nodes; nodeid++) {
-                device_t dev; 
-                uint8_t linkn;
-                dev = PCI_DEV(0, 0x18+nodeid,0);
-                for(linkn = 0; linkn<3; linkn++) {
-                        unsigned regpos;
-                        regpos = 0x98 + 0x20 * linkn;
-                        reg = pci_read_config32(dev, regpos);
-                        if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/
+	}
+
+	for(nodeid=0; nodeid<nodes; nodeid++) {
+		device_t dev;
+		uint8_t linkn;
+		dev = PCI_DEV(0, 0x18+nodeid,0);
+		for(linkn = 0; linkn<3; linkn++) {
+			unsigned regpos;
+			regpos = 0x98 + 0x20 * linkn;
+			reg = pci_read_config32(dev, regpos);
+			if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/
 			print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf));
-                        tempreg = 3 | (nodeid <<4) | (linkn<<8);
-                        /*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */
-                        for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
-                                reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
-                                if(((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) {  /*we got it*/
-                                        break;
-                                }
-                        }
-                        if(ht_c_num == 4) break; /*used up only 4 non conherent allowed*/
-                        /*update to 0xe0...*/
+			tempreg = 3 | (nodeid <<4) | (linkn<<8);
+			/*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */
+			for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
+				reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
+				if(((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) {  /*we got it*/
+					break;
+				}
+			}
+			if(ht_c_num == 4) break; /*used up only 4 non conherent allowed*/
+			/*update to 0xe0...*/
 			if((reg & 0xf) == 3) continue; /*SbLink so don't touch it */
 			print_linkn_in("\tbusn=", next_busn);
-                        tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24);
-                        pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
+			tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24);
+			pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
 			next_busn+=0x3f+1;
 
-#if K8_ALLOCATE_IO_RANGE == 1			
+#if K8_ALLOCATE_IO_RANGE == 1
 			/* io range allocation */
-		        tempreg = nodeid | (linkn<<4) |  ((next_io_base+0x3)<<12); //limit
-		        pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
-		        tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12);        //base :ISA and VGA ?
-		        pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg);
-		        next_io_base += 0x3+0x1;
+			tempreg = nodeid | (linkn<<4) |  ((next_io_base+0x3)<<12); //limit
+			pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
+			tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12);	//base :ISA and VGA ?
+			pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg);
+			next_io_base += 0x3+0x1;
 #endif
 
-                }
-        }
-        /*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/
+		}
+	}
+	/*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/
 
-        for(nodeid = 1; nodeid<nodes; nodeid++) {
-                int i;
-                device_t dev;
-                dev = PCI_DEV(0, 0x18+nodeid,1);
-                for(i = 0; i< 4; i++) {
-                        unsigned regpos;
-                        regpos = 0xe0 + i * 4;
-                        reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
-                        pci_write_config32(dev, regpos, reg);
-                }
+	for(nodeid = 1; nodeid<nodes; nodeid++) {
+		int i;
+		device_t dev;
+		dev = PCI_DEV(0, 0x18+nodeid,1);
+		for(i = 0; i< 4; i++) {
+			unsigned regpos;
+			regpos = 0xe0 + i * 4;
+			reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
+			pci_write_config32(dev, regpos, reg);
+		}
 
 #if K8_ALLOCATE_IO_RANGE == 1
 		/* io range allocation */
-                for(i = 0; i< 4; i++) {
-                        unsigned regpos;
-                        regpos = 0xc4 + i * 8;
-                        reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
-                        pci_write_config32(dev, regpos, reg);
-                }
-                for(i = 0; i< 4; i++) {
-                        unsigned regpos;
-                        regpos = 0xc0 + i * 8;
-                        reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
-                        pci_write_config32(dev, regpos, reg);
-                }
+		for(i = 0; i< 4; i++) {
+			unsigned regpos;
+			regpos = 0xc4 + i * 8;
+			reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
+			pci_write_config32(dev, regpos, reg);
+		}
+		for(i = 0; i< 4; i++) {
+			unsigned regpos;
+			regpos = 0xc0 + i * 8;
+			reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
+			pci_write_config32(dev, regpos, reg);
+		}
 #endif
-        }
-	
+	}
+
 	/* recount ht_c_num*/
 	uint8_t i=0;
-        for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
+	for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
 		reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
-                if(((reg & 0xf) != 0x0)) {
+		if(((reg & 0xf) != 0x0)) {
 			i++;
 		}
-        }
+	}
 
 #if RAMINIT_SYSINFO == 1
 	sysinfo->ht_c_num = i;
-        ht_setup_chains(i, sysinfo);
+	ht_setup_chains(i, sysinfo);
 	sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
 #else
 	return ht_setup_chains(i);
@@ -960,10 +963,10 @@
 	// We need to use recorded link pair info to optimize the link
 	int i;
 	int reset_needed = 0;
-	
+
 	unsigned link_pair_num = sysinfo->link_pair_num;
 
-	for(i=0; i< link_pair_num; i++) {	
+	for(i=0; i< link_pair_num; i++) {
 		struct link_pair_st *link_pair= &sysinfo->link_pair[i];
 		reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
 	}

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c	2008-10-02 19:20:22 UTC (rev 3632)
@@ -103,14 +103,14 @@
 
 static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
 {
-	 
+
 		uint32_t link_type;
 		int i;
 		uint32_t busses, config_busses;
 		unsigned free_reg, config_reg;
 		unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
-                unsigned max_bus;
-                unsigned min_bus;
+		unsigned max_bus;
+		unsigned min_bus;
 		unsigned max_devfn;
 
 		dev->link[link].cap = 0x80 + (link *0x20);
@@ -127,7 +127,7 @@
 			return max;
 		}
 		/* See if there is an available configuration space mapping
-		 * register in function 1. 
+		 * register in function 1.
 		 */
 		free_reg = 0;
 		for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
@@ -137,7 +137,7 @@
 				free_reg = config_reg;
 				continue;
 			}
-			if (((config & 3) == 3) && 
+			if (((config & 3) == 3) &&
 				(((config >> 4) & 7) == nodeid) &&
 				(((config >> 8) & 3) == link)) {
 				break;
@@ -147,7 +147,7 @@
 			config_reg = free_reg;
 		}
 		/* If we can't find an available configuration space mapping
-		 * register skip this bus 
+		 * register skip this bus
 		 */
 		if (config_reg > 0xec) {
 			return max;
@@ -158,36 +158,36 @@
 		 * so we set the subordinate bus number to 0xff for the moment.
 		 */
 #if SB_HT_CHAIN_ON_BUS0 > 0
-                // first chain will on bus 0
+		// first chain will on bus 0
 		if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
-                        min_bus = max;
-                } 
+			min_bus = max;
+		}
 	#if SB_HT_CHAIN_ON_BUS0 > 1
 		// second chain will be on 0x40, third 0x80, forth 0xc0
-                else {
-                        min_bus = ((max>>6) + 1) * 0x40; 
-                }
-                max = min_bus;
-        #else
-                //other ...
-                else  {
-                        min_bus = ++max;
-                }
-        #endif
+		else {
+			min_bus = ((max>>6) + 1) * 0x40;
+		}
+		max = min_bus;
+	#else
+		//other ...
+		else  {
+			min_bus = ++max;
+		}
+	#endif
 #else
-                min_bus = ++max;
+		min_bus = ++max;
 #endif
-                max_bus = 0xff;
+		max_bus = 0xff;
 
-                dev->link[link].secondary = min_bus;
-                dev->link[link].subordinate = max_bus;
+		dev->link[link].secondary = min_bus;
+		dev->link[link].subordinate = max_bus;
 
 		/* Read the existing primary/secondary/subordinate bus
 		 * number configuration.
 		 */
 		busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
 		config_busses = f1_read_config32(config_reg);
-		
+
 		/* Configure the bus numbers for this bridge: the configuration
 		 * transactions will not be propagates by the bridge if it is
 		 * not correctly configured
@@ -199,22 +199,22 @@
 		pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
 
 		config_busses &= 0x000fc88;
-		config_busses |= 
+		config_busses |=
 			(3 << 0) |  /* rw enable, no device compare */
-			(( nodeid & 7) << 4) | 
-			(( link & 3 ) << 8) |  
+			(( nodeid & 7) << 4) |
+			(( link & 3 ) << 8) |
 			((dev->link[link].secondary) << 16) |
 			((dev->link[link].subordinate) << 24);
 		f1_write_config32(config_reg, config_busses);
 
 		/* Now we can scan all of the subordinate busses i.e. the
-		 * chain on the hypertranport link 
+		 * chain on the hypertranport link
 		 */
 		for(i=0;i<4;i++) {
 			ht_unitid_base[i] = 0x20;
 		}
 
-		if (min_bus == 0) 
+		if (min_bus == 0)
 			max_devfn = (0x17<<3) | 7;
 		else
 			max_devfn = (0x1f<<3) | 7;
@@ -251,42 +251,42 @@
 
 static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
 {
-        unsigned nodeid;
-        unsigned link;
-        unsigned sblink = 0;
+	unsigned nodeid;
+	unsigned link;
+	unsigned sblink = 0;
 	unsigned offset_unitid = 0;
-        nodeid = amdk8_nodeid(dev);
-	
-        if(nodeid==0) {
-                sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
+	nodeid = amdk8_nodeid(dev);
+
+	if(nodeid==0) {
+		sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
 #if SB_HT_CHAIN_ON_BUS0 > 0
 	#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
-                offset_unitid = 1;
-        #endif
+		offset_unitid = 1;
+	#endif
 		max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
 #endif
-        }
+	}
 
-        for(link = 0; link < dev->links; link++) {
+	for(link = 0; link < dev->links; link++) {
 #if SB_HT_CHAIN_ON_BUS0 > 0
 		if( (nodeid == 0) && (sblink == link) ) continue; //already done
 #endif
 		offset_unitid = 0;
 		#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
-	                #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+			#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
 			if((nodeid == 0) && (sblink == link))
 			#endif
 				offset_unitid = 1;
 		#endif
 
 		max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
-        }
+	}
 
-        return max;
+	return max;
 }
 
 
-static int reg_useable(unsigned reg, 
+static int reg_useable(unsigned reg,
 	device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
 {
 	struct resource *res;
@@ -303,7 +303,7 @@
 	result = 2;
 	if (res) {
 		result = 0;
-		if (	(goal_link == (link - 1)) && 
+		if (	(goal_link == (link - 1)) &&
 			(goal_nodeid == (nodeid - 1)) &&
 			(res->flags <= 1)) {
 			result = 1;
@@ -370,7 +370,7 @@
 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
 {
 	struct resource *resource;
-	
+
 	/* Initialize the io space constraints on the current bus */
 	resource =  amdk8_find_iopair(dev, nodeid, link);
 	if (resource) {
@@ -380,7 +380,7 @@
 		resource->gran  = log2(HT_IO_HOST_ALIGN);
 		resource->limit = 0xffffUL;
 		resource->flags = IORESOURCE_IO;
-		compute_allocate_resource(&dev->link[link], resource, 
+		compute_allocate_resource(&dev->link[link], resource,
 			IORESOURCE_IO, IORESOURCE_IO);
 	}
 
@@ -393,8 +393,8 @@
 		resource->gran  = log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-		compute_allocate_resource(&dev->link[link], resource, 
-			IORESOURCE_MEM | IORESOURCE_PREFETCH, 
+		compute_allocate_resource(&dev->link[link], resource,
+			IORESOURCE_MEM | IORESOURCE_PREFETCH,
 			IORESOURCE_MEM | IORESOURCE_PREFETCH);
 	}
 
@@ -407,8 +407,8 @@
 		resource->gran  = log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM;
-		compute_allocate_resource(&dev->link[link], resource, 
-			IORESOURCE_MEM | IORESOURCE_PREFETCH, 
+		compute_allocate_resource(&dev->link[link], resource,
+			IORESOURCE_MEM | IORESOURCE_PREFETCH,
 			IORESOURCE_MEM);
 	}
 }
@@ -439,7 +439,7 @@
 	if (resource->flags & IORESOURCE_STORED) {
 		return;
 	}
-	
+
 	/* Only handle PCI memory and IO resources */
 	if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
 		return;
@@ -450,7 +450,7 @@
 	}
 	/* Get the base address */
 	rbase = resource->base;
-	
+
 	/* Get the limit (rounded up) */
 	rend  = resource_end(resource);
 
@@ -473,14 +473,14 @@
 		limit |= (nodeid & 7);
 
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-                        printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
-                                    __func__, dev_path(dev), link);		
+			printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
+				    __func__, dev_path(dev), link);
 			base |= PCI_IO_BASE_VGA_EN;
 		}
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
 			base |= PCI_IO_BASE_NO_ISA;
 		}
-		
+
 		f1_write_config32(reg + 0x4, limit);
 		f1_write_config32(reg, base);
 	}
@@ -513,7 +513,7 @@
  * but it is too diffcult to deal with the resource allocation magic.
  */
 #if CONFIG_CONSOLE_VGA_MULTI == 1
-extern device_t vga_pri;        // the primary vga device, defined in device.c
+extern device_t vga_pri;	// the primary vga device, defined in device.c
 #endif
 
 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
@@ -528,7 +528,7 @@
 	for (link = 0; link < dev->links; link++) {
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 #if CONFIG_CONSOLE_VGA_MULTI == 1
-			printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary, 
+			printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
 				dev->link[link].secondary,dev->link[link].subordinate);
 			/* We need to make sure the vga_pri is under the link */
 			if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
@@ -538,7 +538,7 @@
 			break;
 		}
 	}
-	
+
 	/* no VGA card installed */
 	if (link == dev->links)
 		return;
@@ -581,7 +581,7 @@
 	nodeid = amdk8_nodeid(dev);
 
 	amdk8_create_vga_resource(dev, nodeid);
-	
+
 	/* Set each resource we have found */
 	for(i = 0; i < dev->resources; i++) {
 		amdk8_set_resource(dev, &dev->resource[i], nodeid);
@@ -604,7 +604,7 @@
 
 static void mcf0_control_init(struct device *dev)
 {
-#if 0	
+#if 0
 	printk_debug("NB: Function 0 Misc Control.. ");
 #endif
 #if 0
@@ -673,38 +673,38 @@
 	resource->limit = 0xffffUL;
 	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-        resource->limit = 0xfcffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	/* Initialize the system wide memory resources constraints */
+	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	resource->limit = 0xfcffffffffULL;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 #else
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, 0);
-        resource->base  = 0x400;
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO;
-        compute_allocate_resource(&dev->link[0], resource,
-                IORESOURCE_IO, IORESOURCE_IO);
+	/* Initialize the system wide io space constraints */
+	resource = new_resource(dev, 0);
+	resource->base  = 0x400;
+	resource->limit = 0xffffUL;
+	resource->flags = IORESOURCE_IO;
+	compute_allocate_resource(&dev->link[0], resource,
+		IORESOURCE_IO, IORESOURCE_IO);
 
-        /* Initialize the system wide prefetchable memory resources constraints */
-        resource = new_resource(dev, 1);
-        resource->limit = 0xfcffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-        compute_allocate_resource(&dev->link[0], resource,
-                IORESOURCE_MEM | IORESOURCE_PREFETCH,
-                IORESOURCE_MEM | IORESOURCE_PREFETCH);
+	/* Initialize the system wide prefetchable memory resources constraints */
+	resource = new_resource(dev, 1);
+	resource->limit = 0xfcffffffffULL;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+	compute_allocate_resource(&dev->link[0], resource,
+		IORESOURCE_MEM | IORESOURCE_PREFETCH,
+		IORESOURCE_MEM | IORESOURCE_PREFETCH);
 
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, 2);
-        resource->limit = 0xfcffffffffULL;
-        resource->flags = IORESOURCE_MEM;
-        compute_allocate_resource(&dev->link[0], resource,
-                IORESOURCE_MEM | IORESOURCE_PREFETCH,
-                IORESOURCE_MEM);
+	/* Initialize the system wide memory resources constraints */
+	resource = new_resource(dev, 2);
+	resource->limit = 0xfcffffffffULL;
+	resource->flags = IORESOURCE_MEM;
+	compute_allocate_resource(&dev->link[0], resource,
+		IORESOURCE_MEM | IORESOURCE_PREFETCH,
+		IORESOURCE_MEM);
 #endif
 }
 
-static void ram_resource(device_t dev, unsigned long index, 
+static void ram_resource(device_t dev, unsigned long index,
 	unsigned long basek, unsigned long sizek)
 {
 	struct resource *resource;
@@ -759,83 +759,83 @@
 		struct hw_mem_hole_info mem_hole;
 		int i;
 
-                mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
+		mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
 		mem_hole.node_id = -1;
 
-                for (i = 0; i < 8; i++) {
-                        uint32_t base;
-                        uint32_t hole;
-                        base  = f1_read_config32(0x40 + (i << 3));
-                        if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
-                                continue;
-                        }
+		for (i = 0; i < 8; i++) {
+			uint32_t base;
+			uint32_t hole;
+			base  = f1_read_config32(0x40 + (i << 3));
+			if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+				continue;
+			}
 
-                        hole = pci_read_config32(__f1_dev[i], 0xf0);
-                        if(hole & 1) { // we find the hole 
-	                        mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
-        	                mem_hole.node_id = i; // record the node No with hole
-                	        break; // only one hole
+			hole = pci_read_config32(__f1_dev[i], 0xf0);
+			if(hole & 1) { // we find the hole
+				mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
+				mem_hole.node_id = i; // record the node No with hole
+				break; // only one hole
 			}
-                }
+		}
 
-                //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
-                if(mem_hole.node_id==-1) {
-                        uint32_t limitk_pri = 0;
-                        for(i=0; i<8; i++) {
-                                uint32_t base, limit;
-                                unsigned base_k, limit_k;
-                                base  = f1_read_config32(0x40 + (i << 3));
-                                if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
-                                        continue;
-                                }
+		//We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
+		if(mem_hole.node_id==-1) {
+			uint32_t limitk_pri = 0;
+			for(i=0; i<8; i++) {
+				uint32_t base, limit;
+				unsigned base_k, limit_k;
+				base  = f1_read_config32(0x40 + (i << 3));
+				if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+					continue;
+				}
 
-                                base_k = (base & 0xffff0000) >> 2;
-                                if(limitk_pri != base_k) { // we find the hole 
-	                                mem_hole.hole_startk = limitk_pri;
-        	                        mem_hole.node_id = i;
-                	                break; //only one hole
+				base_k = (base & 0xffff0000) >> 2;
+				if(limitk_pri != base_k) { // we find the hole
+					mem_hole.hole_startk = limitk_pri;
+					mem_hole.node_id = i;
+					break; //only one hole
 				}
 
-	                        limit = f1_read_config32(0x44 + (i << 3));
-                	        limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
-                                limitk_pri = limit_k;
-                        }
-                }
-		
+				limit = f1_read_config32(0x44 + (i << 3));
+				limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
+				limitk_pri = limit_k;
+			}
+		}
+
 		return mem_hole;
-		
+
 }
 static void disable_hoist_memory(unsigned long hole_startk, int i)
 {
-        int ii;
-        device_t dev;
-        uint32_t base, limit;
-        uint32_t hoist;
+	int ii;
+	device_t dev;
+	uint32_t base, limit;
+	uint32_t hoist;
 	uint32_t hole_sizek;
 
 
-        //1. find which node has hole
-        //2. change limit in that node.
-        //3. change base and limit in later node
-        //4. clear that node f0
+	//1. find which node has hole
+	//2. change limit in that node.
+	//3. change base and limit in later node
+	//4. clear that node f0
 
 	//if there is not mem hole enabled, we need to change it's base instead
 
 	hole_sizek = (4*1024*1024) - hole_startk;
 
-        for(ii=7;ii>i;ii--) {
+	for(ii=7;ii>i;ii--) {
 
-                base  = f1_read_config32(0x40 + (ii << 3));
-                if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
-                        continue;
-                }
+		base  = f1_read_config32(0x40 + (ii << 3));
+		if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+			continue;
+		}
 		limit = f1_read_config32(0x44 + (ii << 3));
-                f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
-                f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
-        }
-        limit = f1_read_config32(0x44 + (i << 3));
-        f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
-        dev = __f1_dev[i];
+		f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
+		f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
+	}
+	limit = f1_read_config32(0x44 + (i << 3));
+	f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
+	dev = __f1_dev[i];
 	hoist = pci_read_config32(dev, 0xf0);
 	if(hoist & 1) {
 		pci_write_config32(dev, 0xf0, 0);
@@ -844,35 +844,35 @@
 		base = pci_read_config32(dev, 0x40 + (i << 3));
 		f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
 	}
-		
+
 }
 
 static uint32_t hoist_memory(unsigned long hole_startk, int i)
 {
-        int ii;
-        uint32_t carry_over;
-        device_t dev;
-        uint32_t base, limit;
-        uint32_t basek;
-        uint32_t hoist;
+	int ii;
+	uint32_t carry_over;
+	device_t dev;
+	uint32_t base, limit;
+	uint32_t basek;
+	uint32_t hoist;
 
-        carry_over = (4*1024*1024) - hole_startk;
+	carry_over = (4*1024*1024) - hole_startk;
 
-        for(ii=7;ii>i;ii--) {
+	for(ii=7;ii>i;ii--) {
 
-                base  = f1_read_config32(0x40 + (ii << 3));
-                if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
-                        continue;
-                }
+		base  = f1_read_config32(0x40 + (ii << 3));
+		if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+			continue;
+		}
 		limit = f1_read_config32(0x44 + (ii << 3));
-                f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
-                f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
-        }
-        limit = f1_read_config32(0x44 + (i << 3));
-        f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
-        dev = __f1_dev[i];
-        base  = pci_read_config32(dev, 0x40 + (i << 3));
-        basek  = (base & 0xffff0000) >> 2;
+		f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
+		f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
+	}
+	limit = f1_read_config32(0x44 + (i << 3));
+	f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
+	dev = __f1_dev[i];
+	base  = pci_read_config32(dev, 0x40 + (i << 3));
+	basek  = (base & 0xffff0000) >> 2;
 	if(basek == hole_startk) {
 		//don't need set memhole here, because hole off set will be 0, overflow
 		//so need to change base reg instead, new basek will be 4*1024*1024
@@ -880,19 +880,19 @@
 		base |= (4*1024*1024)<<2;
 		f1_write_config32(0x40 + (i<<3), base);
 	}
-	else 
+	else
 	{
-	        hoist = /* hole start address */
-        	        ((hole_startk << 10) & 0xff000000) +
-                	/* hole address to memory controller address */
-	                (((basek + carry_over) >> 6) & 0x0000ff00) +
-        	        /* enable */
-	                1;
-	
-        	pci_write_config32(dev, 0xf0, hoist);
+		hoist = /* hole start address */
+			((hole_startk << 10) & 0xff000000) +
+			/* hole address to memory controller address */
+			(((basek + carry_over) >> 6) & 0x0000ff00) +
+			/* enable */
+			1;
+
+		pci_write_config32(dev, 0xf0, hoist);
 	}
 
-        return carry_over;
+	return carry_over;
 }
 #endif
 
@@ -911,68 +911,68 @@
 #endif
 
 #if 0
-        /* Place the IO devices somewhere safe */
-        io = find_resource(dev, 0);
-        io->base = DEVICE_IO_START;
+	/* Place the IO devices somewhere safe */
+	io = find_resource(dev, 0);
+	io->base = DEVICE_IO_START;
 #endif
 #if CONFIG_PCI_64BIT_PREF_MEM == 1
-        /* Now reallocate the pci resources memory with the
-         * highest addresses I can manage.
-         */
-        mem1 = find_resource(dev, 1);
-        mem2 = find_resource(dev, 2);
+	/* Now reallocate the pci resources memory with the
+	 * highest addresses I can manage.
+	 */
+	mem1 = find_resource(dev, 1);
+	mem2 = find_resource(dev, 2);
 
 #if 1
-                printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
-                        mem1->base, mem1->limit, mem1->size, mem1->align);
-                printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
-                        mem2->base, mem2->limit, mem2->size, mem2->align);
+	printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+		mem1->base, mem1->limit, mem1->size, mem1->align);
+	printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+		mem2->base, mem2->limit, mem2->size, mem2->align);
 #endif
 
-        /* See if both resources have roughly the same limits */
-        if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
-                ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
-        {
-                /* If so place the one with the most stringent alignment first
-                 */
-                if (mem2->align > mem1->align) {
-                        struct resource *tmp;
-                        tmp = mem1;
-                        mem1 = mem2;
-                        mem2 = tmp;
-                }
-                /* Now place the memory as high up as it will go */
-                mem2->base = resource_max(mem2);
-                mem1->limit = mem2->base - 1;
-                mem1->base = resource_max(mem1);
-        }
-        else {
-                /* Place the resources as high up as they will go */
-                mem2->base = resource_max(mem2);
-                mem1->base = resource_max(mem1);
-        }
+	/* See if both resources have roughly the same limits */
+	if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
+		((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
+	{
+		/* If so place the one with the most stringent alignment first
+		 */
+		if (mem2->align > mem1->align) {
+			struct resource *tmp;
+			tmp = mem1;
+			mem1 = mem2;
+			mem2 = tmp;
+		}
+		/* Now place the memory as high up as it will go */
+		mem2->base = resource_max(mem2);
+		mem1->limit = mem2->base - 1;
+		mem1->base = resource_max(mem1);
+	}
+	else {
+		/* Place the resources as high up as they will go */
+		mem2->base = resource_max(mem2);
+		mem1->base = resource_max(mem1);
+	}
 
 #if 1
-                printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
-                        mem1->base, mem1->limit, mem1->size, mem1->align);
-                printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
-                        mem2->base, mem2->limit, mem2->size, mem2->align);
+	printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+		mem1->base, mem1->limit, mem1->size, mem1->align);
+	printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+		mem2->base, mem2->limit, mem2->size, mem2->align);
 #endif
 
-        last = &dev->resource[dev->resources];
-        for(resource = &dev->resource[0]; resource < last; resource++)
-        {
+	last = &dev->resource[dev->resources];
+	for(resource = &dev->resource[0]; resource < last; resource++)
+	{
 #if 1
-                resource->flags |= IORESOURCE_ASSIGNED;
-                resource->flags &= ~IORESOURCE_STORED;
+		resource->flags |= IORESOURCE_ASSIGNED;
+		resource->flags &= ~IORESOURCE_STORED;
 #endif
-                compute_allocate_resource(&dev->link[0], resource,
-                        BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
+		compute_allocate_resource(&dev->link[0], resource,
+			BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
 
-                resource->flags |= IORESOURCE_STORED;
-                report_resource_stored(dev, resource, "");
+		resource->flags |= IORESOURCE_STORED;
+		report_resource_stored(dev, resource, "");
 
-        }
+	}
 #endif
 
 
@@ -990,50 +990,50 @@
 #endif
 
 #if HW_MEM_HOLE_SIZEK != 0
-    /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
-     * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
-     * otherwise We reset the hole to the mmio_basek
-     */
-    #if K8_REV_F_SUPPORT == 0
-        if (!is_cpu_pre_e0()) {
-    #endif
+	/* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
+	 * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
+	 * otherwise We reset the hole to the mmio_basek
+	 */
+	#if K8_REV_F_SUPPORT == 0
+		if (!is_cpu_pre_e0()) {
+	#endif
 
 		mem_hole = get_hw_mem_hole_info();
 
-                if ((mem_hole.node_id !=  -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
-                        mmio_basek = mem_hole.hole_startk;
+		if ((mem_hole.node_id !=  -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
+			mmio_basek = mem_hole.hole_startk;
 			reset_memhole = 0;
-                }
-		
+		}
+
 		//mmio_basek = 3*1024*1024; // for debug to meet boundary
 
 		if(reset_memhole) {
 			if(mem_hole.node_id!=-1) { // We need to select HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
-		               // We need to reset our Mem Hole, because We want more big HOLE than we already set
-        		       //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
-	        		disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
+			       // We need to reset our Mem Hole, because We want more big HOLE than we already set
+			       //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
+				disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
 			}
 
 		#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
 			//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
-			uint32_t basek_pri; 
-	        	for (i = 0; i < 8; i++) {
-        	        	uint32_t base;
+			uint32_t basek_pri;
+			for (i = 0; i < 8; i++) {
+				uint32_t base;
 				uint32_t basek;
-        	        	base  = f1_read_config32(0x40 + (i << 3));
-	        	        if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
-        	        	        continue;
-	                	}
+				base  = f1_read_config32(0x40 + (i << 3));
+				if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+					continue;
+				}
 
 				basek = (base & 0xffff0000) >> 2;
 				if(mmio_basek == basek) {
-					mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node 
-					break; 
+					mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node
+					break;
 				}
 				basek_pri = basek;
-			}	
-		#endif	
-        	}
+			}
+		#endif
+		}
 
 #if K8_REV_F_SUPPORT == 0
 	} // is_cpu_pre_e0
@@ -1060,12 +1060,12 @@
 			idx += 0x10;
 			basek = (8*64)+(16*16);
 			sizek = limitk - ((8*64)+(16*16));
-			
+
 		}
 
-	
-//		printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu 
-			
+
+//		printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
+
 		/* See if I need to split the region to accomodate pci memory space */
 		if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
 			if (basek <= mmio_basek) {
@@ -1077,13 +1077,13 @@
 					sizek -= pre_sizek;
 				}
 				#if HW_MEM_HOLE_SIZEK != 0
-				if(reset_memhole) 
+				if(reset_memhole)
 					#if K8_REV_F_SUPPORT == 0
-                	                if(!is_cpu_pre_e0() ) 
+					if(!is_cpu_pre_e0() )
 					#endif
-                       		                 sizek += hoist_memory(mmio_basek,i);
+		       				 sizek += hoist_memory(mmio_basek,i);
 				#endif
-				
+
 				basek = mmio_basek;
 			}
 			if ((basek + sizek) <= 4*1024*1024) {
@@ -1108,8 +1108,8 @@
 	for(reg = 0xe0; reg <= 0xec; reg += 4) {
 		f1_write_config32(reg, 0);
 	}
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);  
-	
+	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
+
 	/* Tune the hypertransport transaction for best performance.
 	 * Including enabling relaxed ordering if it is safe.
 	 */
@@ -1151,7 +1151,7 @@
 	int i,j;
 	unsigned nb_cfg_54;
 	unsigned siblings;
-	int e0_later_single_core; 
+	int e0_later_single_core;
 	int disable_siblings;
 
 	nb_cfg_54 = 0;
@@ -1179,19 +1179,19 @@
 	}
 
 	sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
-	
 
+
 	if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
 	{
 		sysconf.enabled_apic_ext_id = 1;
 		if(bsp_apicid == 0) {
 			/* bsp apic id is not changed */
 			sysconf.apicid_offset = APIC_ID_OFFSET;
-		} else 
+		} else
 		{
 			sysconf.lift_bsp_apicid = 1;
-		}	
-		
+		}
+
 	}
 
 	/* Find which cpus are present */
@@ -1233,25 +1233,25 @@
 			printk_debug("  %s siblings=%d\n", dev_path(dev), j);
 
 			if(nb_cfg_54) {
-				// For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4.... 
+				// For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
 				//  ----> you can mixed single core e0 and dual core e0 at any sequence
 				// That is the typical case
 
-		                if(j == 0 ){
+				if(j == 0 ){
 				       #if K8_REV_F_SUPPORT == 0
-                 		       	e0_later_single_core = is_e0_later_in_bsp(i);  // single core 
+		 		       	e0_later_single_core = is_e0_later_in_bsp(i);  // single core
 				       #else
 				       	e0_later_single_core = is_cpu_f0_in_bsp(i);  // We can read cpuid(1) from Func3
 				       #endif
-		                } else {
-		                       e0_later_single_core = 0;
-               			}
-				if(e0_later_single_core) { 
+				} else {
+				       e0_later_single_core = 0;
+	       			}
+				if(e0_later_single_core) {
 					printk_debug("\tFound Rev E or Rev F later single core\r\n");
 
-					j=1; 
+					j=1;
 				}
-	
+
 				if(siblings > j ) {
 				}
 				else {
@@ -1261,27 +1261,27 @@
 				siblings = j;
   			}
 		}
-		
+
 		unsigned jj;
 		if(e0_later_single_core || disable_siblings) {
 			jj = 0;
-		} else 
+		} else
 		{
 			jj = siblings;
 		}
-#if 0	
+#if 0
 		jj = 0; // if create cpu core1 path in amd_siblings by core0
 #endif
-	
-                for (j = 0; j <=jj; j++ ) {
-		
+
+		for (j = 0; j <=jj; j++ ) {
+
 			/* Build the cpu device path */
 			cpu_path.type = DEVICE_PATH_APIC;
 			cpu_path.u.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
-			
+
 			/* See if I can find the cpu */
 			cpu = find_dev_path(cpu_bus, &cpu_path);
-			
+
 			/* Enable the cpu if I have the processor */
 			if (dev && dev->enabled) {
 				if (!cpu) {
@@ -1291,7 +1291,7 @@
 					cpu->enabled = 1;
 				}
 			}
-		
+
 			/* Disable the cpu if I don't have the processor */
 			if (cpu && (!dev || !dev->enabled)) {
 				cpu->enabled = 0;
@@ -1301,14 +1301,14 @@
 			if (cpu) {
 				cpu->path.u.apic.node_id = i;
 				cpu->path.u.apic.core_id = j;
-                                if(sysconf.enabled_apic_ext_id) {
-                                	if(sysconf.lift_bsp_apicid) { 
+				if(sysconf.enabled_apic_ext_id) {
+					if(sysconf.lift_bsp_apicid) {
 						cpu->path.u.apic.apic_id += sysconf.apicid_offset;
-					} else 
+					} else
 					{
-                                               if (cpu->path.u.apic.apic_id != 0) 
-                                                       cpu->path.u.apic.apic_id += sysconf.apicid_offset;
-                                        }
+					       if (cpu->path.u.apic.apic_id != 0)
+						       cpu->path.u.apic.apic_id += sysconf.apicid_offset;
+					}
 				}
 				printk_debug("CPU: %s %s\n",
 					dev_path(cpu), cpu->enabled?"enabled":"disabled");
@@ -1324,7 +1324,7 @@
 	initialize_cpus(&dev->link[0]);
 }
 
-static void cpu_bus_noop(device_t dev) 
+static void cpu_bus_noop(device_t dev)
 {
 }
 

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c	2008-10-02 19:20:22 UTC (rev 3632)
@@ -4,7 +4,7 @@
 	2005.02 yhlu add E0 memory hole support
 */
 #if K8_REV_F_SUPPORT == 1
-        #include "raminit_f.c"
+	#include "raminit_f.c"
 #else
 
 #include <cpu/x86/mem.h>
@@ -67,7 +67,7 @@
 
 static int controller_present(const struct mem_controller *ctrl)
 {
-        return pci_read_config32(ctrl->f0, 0) == 0x11001022;
+	return pci_read_config32(ctrl->f0, 0) == 0x11001022;
 }
 
 #if RAMINIT_SYSINFO==1
@@ -198,7 +198,7 @@
 	 * [29:21] Address Mask (33-25)
 	 *	   The bits with an address mask of 1 are excluded from address comparison
 	 * [31:30] Reserved
-	 * 
+	 *
 	 */
 	PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x00000000,
 	PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x00000000,
@@ -211,7 +211,7 @@
 	/* DRAM Bank Address Mapping Register
 	 * F2:0x80
 	 * Specify the memory module size
-	 * [ 2: 0] CS1/0 
+	 * [ 2: 0] CS1/0
 	 * [ 6: 4] CS3/2
 	 * [10: 8] CS5/4
 	 * [14:12] CS7/6
@@ -222,7 +222,7 @@
 	 *	   100 = 512Mbyte (Rows = 13 & Col = 11)|(Rows = 14 & Col = 10)
 	 *	   101 = 1Gbyte	  (Rows = 14 & Col = 11)|(Rows = 13 & Col = 12)
 	 *	   110 = 2Gbyte	  (Rows = 14 & Col = 12)
-	 *	   111 = reserved 
+	 *	   111 = reserved
 	 * [ 3: 3] Reserved
 	 * [ 7: 7] Reserved
 	 * [11:11] Reserved
@@ -338,8 +338,8 @@
 	 *	   0 = Disabled
 	 *	   1 = Enabled
 	 * [ 3: 3] Disable DQS Hystersis  (FIXME handle this one carefully)
-	 *	   0 = Enable DQS input filter 
-	 *	   1 = Disable DQS input filtering 
+	 *	   0 = Enable DQS input filter
+	 *	   1 = Disable DQS input filtering
 	 * [ 7: 4] Reserved
 	 * [ 8: 8] DRAM_Init
 	 *	   0 = Initialization done or not yet started.
@@ -396,12 +396,12 @@
 	 *	   111 = Oldest entry in DCQ can be bypassed 7 times
 	 * [31:28] Reserved
 	 */
-	PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000, 
-	(4 << 25)|(0 << 24)| 
-	(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| 
-	(1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| 
-	(2 << 14)|(0 << 13)|(0 << 12)| 
-	(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| 
+	PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000,
+	(4 << 25)|(0 << 24)|
+	(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)|
+	(1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)|
+	(2 << 14)|(0 << 13)|(0 << 12)|
+	(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)|
 	(0 << 3) |(0 << 1) |(0 << 0),
 	/* DRAM Config High Register
 	 * F2:0x94
@@ -548,10 +548,10 @@
 	int max;
 
 #if 1
-        if (!controller_present(ctrl)) {
-//                print_debug("No memory controller present\r\n");
-                return;
-        }
+	if (!controller_present(ctrl)) {
+//		print_debug("No memory controller present\r\n");
+		return;
+	}
 #endif
 	print_spew("setting up CPU");
 	print_spew_hex8(ctrl->node_id);
@@ -563,8 +563,8 @@
 		unsigned long reg;
 #if 0
 	#if CONFIG_USE_PRINTK_IN_CAR
-                prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
-        #else
+		prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
+	#else
 		print_spew_hex32(register_values[i]);
 		print_spew(" <-");
 		print_spew_hex32(register_values[i+2]);
@@ -602,7 +602,7 @@
 		dcl &= ~DCL_DimmEccEn;
 	}
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
-	
+
 }
 
 static int is_dual_channel(const struct mem_controller *ctrl)
@@ -614,7 +614,7 @@
 
 static int is_opteron(const struct mem_controller *ctrl)
 {
-	/* Test to see if I am an Opteron.  
+	/* Test to see if I am an Opteron.
 	 * FIXME Socket 939 based Athlon64 have dual channel capability,
 	 * too, so we need a better test for Opterons
 	 */
@@ -684,7 +684,7 @@
 	if (value < 0) goto hw_err;
 	value &= 0xff;
 	value <<= 8;
-	
+
 	low = spd_read_byte(device, 6);	/* (low byte) */
 	if (low < 0) goto hw_err;
 	value = value | (low & 0xff);
@@ -743,20 +743,20 @@
 	if (sz.side1 != sz.side2) {
 		sz.side2 = 0;
 	}
-	
+
 	/* For each base register.
 	 * Place the dimm size in 32 MB quantities in the bits 31 - 21.
 	 * The initialize dimm size is in bits.
 	 * Set the base enable bit0.
 	 */
-	
+
 	base0 = base1 = 0;
 
 	/* Make certain side1 of the dimm is at least 32MB */
 	if (sz.side1 >= (25 +3)) {
 		base0 = (1 << ((sz.side1 - (25 + 3)) + 21)) | 1;
 	}
-	
+
 	/* Make certain side2 of the dimm is at least 32MB */
 	if (sz.side2 >= (25 + 3)) {
 		base1 = (1 << ((sz.side2 - (25 + 3)) + 21)) | 1;
@@ -810,9 +810,9 @@
 	map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
 	map &= ~(0xf << (index * 4));
 #if QRANK_DIMM_SUPPORT == 1
-        if(sz.rank == 4) {
-                map &= ~(0xf << ( (index + 2) * 4));
-        }
+	if(sz.rank == 4) {
+		map &= ~(0xf << ( (index + 2) * 4));
+	}
 #endif
 
 
@@ -821,29 +821,29 @@
 		if(is_cpu_pre_d0()) {
 			map |= (sz.side1 - (25 + 3)) << (index *4);
 #if QRANK_DIMM_SUPPORT == 1
-	                if(sz.rank == 4) {
-         	              map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
-               		}
+			if(sz.rank == 4) {
+	 			map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
+			}
 #endif
 		}
 		else {
 			map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4);
 #if QRANK_DIMM_SUPPORT == 1
-		        if(sz.rank == 4) {
-                	       map |=  cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
-               		}
+			if(sz.rank == 4) {
+				map |=  cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
+			}
 #endif
 		}
 	}
 
 	pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
-	
+
 }
 
 static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
 {
 	int i;
-	
+
 	for(i = 0; i < DIMM_SOCKETS; i++) {
 		struct dimm_size sz;
 		if (!(dimm_mask & (1 << i))) {
@@ -913,11 +913,11 @@
 	 */
 	if (tom_k >= 0x003f0000) {
 #if HW_MEM_HOLE_SIZEK != 0
-                if(hole_startk != 0) {
-                        tom_k = hole_startk;
-                } else
+		if(hole_startk != 0) {
+			tom_k = hole_startk;
+		} else
 #endif
-                tom_k = 0x3f0000;
+		tom_k = 0x3f0000;
 	}
 	msr.lo = (tom_k & 0x003fffff) << 10;
 	msr.hi = (tom_k & 0xffc00000) >> 22;
@@ -927,29 +927,29 @@
 static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
 {
 	/* 35 - 25 */
-	static const uint8_t csbase_low_shift[] = { 
+	static const uint8_t csbase_low_shift[] = {
 	/* 32MB */	(13 - 4),
 	/* 64MB */	(14 - 4),
-	/* 128MB */	(14 - 4), 
+	/* 128MB */	(14 - 4),
 	/* 256MB */	(15 - 4),
 	/* 512MB */	(15 - 4),
 	/* 1GB */	(16 - 4),
-	/* 2GB */	(16 - 4), 
+	/* 2GB */	(16 - 4),
 	};
 
-        static const uint8_t csbase_low_d0_shift[] = {
-        /* 32MB */      (13 - 4),
-        /* 64MB */      (14 - 4),
-        /* 128MB */     (14 - 4),
+	static const uint8_t csbase_low_d0_shift[] = {
+	/* 32MB */      (13 - 4),
+	/* 64MB */      (14 - 4),
+	/* 128MB */     (14 - 4),
 	/* 128MB */     (15 - 4),
-        /* 256MB */     (15 - 4),
-        /* 512MB */     (15 - 4),
-        /* 256MB */     (16 - 4),
-        /* 512MB */     (16 - 4),
-        /* 1GB */       (16 - 4),
+	/* 256MB */     (15 - 4),
+	/* 512MB */     (15 - 4),
+	/* 256MB */     (16 - 4),
+	/* 512MB */     (16 - 4),
+	/* 1GB */       (16 - 4),
 	/* 1GB */       (17 - 4),
-        /* 2GB */       (17 - 4),
-        };
+	/* 2GB */       (17 - 4),
+	};
 
 	/* cs_base_high is not changed */
 
@@ -970,9 +970,9 @@
 		unsigned size;
 		unsigned cs_mode;
 		uint32_t value;
-		
+
 		value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
-		
+
 		/* Is it enabled? */
 		if (!(value & 1)) {
 			continue;
@@ -988,15 +988,15 @@
 		}
 
 		value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
-                cs_mode =( value >> ((index>>1)*4)) & 0xf;
-                if(cs_mode == 0 ) continue;
-                if(common_cs_mode == 0) {
-                	common_cs_mode = cs_mode;
-                }
-                /* The size differed fail */
-                if(common_cs_mode != cs_mode) {
-                        return 0;
-                }
+		cs_mode =( value >> ((index>>1)*4)) & 0xf;
+		if(cs_mode == 0 ) continue;
+		if(common_cs_mode == 0) {
+			common_cs_mode = cs_mode;
+		}
+		/* The size differed fail */
+		if(common_cs_mode != cs_mode) {
+			return 0;
+		}
 	}
 
 	/* Chip selects can only be interleaved when there is
@@ -1011,26 +1011,26 @@
 	if(is_cpu_pre_d0()){
 		csbase_inc = 1 << csbase_low_shift[common_cs_mode];
 		if(is_dual_channel(ctrl)) {
-                /* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
-	                if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
-//     		                print_debug("8 4GB chip selects cannot be interleaved\r\n");
-	                        return 0;
-                	}  
+		/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
+			if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
+//     				print_debug("8 4GB chip selects cannot be interleaved\r\n");
+				return 0;
+			}
 			csbase_inc <<=1;
 		}
 	}
 	else {
 		csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
 		if(is_dual_channel(ctrl)) {
-	                if( (bits==3) && (common_cs_mode > 8)) {
-//        	                print_debug("8 cs_mode>8 chip selects cannot be interleaved\r\n");
-        	                return 0;
+			if( (bits==3) && (common_cs_mode > 8)) {
+//				print_debug("8 cs_mode>8 chip selects cannot be interleaved\r\n");
+				return 0;
 			}
 			csbase_inc <<=1;
-                }   
+		}
 	}
 
-	/* Compute the initial values for csbase and csbask. 
+	/* Compute the initial values for csbase and csbask.
 	 * In csbase just set the enable bit and the base to zero.
 	 * In csmask set the mask bits for the size and page level interleave.
 	 */
@@ -1049,7 +1049,7 @@
 		pci_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
 		csbase += csbase_inc;
 	}
-	
+
 	print_spew("Interleaved\r\n");
 
 	/* Return the memory size in K */
@@ -1077,12 +1077,12 @@
 			if (!(value & 1)) {
 				continue;
 			}
-			
+
 			/* Is it greater? */
 			if (value <= csbase) {
 				continue;
 			}
-			
+
 			/* Has it already been selected */
 			if (tom & (1 << (index + 24))) {
 				continue;
@@ -1116,7 +1116,7 @@
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
 		/* Write the new mask register */
 		pci_write_config32(ctrl->f2, DRAM_CSMASK + (canidate << 2), csmask);
-		
+
 	}
 	/* Return the memory size in K */
 	return (tom & ~0xff000000) << 15;
@@ -1164,8 +1164,8 @@
 
 static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask)
 {
-	print_debug("disabling dimm"); 
-	print_debug_hex8(index); 
+	print_debug("disabling dimm");
+	print_debug_hex8(index);
 	print_debug("\r\n");
 	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
 	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
@@ -1194,7 +1194,7 @@
 		/* Registered dimm ? */
 		if (value & (1 << 1)) {
 			registered = 1;
-		} 
+		}
 		/* Otherwise it must be an unbuffered dimm */
 		else {
 			unbuffered = 1;
@@ -1209,9 +1209,9 @@
 	if (unbuffered) {
 		if ((has_dualch) && (!is_cpu_pre_d0())) {
 			dcl |= DCL_UnBufDimm; /* set DCL_DualDIMMen too? */
-			
+
 			/* set DCL_En2T if you have non-equal DDR mem types! */
-			
+
 			if ((cpuid_eax(1) & 0x30) == 0x30) {
 				/* CS[7:4] is copy of CS[3:0], should be set for 939 socket */
 				dcl |= DCL_UpperCSMap;
@@ -1286,7 +1286,7 @@
 	};
 	/* If the dimms are not in pairs do not do dual channels */
 	if ((dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
-		((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { 
+		((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
 		goto single_channel;
 	}
 	/* If the cpu is not capable of doing dual channels don't do dual channels */
@@ -1521,7 +1521,7 @@
 	/* Make a second pass through the dimms and disable
 	 * any that cannot support the selected memclk and cas latency.
 	 */
-	
+
 	for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
 		int latencies;
 		int latency;
@@ -1551,12 +1551,12 @@
 		if ((latency != min_latency) || (index >= 3)) {
 			goto dimm_err;
 		}
-		
+
 		/* Read the min_cycle_time for this latency */
 		value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
 		if (value < 0) goto hw_error;
-		
-		/* All is good if the selected clock speed 
+
+		/* All is good if the selected clock speed
 		 * is what I need or slower.
 		 */
 		if (value <= min_cycle_time) {
@@ -1571,12 +1571,12 @@
 #if QRANK_DIMM_SUPPORT
 	if(dimm_mask == (3|(3<<DIMM_SOCKETS)) ) {
 		int ranks = 4;
-	        for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
+		for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
 			int val;
-                	if (!(dimm_mask & (1 << i))) {
-                        	continue;
-	                }
-        	        val = spd_read_byte(ctrl->channel0[i], 5);
+			if (!(dimm_mask & (1 << i))) {
+				continue;
+			}
+			val = spd_read_byte(ctrl->channel0[i], 5);
 			if(val!=ranks) {
 				ranks = val;
 				break;
@@ -1587,7 +1587,7 @@
 				min_cycle_time = 0x60;
 			}
 		}
-		
+
 	}
 #endif
 #endif
@@ -1615,7 +1615,7 @@
 	value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
 	value |= latencies[min_latency - 2] << DTL_TCL_SHIFT;
 	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
-	
+
 	result.dimm_mask = dimm_mask;
 	return result;
  hw_error:
@@ -1844,9 +1844,9 @@
 	}
 
 #if QRANK_DIMM_SUPPORT == 1
-	rank = spd_read_byte(ctrl->channel0[i], 5);       /* number of physical banks */
+	rank = spd_read_byte(ctrl->channel0[i], 5);	/* number of physical banks */
 	if (rank < 0) {
-		return -1;	
+		return -1;
 	}
 #endif
 
@@ -1943,7 +1943,7 @@
 	if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) {
 		die("Unknown Trwt\r\n");
 	}
-	
+
 	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
 	dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT);
 	dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT);
@@ -2022,7 +2022,7 @@
 		if (dimms == 4) {
 			/* 9ns */
 			async_lat = 9;
-		} 
+		}
 		else {
 			/* 8ns */
 			async_lat = 8;
@@ -2059,7 +2059,7 @@
 static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask)
 {
 	int i;
-	
+
 	init_Tref(ctrl, param);
 	for(i = 0; i < DIMM_SOCKETS; i++) {
 		int rc;
@@ -2076,8 +2076,8 @@
 
 		/* DRAM Timing High Register */
 		if ((rc = update_dimm_Tref(ctrl, param, i)) <= 0) goto dimm_err;
-	
 
+
 		/* DRAM Config Low */
 		if ((rc = update_dimm_x4 (ctrl, param, i)) <= 0) goto dimm_err;
 		if ((rc = update_dimm_ecc(ctrl, param, i)) <= 0) goto dimm_err;
@@ -2104,9 +2104,9 @@
 }
 
 #if RAMINIT_SYSINFO==1
-static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) 
+static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
 #else
-static void sdram_set_spd_registers(const struct mem_controller *ctrl) 
+static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 #endif
 {
 	struct spd_set_memclk_result result;
@@ -2125,19 +2125,19 @@
 		print_debug("No memory for this cpu\r\n");
 		return;
 	}
-	dimm_mask = spd_enable_2channels(ctrl, dimm_mask);        
-	if (dimm_mask < 0) 
+	dimm_mask = spd_enable_2channels(ctrl, dimm_mask);
+	if (dimm_mask < 0)
 		goto hw_spd_err;
-	dimm_mask = spd_set_ram_size(ctrl , dimm_mask);           
-	if (dimm_mask < 0) 
+	dimm_mask = spd_set_ram_size(ctrl , dimm_mask);
+	if (dimm_mask < 0)
 		goto hw_spd_err;
-	dimm_mask = spd_handle_unbuffered_dimms(ctrl, dimm_mask); 
-	if (dimm_mask < 0) 
+	dimm_mask = spd_handle_unbuffered_dimms(ctrl, dimm_mask);
+	if (dimm_mask < 0)
 		goto hw_spd_err;
 	result = spd_set_memclk(ctrl, dimm_mask);
 	param     = result.param;
 	dimm_mask = result.dimm_mask;
-	if (dimm_mask < 0) 
+	if (dimm_mask < 0)
 		goto hw_spd_err;
 	dimm_mask = spd_set_dram_timing(ctrl, param , dimm_mask);
 	if (dimm_mask < 0)
@@ -2154,108 +2154,108 @@
 #if HW_MEM_HOLE_SIZEK != 0
 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i)
 {
-        int ii;
-        uint32_t carry_over;
-        device_t dev;
-        uint32_t base, limit;
-        uint32_t basek;
-        uint32_t hoist;
-        int j;
+	int ii;
+	uint32_t carry_over;
+	device_t dev;
+	uint32_t base, limit;
+	uint32_t basek;
+	uint32_t hoist;
+	int j;
 
-        carry_over = (4*1024*1024) - hole_startk;
+	carry_over = (4*1024*1024) - hole_startk;
 
-        for(ii=controllers - 1;ii>i;ii--) {
-                base  = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
-                if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
-                        continue;
-                }
+	for(ii=controllers - 1;ii>i;ii--) {
+		base  = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
+		if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+			continue;
+		}
 		limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
-                for(j = 0; j < controllers; j++) {
-                        pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
-                        pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
-                }
-        }
-        limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
-        for(j = 0; j < controllers; j++) {
-                pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
-        }
-        dev = ctrl[i].f1;
-        base  = pci_read_config32(dev, 0x40 + (i << 3));
-        basek  = (base & 0xffff0000) >> 2;
-        if(basek == hole_startk) {
-                //don't need set memhole here, because hole off set will be 0, overflow
-                //so need to change base reg instead, new basek will be 4*1024*1024
-                base &= 0x0000ffff;
-                base |= (4*1024*1024)<<2;
-                for(j = 0; j < controllers; j++) {
-                        pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
-                }
-        }
+		for(j = 0; j < controllers; j++) {
+			pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
+			pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
+		}
+	}
+	limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
+	for(j = 0; j < controllers; j++) {
+		pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
+	}
+	dev = ctrl[i].f1;
+	base  = pci_read_config32(dev, 0x40 + (i << 3));
+	basek  = (base & 0xffff0000) >> 2;
+	if(basek == hole_startk) {
+		//don't need set memhole here, because hole off set will be 0, overflow
+		//so need to change base reg instead, new basek will be 4*1024*1024
+		base &= 0x0000ffff;
+		base |= (4*1024*1024)<<2;
+		for(j = 0; j < controllers; j++) {
+			pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
+		}
+	}
 	else {
-        	hoist = /* hole start address */
-                	((hole_startk << 10) & 0xff000000) +
-	                /* hole address to memory controller address */
-        	        (((basek + carry_over) >> 6) & 0x0000ff00) +
-                	/* enable */
-	                1;
-	        pci_write_config32(dev, 0xf0, hoist);
+		hoist = /* hole start address */
+			((hole_startk << 10) & 0xff000000) +
+			/* hole address to memory controller address */
+			(((basek + carry_over) >> 6) & 0x0000ff00) +
+			/* enable */
+			1;
+		pci_write_config32(dev, 0xf0, hoist);
 	}
 
-        return carry_over;
+	return carry_over;
 }
 
 static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
 {
 
-        uint32_t hole_startk;
-        int i;
+	uint32_t hole_startk;
+	int i;
 
-        hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
+	hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
 
-#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 
+#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
 	/* We need to double check if hole_startk is valid.
-	 * If it is equal to the dram base address in K (base_k), 
+	 * If it is equal to the dram base address in K (base_k),
 	 * we need to decrease it.
 	 */
-        uint32_t basek_pri;
-        for(i=0; i<controllers; i++) {
-                        uint32_t base;
-                        unsigned base_k;
-                        base  = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
-                        if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
-                                continue;
-                        }
-                        base_k = (base & 0xffff0000) >> 2;
-                        if(base_k == hole_startk) {
+	uint32_t basek_pri;
+	for(i=0; i<controllers; i++) {
+			uint32_t base;
+			unsigned base_k;
+			base  = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
+			if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+				continue;
+			}
+			base_k = (base & 0xffff0000) >> 2;
+			if(base_k == hole_startk) {
 				/* decrease memory hole startk to make sure it is
-				 * in the middle of the previous node 
+				 * in the middle of the previous node
 				 */
-                                hole_startk -= (base_k - basek_pri)>>1; 
-                                break; /* only one hole */
-                        }
-                        basek_pri = base_k;
-        }
+				hole_startk -= (base_k - basek_pri)>>1;
+				break; /* only one hole */
+			}
+			basek_pri = base_k;
+	}
 
 #endif
-        /* Find node number that needs the memory hole configured */
-        for(i=0; i<controllers; i++) {
-                        uint32_t base, limit;
-                        unsigned base_k, limit_k;
-                        base  = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
-                        if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
-                                continue;
-                        }
-                        limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
-                        base_k = (base & 0xffff0000) >> 2;
-                        limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
+	/* Find node number that needs the memory hole configured */
+	for(i=0; i<controllers; i++) {
+			uint32_t base, limit;
+			unsigned base_k, limit_k;
+			base  = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
+			if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+				continue;
+			}
+			limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
+			base_k = (base & 0xffff0000) >> 2;
+			limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
 			if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
-                                unsigned end_k;
-                                hoist_memory(controllers, ctrl, hole_startk, i);
-                                end_k = memory_end_k(ctrl, controllers);
-                                set_top_mem(end_k, hole_startk);
-                                break; /* only one hole */
-                        }
-        }
+				unsigned end_k;
+				hoist_memory(controllers, ctrl, hole_startk, i);
+				end_k = memory_end_k(ctrl, controllers);
+				set_top_mem(end_k, hole_startk);
+				break; /* only one hole */
+			}
+	}
 
 }
 
@@ -2369,10 +2369,10 @@
 	}
 
 #if HW_MEM_HOLE_SIZEK != 0
-         // init hw mem hole here
-        /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
+	 // init hw mem hole here
+	/* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
 	if(!is_cpu_pre_e0())
-	        set_hw_mem_hole(controllers, ctrl);
+		set_hw_mem_hole(controllers, ctrl);
 #endif
 
 	//FIXME add enable node interleaving here -- yhlu
@@ -2396,7 +2396,7 @@
 
 	/* The first 1M is now setup, use it */
 	cache_lbmem(MTRR_TYPE_WRBACK);
-	
+
 	print_debug(" done\r\n");
 #endif
 }
@@ -2408,24 +2408,24 @@
 
 static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr)
 {
-        int i;
-        int j;
-        struct mem_controller *ctrl;
-        for(i=0;i<controllers; i++) {
-                ctrl = &ctrl_a[i];
-                ctrl->node_id = i;
-                ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
-                ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
-                ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
-                ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
+	int i;
+	int j;
+	struct mem_controller *ctrl;
+	for(i=0;i<controllers; i++) {
+		ctrl = &ctrl_a[i];
+		ctrl->node_id = i;
+		ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
+		ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
+		ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
+		ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
 
-                if(spd_addr == (void *)0) continue;
+		if(spd_addr == (void *)0) continue;
 
-                for(j=0;j<DIMM_SOCKETS;j++) {
-                        ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
-                        ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];
-                }
-        }
+		for(j=0;j<DIMM_SOCKETS;j++) {
+			ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
+			ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];
+		}
+	}
 }
 #endif
 

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c	2008-10-02 19:20:22 UTC (rev 3632)
@@ -21,14 +21,14 @@
 //0: mean no debug info
 #define DQS_TRAIN_DEBUG 0
 
-static inline void print_debug_dqs(const char *str, unsigned val, unsigned level) 
+static inline void print_debug_dqs(const char *str, unsigned val, unsigned level)
 {
 #if DQS_TRAIN_DEBUG > 0
 	if(DQS_TRAIN_DEBUG > level) {
 		#if CONFIG_USE_PRINTK_IN_CAR
 		printk_debug("%s%x\r\n", str, val);
 		#else
-	        print_debug(str); print_debug_hex32(val); print_debug("\r\n");
+		print_debug(str); print_debug_hex32(val); print_debug("\r\n");
 		#endif
 	}
 #endif
@@ -37,36 +37,36 @@
 static inline void print_debug_dqs_pair(const char *str, unsigned val, const char *str2, unsigned val2, unsigned level)
 {
 #if DQS_TRAIN_DEBUG > 0
-        if(DQS_TRAIN_DEBUG > level) {
+	if(DQS_TRAIN_DEBUG > level) {
 		#if CONFIG_USE_PRINTK_IN_CAR
-                printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2);
-                #else
-                print_debug(str); print_debug_hex32(val); print_debug(str2); print_debug_hex32(val2); print_debug("\r\n");
-                #endif
-        }
+		printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2);
+		#else
+		print_debug(str); print_debug_hex32(val); print_debug(str2); print_debug_hex32(val2); print_debug("\r\n");
+		#endif
+	}
 #endif
 }
 
 static inline void print_debug_dqs_tsc(const char *str, unsigned i, unsigned val, unsigned val2, unsigned level)
 {
 #if DQS_TRAIN_DEBUG > 0
-        if(DQS_TRAIN_DEBUG > level) {
+	if(DQS_TRAIN_DEBUG > level) {
 		#if CONFIG_USE_PRINTK_IN_CAR
-                printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2);
-                #else
+		printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+		#else
 		print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n");
-                #endif
-        }
+		#endif
+	}
 #endif
 }
 
 static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2)
 {
 	#if CONFIG_USE_PRINTK_IN_CAR
-        printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2);
-        #else
-        print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n");
-        #endif
+	printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+	#else
+	print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n");
+	#endif
 
 }
 
@@ -74,13 +74,13 @@
 {
 
 	int i;
-        sysinfo->mem_base[nodeid] = pci_read_config32(ctrl->f1, 0x40 + (nodeid<<3));
+	sysinfo->mem_base[nodeid] = pci_read_config32(ctrl->f1, 0x40 + (nodeid<<3));
 
 	for(i=0;i<8; i++) {
 		sysinfo->cs_base[nodeid*8+i] = pci_read_config32(ctrl->f2, 0x40 + (i<<2));
 	}
 
-	sysinfo->hole_reg[nodeid] = pci_read_config32(ctrl->f1, 0xf0);	
+	sysinfo->hole_reg[nodeid] = pci_read_config32(ctrl->f1, 0xf0);
 
 }
 static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl,  unsigned cs_idx, struct sys_info *sysinfo)
@@ -89,7 +89,7 @@
 	uint32_t mem_base;
 	unsigned nodeid = ctrl->node_id;
 
-#if HW_MEM_HOLE_SIZEK != 0	
+#if HW_MEM_HOLE_SIZEK != 0
 	uint32_t hole_reg;
 #endif
 
@@ -107,17 +107,17 @@
 	if(hole_reg & 1) {
 		unsigned hole_startk;
 		hole_startk = (hole_reg & (0xff<<24)) >> 10;
-		if( (dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) { 
+		if( (dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) {
 			dword += ((4*1024*1024 - hole_startk)<<2);
 		}
-	}  
+	}
 #endif
 
 	//add 1MB offset to avoid compat area
 	dword += (1<<(20-8));
-		
-	//So final result is upper 32 bit addr 
-	
+
+	//So final result is upper 32 bit addr
+
 	return dword;
 
 }
@@ -130,14 +130,14 @@
 
 static inline unsigned long read_cr4(void)
 {
-        unsigned long cr4;
-        asm volatile ("movl %%cr4, %0" : "=r" (cr4));
-        return cr4;
+	unsigned long cr4;
+	asm volatile ("movl %%cr4, %0" : "=r" (cr4));
+	return cr4;
 }
 
 static inline void write_cr4(unsigned long cr4)
 {
-        asm volatile ("movl %0, %%cr4" : : "r" (cr4));
+	asm volatile ("movl %0, %%cr4" : : "r" (cr4));
 }
 
 
@@ -151,55 +151,55 @@
 
 static inline void disable_sse2()
 {
-        unsigned long cr4;
-        cr4 = read_cr4();
-        cr4 &= ~(1<<9);
-        write_cr4(cr4);
+	unsigned long cr4;
+	cr4 = read_cr4();
+	cr4 &= ~(1<<9);
+	write_cr4(cr4);
 }
 
 
 static void set_wrap32dis(void) {
 	msr_t msr;
-	
+
 	msr = rdmsr(0xc0010015);
 	msr.lo |= (1<<17);
-	
+
 	wrmsr(0xc0010015, msr);
 
 }
 
 static void clear_wrap32dis(void) {
-        msr_t msr;
+	msr_t msr;
 
-        msr = rdmsr(0xc0010015);
-        msr.lo &= ~(1<<17);
+	msr = rdmsr(0xc0010015);
+	msr.lo &= ~(1<<17);
 
-        wrmsr(0xc0010015, msr);
+	wrmsr(0xc0010015, msr);
 
 }
 
 static void set_FSBASE(uint32_t addr_hi)
 {
-        msr_t msr;
+	msr_t msr;
 
-        //set fs and use fs prefix to access the mem
-        msr.hi = addr_hi;
-        msr.lo = 0;
-        wrmsr(0xc0000100, msr); //FS_BASE
+	//set fs and use fs prefix to access the mem
+	msr.hi = addr_hi;
+	msr.lo = 0;
+	wrmsr(0xc0000100, msr); //FS_BASE
 
 }
 
 static unsigned ChipSelPresent(const struct mem_controller *ctrl, unsigned cs_idx, struct sys_info *sysinfo)
 {
-        unsigned enabled;
+	unsigned enabled;
 	unsigned nodeid = ctrl->node_id;
-	
 
-        enabled = sysinfo->cs_base[nodeid * 8 + cs_idx];
-        enabled &= 1;
 
-        return enabled;
+	enabled = sysinfo->cs_base[nodeid * 8 + cs_idx];
+	enabled &= 1;
 
+	return enabled;
+
 }
 
 static unsigned RcvrRankEnabled(const struct mem_controller *ctrl, int channel, int cs_idx, unsigned is_Width128, struct sys_info *sysinfo)
@@ -209,21 +209,21 @@
 
 static void WriteLNTestPattern(unsigned addr_lo, uint8_t *buf_a, unsigned line_num)
 {
-        __asm__ volatile (
-                "1:\n\t"
+	__asm__ volatile (
+		"1:\n\t"
 		"movdqa (%3), %%xmm0\n\t"
 		"movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */
-                "addl %1, %0\n\t"
-                "addl %1, %3\n\t"
-                "loop 1b\n\t"
+		"addl %1, %0\n\t"
+		"addl %1, %3\n\t"
+		"loop 1b\n\t"
 
-                :: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a)
-        );
+		:: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a)
+	);
 
 
 }
 
-static void Write1LTestPattern(unsigned addr, unsigned p, uint8_t *buf_a, uint8_t *buf_b) 
+static void Write1LTestPattern(unsigned addr, unsigned p, uint8_t *buf_a, uint8_t *buf_b)
 {
 	uint8_t *buf;
 	if(p==1) { buf = buf_b; }
@@ -234,18 +234,18 @@
 	WriteLNTestPattern(addr<<8, buf, 1);
 }
 
-static void Read1LTestPattern(unsigned addr) 
+static void Read1LTestPattern(unsigned addr)
 {
-        unsigned value;
+	unsigned value;
 
 	set_FSBASE(addr>>24);
-	
+
 	/* 1st move causes read fill (to exclusive or shared)*/
-        __asm__ volatile (
-                "movl %%fs:(%1), %0\n\t"
-                :"=b"(value): "a" (addr<<8)
-        );
-	
+	__asm__ volatile (
+		"movl %%fs:(%1), %0\n\t"
+		:"=b"(value): "a" (addr<<8)
+	);
+
 }
 
 #define DQS_PASS 0
@@ -283,42 +283,42 @@
 		test_buf = (uint32_t *)TestPattern2;
 	}
 
-	set_FSBASE(addr>>24);	
-	
+	set_FSBASE(addr>>24);
+
 	addr_lo = addr<<8;
-	
+
 	if(is_Width128 && (channel == 1)) {
 		addr_lo += 8; //second channel
 		test_buf += 2;
 	}
-	
-        __asm__ volatile (
-                "movl %%fs:(%1), %0\n\t"
-                :"=b"(value): "a" (addr_lo)
-        );
 
+	__asm__ volatile (
+		"movl %%fs:(%1), %0\n\t"
+		:"=b"(value): "a" (addr_lo)
+	);
+
 	value_test = *test_buf;
 
-	
-        print_debug_dqs_pair("\t\t\t\t\t\tQW0.lo : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4); 
-        print_debug_dqs_pair("\t\t\t\t\t\tQW0.lo : addr_lo = ", addr_lo, " value = ", value, 4); 
 
+	print_debug_dqs_pair("\t\t\t\t\t\tQW0.lo : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4);
+	print_debug_dqs_pair("\t\t\t\t\t\tQW0.lo : addr_lo = ", addr_lo, " value = ", value, 4);
+
 	if(value == value_test) {
 		addr_lo += 4;
 		test_buf++;
-	        __asm__ volatile (
-	                "movl %%fs:(%1), %0\n\t"
-        	        :"=b"(value): "a" (addr_lo)
-        	);
-	        value_test = *test_buf;
-	        print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4);
-        	print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : addr_lo = ", addr_lo, " value = ", value, 4);
+		__asm__ volatile (
+			"movl %%fs:(%1), %0\n\t"
+			:"=b"(value): "a" (addr_lo)
+		);
+		value_test = *test_buf;
+		print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4);
+		print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : addr_lo = ", addr_lo, " value = ", value, 4);
 
 		if(value == value_test){
 			result =  DQS_PASS;
 		}
 	}
-	
+
 	if(Pass == DQS_SECOND_PASS) { // second pass need to be inverted
 		if(result==DQS_PASS) {
 			result = DQS_FAIL;
@@ -332,25 +332,25 @@
 
 }
 
-static void SetMaxAL_RcvrDly(const struct mem_controller *ctrl, unsigned dly) 
+static void SetMaxAL_RcvrDly(const struct mem_controller *ctrl, unsigned dly)
 {
-        uint32_t reg;
+	uint32_t reg;
 
 	dly += (20-1); // round it
 	dly /= 20; // convert from unit 50ps to 1ns
-	
+
 	dly += 6;
 
 
-        reg = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
-        reg &= ~(DCH_MaxAsyncLat_MASK <<DCH_MaxAsyncLat_SHIFT);
-        reg |= ((dly - DCH_MaxAsyncLat_BASE) << DCH_MaxAsyncLat_SHIFT);
-        pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, reg);
-	
+	reg = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+	reg &= ~(DCH_MaxAsyncLat_MASK <<DCH_MaxAsyncLat_SHIFT);
+	reg |= ((dly - DCH_MaxAsyncLat_BASE) << DCH_MaxAsyncLat_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, reg);
+
 }
 
 /*
-	Set the Target range to WT IO (using an IORR overlapping the already existing 
+	Set the Target range to WT IO (using an IORR overlapping the already existing
 	WB dram type). Use IORR0
 */
 static void SetTargetWTIO(unsigned addr)
@@ -359,19 +359,19 @@
 	msr.hi = addr>>24;
 	msr.lo = addr<<8;
 	wrmsr(0xc0010016, msr); //IORR0 BASE
-	
+
 	msr.hi = 0xff;
 	msr.lo = 0xfc000800;  // 64MB Mask
-	wrmsr(0xc0010017, msr); // IORR0 Mask 
+	wrmsr(0xc0010017, msr); // IORR0 Mask
 }
 
 static void ResetTargetWTIO(void)
 {
-        msr_t msr;
+	msr_t msr;
 
-        msr.hi = 0;
-        msr.lo = 0;  
-        wrmsr(0xc0010017, msr); // IORR0 Mask
+	msr.hi = 0;
+	msr.lo = 0;
+	wrmsr(0xc0010017, msr); // IORR0 Mask
 }
 
 static void proc_CLFLUSH(unsigned addr)
@@ -379,13 +379,13 @@
 
 	set_FSBASE(addr>>24);
 
-        /* 1st move causes read fill (to exclusive or shared)*/
-        __asm__ volatile (
+	/* 1st move causes read fill (to exclusive or shared)*/
+	__asm__ volatile (
 			/* clflush fs:[eax] */
 		"clflush %%fs:(%0)\n\t"
-                ::"a" (addr<<8)
-        );
-	
+		::"a" (addr<<8)
+	);
+
 }
 static void proc_IOCLFLUSH(unsigned addr)
 {
@@ -411,39 +411,39 @@
 
 static uint16_t get_exact_T1000(unsigned i)
 {
-        //			           200   266,   333,  400
+	//				   200   266,   333,  400
 	static const uint16_t T1000_a[]= { 5000, 3759, 3003, 2500 };
 
-        static const uint16_t TT_a[] = {
-                 /*200   266   333   400 */
-         /*4 */   6250, 6250, 6250, 6250,
-         /*5 */   5000, 5000, 5000, 2500,
-         /*6 */   5000, 4166, 4166, 2500,
-         /*7 */   5000, 4285, 3571, 2500,
+	static const uint16_t TT_a[] = {
+		 /*200   266   333   400 */
+	 /*4 */   6250, 6250, 6250, 6250,
+	 /*5 */   5000, 5000, 5000, 2500,
+	 /*6 */   5000, 4166, 4166, 2500,
+	 /*7 */   5000, 4285, 3571, 2500,
 
-         /*8 */   5000, 3750, 3125, 2500,
-         /*9 */   5000, 3888, 3333, 2500,
-         /*10*/   5000, 4000, 3000, 2500,
-         /*11*/   5000, 4090, 3181, 2500,
+	 /*8 */   5000, 3750, 3125, 2500,
+	 /*9 */   5000, 3888, 3333, 2500,
+	 /*10*/   5000, 4000, 3000, 2500,
+	 /*11*/   5000, 4090, 3181, 2500,
 
-         /*12*/   5000, 3750, 3333, 2500,
-         /*13*/   5000, 3846, 3076, 2500,
-         /*14*/   5000, 3928, 3214, 2500,
-         /*15*/   5000, 4000, 3000, 2500,
-        };
+	 /*12*/   5000, 3750, 3333, 2500,
+	 /*13*/   5000, 3846, 3076, 2500,
+	 /*14*/   5000, 3928, 3214, 2500,
+	 /*15*/   5000, 4000, 3000, 2500,
+	};
 
-        unsigned fid_cur;
-        int index;
+	unsigned fid_cur;
+	int index;
 
-        msr_t msr;
-        msr = rdmsr(0xc0010042);
-        fid_cur = msr.lo & 0x3f;
+	msr_t msr;
+	msr = rdmsr(0xc0010042);
+	fid_cur = msr.lo & 0x3f;
 
-        index = fid_cur>>1;
+	index = fid_cur>>1;
 
-        if(index>12) return T1000_a[i];
+	if(index>12) return T1000_a[i];
 
-        return TT_a[index * 4+i];
+	return TT_a[index * 4+i];
 
 }
 
@@ -451,24 +451,24 @@
 {
 	int i;
 	uint32_t dword;
-	
+
 	dword = 0x00000000;
 	for(i=1; i<=3; i++) {
-        	/* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x01-0x03, 0x21-0x23) to 0x00 for all bytes */
-	        pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword);
+		/* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x01-0x03, 0x21-0x23) to 0x00 for all bytes */
+		pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword);
 		pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword);
 	}
 
-        dword = 0x2f2f2f2f;
-        for(i=5; i<=7; i++) {
-                /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x05-0x07, 0x25-0x27) to 0x2f for all bytes */
-                pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword);
-                pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword);
-        }
+	dword = 0x2f2f2f2f;
+	for(i=5; i<=7; i++) {
+		/* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x05-0x07, 0x25-0x27) to 0x2f for all bytes */
+		pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword);
+		pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword);
+	}
 
 
 }
-#ifndef K8_REV_F_SUPPORT_F0_F1_WORKAROUND 
+#ifndef K8_REV_F_SUPPORT_F0_F1_WORKAROUND
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 1
 #endif
 
@@ -481,21 +481,21 @@
 			0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa,
 			0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa,
 		};
-        static const uint32_t TestPattern1[] = {
-                        0x55555555, 0x55555555, 0x55555555, 0x55555555,
+	static const uint32_t TestPattern1[] = {
 			0x55555555, 0x55555555, 0x55555555, 0x55555555,
 			0x55555555, 0x55555555, 0x55555555, 0x55555555,
 			0x55555555, 0x55555555, 0x55555555, 0x55555555,
+			0x55555555, 0x55555555, 0x55555555, 0x55555555,
 		};
-	static const uint32_t TestPattern2[] = { 
+	static const uint32_t TestPattern2[] = {
 			0x12345678, 0x87654321, 0x23456789, 0x98765432,
 			0x59385824, 0x30496724, 0x24490795, 0x99938733,
-                        0x40385642, 0x38465245, 0x29432163, 0x05067894,
-                        0x12349045, 0x98723467, 0x12387634, 0x34587623,
+			0x40385642, 0x38465245, 0x29432163, 0x05067894,
+			0x12349045, 0x98723467, 0x12387634, 0x34587623,
 		};
 
-	uint8_t pattern_buf_x[64 * 4 + 16]; // We need to two cache line So have more 16 bytes to keep 16 byte alignment */ 
-	uint8_t *buf_a, *buf_b; 
+	uint8_t pattern_buf_x[64 * 4 + 16]; // We need to two cache line So have more 16 bytes to keep 16 byte alignment */
+	uint8_t *buf_a, *buf_b;
 	uint32_t ecc_bit;
 	uint32_t dword;
 	uint8_t *dqs_rcvr_dly_a = &sysinfo->dqs_rcvr_dly_a[ctrl->node_id * 2* 8] ; //8 node, channel 2, receiver 8
@@ -543,14 +543,14 @@
 	//disable ECC temp
 	dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	ecc_bit = dword & DCL_DimmEccEn;
-	dword &= ~(DCL_DimmEccEn); 
+	dword &= ~(DCL_DimmEccEn);
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword);
 
 
 	if(Pass == DQS_FIRST_PASS) {
 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
 	cpu_f0_f1 = is_cpu_pre_f2_in_bsp(ctrl->node_id);
-	if(!cpu_f0_f1) 
+	if(!cpu_f0_f1)
 #endif
 	{
 #if 1
@@ -566,27 +566,27 @@
 	dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
 	dword &= DCH_MemClkFreq_MASK;
 
-	T1000 = get_exact_T1000(dword); 
+	T1000 = get_exact_T1000(dword);
 
-	// SetupRcvrPattern 
+	// SetupRcvrPattern
 	buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (0xfffffff0));
-        buf_b = buf_a + 128; //??
+	buf_b = buf_a + 128; //??
 	if(Pass==DQS_FIRST_PASS) {
-	        for(i=0;i<16;i++) {
-        	        *((uint32_t *)(buf_a + i*4)) = TestPattern0[i];
-	                *((uint32_t *)(buf_b + i*4)) = TestPattern1[i];
-        	}
+		for(i=0;i<16;i++) {
+			*((uint32_t *)(buf_a + i*4)) = TestPattern0[i];
+			*((uint32_t *)(buf_b + i*4)) = TestPattern1[i];
+		}
 	}
 	else {
-                for(i=0;i<16;i++) {
-                        *((uint32_t *)(buf_a + i*4)) = TestPattern2[i];
+		for(i=0;i<16;i++) {
+			*((uint32_t *)(buf_a + i*4)) = TestPattern2[i];
 			*((uint32_t *)(buf_b + i*4)) = TestPattern2[i];
-                }
+		}
 	}
 
 	print_debug_dqs("\r\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0);
 
-	print_debug_addr("TrainRcvEn: buf_a:", buf_a); 
+	print_debug_addr("TrainRcvEn: buf_a:", buf_a);
 
 	Errors = 0;
 	/* for each channel */
@@ -606,10 +606,10 @@
 		/* there are four recriver pairs, loosely associated with CS */ 
 		for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) 
 		{
-			
+
 			unsigned index=(receiver>>1) * 3 + 0x10;
 
-	                print_debug_dqs("\t\tTrainRcvEn52: index ", index, 2); 
+			print_debug_dqs("\t\tTrainRcvEn52: index ", index, 2);
 
 			if(is_Width128) {
 				if(channel) {
@@ -618,22 +618,22 @@
 				}
 			}
 			else {
-				if(channel) { 
+				if(channel) {
 					index += 0x20;
 				}
-			}	
+			}
 
 			LastTest = DQS_FAIL;
 			RcvrEnDlyRmin = 0xaf;
-				
+
 			if(!RcvrRankEnabled(ctrl, channel, receiver, is_Width128, sysinfo)) continue;
 
 			/* for each DQS receiver enable setting */
-	
+
 			TestAddr0 = Get_RcvrSysAddr(ctrl, channel, receiver, sysinfo);
 
 			TestAddr0B = TestAddr0 + (1<<(20+2-8)); // 4MB
-	
+
 			if(RcvrRankEnabled(ctrl, channel, receiver+1, is_Width128, sysinfo)) {
 				TestAddr1 = Get_RcvrSysAddr(ctrl, channel, receiver+1, sysinfo);
 				TestAddr1B = TestAddr1 + (1<<(20+2-8)); //4MB
@@ -643,7 +643,7 @@
 				two_ranks = 0;
 			}
 
-	                print_debug_dqs("\t\tTrainRcvEn53: TestAddr0B ", TestAddr0B, 2); 
+			print_debug_dqs("\t\tTrainRcvEn53: TestAddr0B ", TestAddr0B, 2);
 
 			Write1LTestPattern(TestAddr0, 0, buf_a, buf_b); // rank0 of dimm, test p0
 			Write1LTestPattern(TestAddr0B, 1, buf_a, buf_b); //rank0 of dimm, test p1
@@ -654,13 +654,13 @@
 			}
 
 			if(Pass == DQS_FIRST_PASS) {
-				RcvrEnDly = 0; 
+				RcvrEnDly = 0;
 			} else {
 				RcvrEnDly = dqs_rcvr_dly_a[channel * 8 + receiver];
 			}
 
 			while ( RcvrEnDly < 0xaf) { // Sweep Delay value here
-		                print_debug_dqs("\t\t\tTrainRcvEn541: RcvrEnDly ", RcvrEnDly, 3);
+				print_debug_dqs("\t\t\tTrainRcvEn541: RcvrEnDly ", RcvrEnDly, 3);
 
 				if(RcvrEnDly & 1) {
 					/* Odd steps get another pattern such that even
@@ -680,15 +680,15 @@
 				/* Program current Receiver enable delay */
 				pci_write_config32_index_wait(ctrl->f2, 0x98, index, RcvrEnDly);
 				/* FIXME: 64bit MUX */
-	
+
 				if(is_Width128) {
 					/* Program current Receiver enable delay chaannel b */
 					pci_write_config32_index_wait(ctrl->f2, 0x98, index+ 0x20, RcvrEnDly);
 				}
-			
-                                /* Program the MaxAsyncLat filed with the
-                                   current DQS receiver enable setting plus 6ns
-                                */	
+
+				/* Program the MaxAsyncLat filed with the
+				   current DQS receiver enable setting plus 6ns
+				*/
 				/*Porgram MaxAsyncLat to correspond with current delay */
 				SetMaxAL_RcvrDly(ctrl, RcvrEnDly);
 
@@ -701,36 +701,36 @@
 
 				ResetDCTWrPtr(ctrl);
 
-				print_debug_dqs("\t\t\tTrainRcvEn542: Test0 ", Test0, 3); 
+				print_debug_dqs("\t\t\tTrainRcvEn542: Test0 ", Test0, 3);
 
 				if(Test0 == DQS_PASS) {
 
 					Read1LTestPattern(TestAddr0B);
-                               		Test1 = CompareTestPatternQW0(channel, TestAddr0B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128);
+			       		Test1 = CompareTestPatternQW0(channel, TestAddr0B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128);
 					proc_IOCLFLUSH(TestAddr0B);
 
 					ResetDCTWrPtr(ctrl);
 
-					print_debug_dqs("\t\t\tTrainRcvEn543: Test1 ", Test1, 3); 
-					
+					print_debug_dqs("\t\t\tTrainRcvEn543: Test1 ", Test1, 3);
+
 					if(Test1 == DQS_PASS) {
 						if(two_ranks) {
 							Read1LTestPattern(TestAddr1);
-                                			Test0 = CompareTestPatternQW0(channel, TestAddr1, PatternA, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128);
-                                			proc_IOCLFLUSH(TestAddr1);
-                                			ResetDCTWrPtr(ctrl);
+							Test0 = CompareTestPatternQW0(channel, TestAddr1, PatternA, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128);
+							proc_IOCLFLUSH(TestAddr1);
+							ResetDCTWrPtr(ctrl);
 
-                                			if(Test0 == DQS_PASS) {
-                                        			Read1LTestPattern(TestAddr1B);
-                                        			Test1 = CompareTestPatternQW0(channel, TestAddr1B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128);
-                                        			proc_IOCLFLUSH(TestAddr1B);
-                                        			ResetDCTWrPtr(ctrl);
+							if(Test0 == DQS_PASS) {
+								Read1LTestPattern(TestAddr1B);
+								Test1 = CompareTestPatternQW0(channel, TestAddr1B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128);
+								proc_IOCLFLUSH(TestAddr1B);
+								ResetDCTWrPtr(ctrl);
 
-                                        			if(Test1 == DQS_PASS) {
-                                                        		CurrTest = DQS_PASS;
-                                                		}
-                                        		} 
-							print_debug_dqs("\t\t\tTrainRcvEn544: Test0 ", Test0, 3); 
+								if(Test1 == DQS_PASS) {
+									CurrTest = DQS_PASS;
+								}
+							}
+							print_debug_dqs("\t\t\tTrainRcvEn544: Test0 ", Test0, 3);
 						}
 						else {
 							CurrTest = DQS_PASS;
@@ -738,7 +738,7 @@
 					}
 				}
 
-				print_debug_dqs("\t\t\tTrainRcvEn55: RcvrEnDly ", RcvrEnDly, 3); 
+				print_debug_dqs("\t\t\tTrainRcvEn55: RcvrEnDly ", RcvrEnDly, 3);
 
 				if(CurrTest == DQS_PASS) {
 					if(LastTest == DQS_FAIL) {
@@ -746,61 +746,61 @@
 						break;
 					}
 				}
-				
+
 				LastTest = CurrTest;
-				
+
 				/* swap the rank 0 pointers */
 				tmp = TestAddr0;
 				TestAddr0 = TestAddr0B;
 				TestAddr0B = tmp;
 
 				/* swap the rank 1 pointers */
-                                tmp = TestAddr1;
-                                TestAddr1 = TestAddr1B;
-                                TestAddr1B = tmp;
+				tmp = TestAddr1;
+				TestAddr1 = TestAddr1B;
+				TestAddr1B = tmp;
 
-				print_debug_dqs("\t\t\tTrainRcvEn56: RcvrEnDly ", RcvrEnDly, 3); 
-				
+				print_debug_dqs("\t\t\tTrainRcvEn56: RcvrEnDly ", RcvrEnDly, 3);
+
 				RcvrEnDly++;
-				
+
 			} // while RcvrEnDly
 
-			print_debug_dqs("\t\tTrainRcvEn61: RcvrEnDly ", RcvrEnDly, 2); 
+			print_debug_dqs("\t\tTrainRcvEn61: RcvrEnDly ", RcvrEnDly, 2);
 
 			if(RcvrEnDlyRmin == 0xaf) {
 				//no passing window
 				Errors |= SB_NORCVREN;
 			}
 
-                        if(Pass == DQS_FIRST_PASS) {
-                                // We need a better value for DQSPos trainning
-                                RcvrEnDly = RcvrEnDlyRmin /* + RCVREN_MARGIN * T1000/64/50 */;
-                        } else {
-                                RcvrEnDly = RcvrEnDlyRmin;
-                        }
+			if(Pass == DQS_FIRST_PASS) {
+				// We need a better value for DQSPos trainning
+				RcvrEnDly = RcvrEnDlyRmin /* + RCVREN_MARGIN * T1000/64/50 */;
+			} else {
+				RcvrEnDly = RcvrEnDlyRmin;
+			}
 
-                        if(RcvrEnDly > 0xae) {
-                                //passing window too narrow, too far delayed
-                                Errors |= SB_SmallRCVR;
-                                RcvrEnDly = 0xae;
-                        }
+			if(RcvrEnDly > 0xae) {
+				//passing window too narrow, too far delayed
+				Errors |= SB_SmallRCVR;
+				RcvrEnDly = 0xae;
+			}
 
-                        if(Pass == DQS_SECOND_PASS) { //second pass must average vales
-                                RcvrEnDly += dqs_rcvr_dly_a[channel * 8 + receiver] /* - (RCVREN_MARGIN * T1000/64/50)*/;
-                                RcvrEnDly >>= 1;
-                        }
-		
-			dqs_rcvr_dly_a[channel * 8 + receiver] = RcvrEnDly; 
-	
-			//Set final RcvrEnDly for this DIMM and Channel	
+			if(Pass == DQS_SECOND_PASS) { //second pass must average vales
+				RcvrEnDly += dqs_rcvr_dly_a[channel * 8 + receiver] /* - (RCVREN_MARGIN * T1000/64/50)*/;
+				RcvrEnDly >>= 1;
+			}
+
+			dqs_rcvr_dly_a[channel * 8 + receiver] = RcvrEnDly;
+
+			//Set final RcvrEnDly for this DIMM and Channel
 			pci_write_config32_index_wait(ctrl->f2, 0x98, index, RcvrEnDly);
-		
+
 			if(is_Width128) {
 				pci_write_config32_index_wait(ctrl->f2, 0x98, index+0x20, RcvrEnDly); // channel B
-				if(channel) { 
+				if(channel) {
 					pci_write_config32_index_wait(ctrl->f2, 0x98, index, CurrRcvrCHADelay);
 					if(RcvrEnDly > CurrRcvrCHADelay) {
-						dword = RcvrEnDly - CurrRcvrCHADelay;	
+						dword = RcvrEnDly - CurrRcvrCHADelay;
 					}
 					else {
 						dword = CurrRcvrCHADelay - RcvrEnDly;
@@ -812,53 +812,53 @@
 				}
 			}
 
-			print_debug_dqs("\t\tTrainRcvEn63: RcvrEnDly ", RcvrEnDly, 2); 
+			print_debug_dqs("\t\tTrainRcvEn63: RcvrEnDly ", RcvrEnDly, 2);
 
 			if(RcvrEnDly > CTLRMaxDelay) {
 				CTLRMaxDelay = RcvrEnDly;
 			}
 
-			print_debug_dqs("\t\tTrainRcvEn64: CTLRMaxDelay ", CTLRMaxDelay, 2); 
-			
+			print_debug_dqs("\t\tTrainRcvEn64: CTLRMaxDelay ", CTLRMaxDelay, 2);
+
 		} /* receiver */
 	} /* channel */
 
-	print_debug_dqs("\tTrainRcvEn65: CTLRMaxDelay ", CTLRMaxDelay, 1); 
+	print_debug_dqs("\tTrainRcvEn65: CTLRMaxDelay ", CTLRMaxDelay, 1);
 
-        /* Program the MaxAsysncLat field with the largest DQS Receiver Enable setting */
+	/* Program the MaxAsysncLat field with the largest DQS Receiver Enable setting */
 	SetMaxAL_RcvrDly(ctrl, CTLRMaxDelay);
 	ResetDCTWrPtr(ctrl);
 
-	//Enable ECC again 
-        dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
-        dword &= ~(DCL_DimmEccEn);
+	//Enable ECC again
+	dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dword &= ~(DCL_DimmEccEn);
 	dword |= ecc_bit;
-        pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword);
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword);
 
 	if(Pass == DQS_FIRST_PASS) {
 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
-	if(!cpu_f0_f1) 
+	if(!cpu_f0_f1)
 #endif
 	{
 		dword = pci_read_config32(ctrl->f2, DRAM_CTRL);
-	        dword &= ~DC_DqsRcvEnTrain;
-	        pci_write_config32(ctrl->f2, DRAM_CTRL, dword);
+		dword &= ~DC_DqsRcvEnTrain;
+		pci_write_config32(ctrl->f2, DRAM_CTRL, dword);
 	}
 	}
 
-	//Clear wrap32dis 
+	//Clear wrap32dis
 
 	clear_wrap32dis();
 
 	//restore SSE2 setting
 	disable_sse2();
 
-#if MEM_TRAIN_SEQ != 1  
+#if MEM_TRAIN_SEQ != 1
 	/* We need tidy output for type 1 */
 	#if CONFIG_USE_PRINTK_IN_CAR
 	printk_debug(" CTLRMaxDelay=%02x", CTLRMaxDelay);
 	#else
-	print_debug(" CTLRMaxDelay="); print_debug_hex8(CTLRMaxDelay); 
+	print_debug(" CTLRMaxDelay="); print_debug_hex8(CTLRMaxDelay);
 	#endif
 #endif
 
@@ -872,20 +872,20 @@
 
 static void SetDQSDelayCSR(const struct mem_controller *ctrl, unsigned channel, unsigned bytelane, unsigned direction, unsigned dqs_delay)
 { //ByteLane could be 0-8, last is for ECC
-        unsigned index;
-        uint32_t dword;
+	unsigned index;
+	uint32_t dword;
 	unsigned shift;
 
-        dqs_delay &= 0xff;
+	dqs_delay &= 0xff;
 
-        index = (bytelane>>2) + 1 + channel * 0x20 + (direction << 2);
+	index = (bytelane>>2) + 1 + channel * 0x20 + (direction << 2);
 	shift = bytelane;
 	while(shift>3) {
 		shift-=4;
 	}
 	shift <<= 3; // 8 bit
 
-        dword = pci_read_config32_index_wait(ctrl->f2, 0x98, index);
+	dword = pci_read_config32_index_wait(ctrl->f2, 0x98, index);
 	dword &= ~(0x3f<<shift);
 	dword |= (dqs_delay<<shift);
 	pci_write_config32_index_wait(ctrl->f2, 0x98, index, dword);
@@ -897,10 +897,10 @@
 	unsigned index;
 	uint32_t dword;
 	int i;
-	
+
 	dword = 0;
 	dqs_delay &= 0xff;
-	for(i=0;i<4;i++) { 
+	for(i=0;i<4;i++) {
 		dword |= dqs_delay<<(i*8);
 	}
 
@@ -909,7 +909,7 @@
 	for(i=0; i<2; i++) {
 		pci_write_config32_index_wait(ctrl->f2, 0x98, index + i, dword);
 	}
-	
+
 }
 
 static unsigned MiddleDQS(unsigned min_d, unsigned max_d)
@@ -924,7 +924,7 @@
 
 static  inline void save_dqs_delay(unsigned channel, unsigned bytelane, unsigned direction, uint8_t *dqs_delay_a, uint8_t dqs_delay)
 {
-        dqs_delay_a[channel * 2*9 + direction * 9 + bytelane] = dqs_delay;
+	dqs_delay_a[channel * 2*9 + direction * 9 + bytelane] = dqs_delay;
 }
 
 static void WriteDQSTestPattern(unsigned addr_lo, unsigned pattern , uint8_t *buf_a)
@@ -932,58 +932,58 @@
 	WriteLNTestPattern(addr_lo, buf_a, (pattern+1) * 9);
 }
 
-static void ReadL18TestPattern(unsigned addr_lo) 
+static void ReadL18TestPattern(unsigned addr_lo)
 {
-        //set fs and use fs prefix to access the mem
-        __asm__ volatile (
-                "movl %%fs:-128(%%esi), %%eax\n\t"  //TestAddr cache line
+	//set fs and use fs prefix to access the mem
+	__asm__ volatile (
+		"movl %%fs:-128(%%esi), %%eax\n\t"  //TestAddr cache line
 		"movl %%fs:-64(%%esi), %%eax\n\t"   //+1
 		"movl %%fs:(%%esi), %%eax\n\t"	//+2
 		"movl %%fs:64(%%esi), %%eax\n\t"   //+3
 
-                "movl %%fs:-128(%%edi), %%eax\n\t"	//+4
-                "movl %%fs:-64(%%edi), %%eax\n\t"	//+5
-                "movl %%fs:(%%edi), %%eax\n\t"	//+6
-                "movl %%fs:64(%%edi), %%eax\n\t"	//+7
+		"movl %%fs:-128(%%edi), %%eax\n\t"	//+4
+		"movl %%fs:-64(%%edi), %%eax\n\t"	//+5
+		"movl %%fs:(%%edi), %%eax\n\t"	//+6
+		"movl %%fs:64(%%edi), %%eax\n\t"	//+7
 
-                "movl %%fs:-128(%%ebx), %%eax\n\t"  //+8
-                "movl %%fs:-64(%%ebx), %%eax\n\t"	//+9
-                "movl %%fs:(%%ebx), %%eax\n\t"	//+10
-                "movl %%fs:64(%%ebx), %%eax\n\t"	//+11
+		"movl %%fs:-128(%%ebx), %%eax\n\t"  //+8
+		"movl %%fs:-64(%%ebx), %%eax\n\t"	//+9
+		"movl %%fs:(%%ebx), %%eax\n\t"	//+10
+		"movl %%fs:64(%%ebx), %%eax\n\t"	//+11
 
-                "movl %%fs:-128(%%ecx), %%eax\n\t"	//+12
-                "movl %%fs:-64(%%ecx), %%eax\n\t"	//+13
-                "movl %%fs:(%%ecx), %%eax\n\t"	//+14
-                "movl %%fs:64(%%ecx), %%eax\n\t"	//+15
+		"movl %%fs:-128(%%ecx), %%eax\n\t"	//+12
+		"movl %%fs:-64(%%ecx), %%eax\n\t"	//+13
+		"movl %%fs:(%%ecx), %%eax\n\t"	//+14
+		"movl %%fs:64(%%ecx), %%eax\n\t"	//+15
 
-                "movl %%fs:-128(%%edx), %%eax\n\t"	//+16
-                "movl %%fs:-64(%%edx), %%eax\n\t"	//+17
+		"movl %%fs:-128(%%edx), %%eax\n\t"	//+16
+		"movl %%fs:-64(%%edx), %%eax\n\t"	//+17
 
-                :: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), "d" (addr_lo +128+16*64), "S"(addr_lo+128), "D"(addr_lo+128+4*64)
-        );
+		:: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), "d" (addr_lo +128+16*64), "S"(addr_lo+128), "D"(addr_lo+128+4*64)
+	);
 
 }
 
-static void ReadL9TestPattern(unsigned addr_lo) 
+static void ReadL9TestPattern(unsigned addr_lo)
 {
 
-        //set fs and use fs prefix to access the mem
-        __asm__ volatile (
+	//set fs and use fs prefix to access the mem
+	__asm__ volatile (
 
-                "movl %%fs:-128(%%ecx), %%eax\n\t"  //TestAddr cache line
-                "movl %%fs:-64(%%ecx), %%eax\n\t"   //+1
-                "movl %%fs:(%%ecx), %%eax\n\t"      //+2
-                "movl %%fs:64(%%ecx), %%eax\n\t"   //+3
+		"movl %%fs:-128(%%ecx), %%eax\n\t"  //TestAddr cache line
+		"movl %%fs:-64(%%ecx), %%eax\n\t"   //+1
+		"movl %%fs:(%%ecx), %%eax\n\t"      //+2
+		"movl %%fs:64(%%ecx), %%eax\n\t"   //+3
 
-                "movl %%fs:-128(%%edx), %%eax\n\t"  //+4
-                "movl %%fs:-64(%%edx), %%eax\n\t"   //+5
-                "movl %%fs:(%%edx), %%eax\n\t"      //+6
-                "movl %%fs:64(%%edx), %%eax\n\t"   //+7
+		"movl %%fs:-128(%%edx), %%eax\n\t"  //+4
+		"movl %%fs:-64(%%edx), %%eax\n\t"   //+5
+		"movl %%fs:(%%edx), %%eax\n\t"      //+6
+		"movl %%fs:64(%%edx), %%eax\n\t"   //+7
 
-                "movl %%fs:-128(%%ebx), %%eax\n\t"      //+8
+		"movl %%fs:-128(%%ebx), %%eax\n\t"      //+8
 
-                :: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128), "d"(addr_lo+128+4*64) 
-        );
+		:: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128), "d"(addr_lo+128+4*64)
+	);
 
 }
 
@@ -1000,56 +1000,56 @@
 
 static void FlushDQSTestPattern_L9(unsigned addr_lo)
 {
-        __asm__ volatile (
-                "clflush %%fs:-128(%%ecx)\n\t"
-                "clflush %%fs:-64(%%ecx)\n\t"
-                "clflush %%fs:(%%ecx)\n\t"
-                "clflush %%fs:64(%%ecx)\n\t"
+	__asm__ volatile (
+		"clflush %%fs:-128(%%ecx)\n\t"
+		"clflush %%fs:-64(%%ecx)\n\t"
+		"clflush %%fs:(%%ecx)\n\t"
+		"clflush %%fs:64(%%ecx)\n\t"
 
-                "clflush %%fs:-128(%%eax)\n\t"
-                "clflush %%fs:-64(%%eax)\n\t"
-                "clflush %%fs:(%%eax)\n\t"
-                "clflush %%fs:64(%%eax)\n\t"
+		"clflush %%fs:-128(%%eax)\n\t"
+		"clflush %%fs:-64(%%eax)\n\t"
+		"clflush %%fs:(%%eax)\n\t"
+		"clflush %%fs:64(%%eax)\n\t"
 
-                "clflush %%fs:-128(%%ebx)\n\t"
+		"clflush %%fs:-128(%%ebx)\n\t"
 
-                ::  "b" (addr_lo+128+8*64), "c"(addr_lo+128), "a"(addr_lo+128+4*64)
+		::  "b" (addr_lo+128+8*64), "c"(addr_lo+128), "a"(addr_lo+128+4*64)
 	);
 
 }
 static __attribute__((noinline)) void FlushDQSTestPattern_L18(unsigned addr_lo)
 {
        __asm__ volatile (
-                "clflush %%fs:-128(%%eax)\n\t"
-                "clflush %%fs:-64(%%eax)\n\t"
-                "clflush %%fs:(%%eax)\n\t"
-                "clflush %%fs:64(%%eax)\n\t"
+		"clflush %%fs:-128(%%eax)\n\t"
+		"clflush %%fs:-64(%%eax)\n\t"
+		"clflush %%fs:(%%eax)\n\t"
+		"clflush %%fs:64(%%eax)\n\t"
 
-                "clflush %%fs:-128(%%edi)\n\t"
-                "clflush %%fs:-64(%%edi)\n\t"
-                "clflush %%fs:(%%edi)\n\t"
-                "clflush %%fs:64(%%edi)\n\t"
+		"clflush %%fs:-128(%%edi)\n\t"
+		"clflush %%fs:-64(%%edi)\n\t"
+		"clflush %%fs:(%%edi)\n\t"
+		"clflush %%fs:64(%%edi)\n\t"
 
-                "clflush %%fs:-128(%%ebx)\n\t"
-                "clflush %%fs:-64(%%ebx)\n\t"
-                "clflush %%fs:(%%ebx)\n\t"
-                "clflush %%fs:64(%%ebx)\n\t"
+		"clflush %%fs:-128(%%ebx)\n\t"
+		"clflush %%fs:-64(%%ebx)\n\t"
+		"clflush %%fs:(%%ebx)\n\t"
+		"clflush %%fs:64(%%ebx)\n\t"
 
-                "clflush %%fs:-128(%%ecx)\n\t"
-                "clflush %%fs:-64(%%ecx)\n\t"
-                "clflush %%fs:(%%ecx)\n\t"
-                "clflush %%fs:64(%%ecx)\n\t"
+		"clflush %%fs:-128(%%ecx)\n\t"
+		"clflush %%fs:-64(%%ecx)\n\t"
+		"clflush %%fs:(%%ecx)\n\t"
+		"clflush %%fs:64(%%ecx)\n\t"
 
-                "clflush %%fs:-128(%%edx)\n\t"
-                "clflush %%fs:-64(%%edx)\n\t"
+		"clflush %%fs:-128(%%edx)\n\t"
+		"clflush %%fs:-64(%%edx)\n\t"
 
-                :: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), "d" (addr_lo +128+16*64), "a"(addr_lo+128), "D"(addr_lo+128+4*64)
+		:: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), "d" (addr_lo +128+16*64), "a"(addr_lo+128), "D"(addr_lo+128+4*64)
 	);
 }
 
 static void FlushDQSTestPattern(unsigned addr_lo, unsigned pattern )
 {
-	
+
 	if(pattern == 0){
 		FlushDQSTestPattern_L9(addr_lo);
 	}
@@ -1060,7 +1060,7 @@
 
 static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsigned pattern, uint8_t *buf_a)
 {
-        uint32_t *test_buf;
+	uint32_t *test_buf;
 	unsigned bitmap = 0xff;
 	unsigned bytelane;
 	int i;
@@ -1068,48 +1068,48 @@
 	int j;
 	uint32_t value_test;
 
-        test_buf = (uint32_t *)buf_a;
-	
+	test_buf = (uint32_t *)buf_a;
 
-        if(pattern && channel) {
-                addr_lo += 8; //second channel
-                test_buf+= 2;
-        }
 
+	if(pattern && channel) {
+		addr_lo += 8; //second channel
+		test_buf+= 2;
+	}
+
 	bytelane = 0;
 	for(i=0;i<9*64/4;i++) {
-	        __asm__ volatile (
-	                "movl %%fs:(%1), %0\n\t"
-        	        :"=b"(value): "a" (addr_lo)
-        	);
+		__asm__ volatile (
+			"movl %%fs:(%1), %0\n\t"
+			:"=b"(value): "a" (addr_lo)
+		);
 		value_test = *test_buf;
 
-		print_debug_dqs_pair("\t\t\t\t\t\ttest_buf= ", (unsigned)test_buf, " value = ", value_test, 7); 
+		print_debug_dqs_pair("\t\t\t\t\t\ttest_buf= ", (unsigned)test_buf, " value = ", value_test, 7);
 		print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ",addr_lo, " value = ", value, 7);
 
 		for(j=0;j<4*8;j+=8) {
 			if(((value>>j)&0xff) != ((value_test>>j)& 0xff)) {
 				bitmap &= ~(1<<bytelane);
 			}
-		
+
 			bytelane++;
-			bytelane &= 0x7; 
+			bytelane &= 0x7;
 		}
-		print_debug_dqs("\t\t\t\t\t\tbitmap = ", bitmap, 7);  
+		print_debug_dqs("\t\t\t\t\t\tbitmap = ", bitmap, 7);
 
 		if(bytelane == 0) {
-			if(pattern == 1) { //dual channel 
+			if(pattern == 1) { //dual channel
 				addr_lo += 8; //skip over other channel's data
 				test_buf += 2;
 			}
 		}
 		addr_lo += 4;
 		test_buf +=1;
-		
+
 	}
 
 
-        return bitmap;
+	return bitmap;
 
 }
 
@@ -1119,11 +1119,11 @@
 	unsigned Errors;
 	unsigned BanksPresent;
 
-	unsigned MutualCSPassW[48];	
+	unsigned MutualCSPassW[48];
 
 	unsigned ChipSel;
 	unsigned DQSDelay;
-	
+
 	unsigned TestAddr;
 
 	unsigned LastTest;
@@ -1142,16 +1142,16 @@
 	}
 
 	for(ChipSel = 0; ChipSel < 8; ChipSel++) { //logical register chipselects 0..7
-		print_debug_dqs("\t\t\t\tTrainDQSPos: 11 ChipSel ", ChipSel, 4); 
+		print_debug_dqs("\t\t\t\tTrainDQSPos: 11 ChipSel ", ChipSel, 4);
 		//FIXME: process 64MUXedMode
 		if(!ChipSelPresent(ctrl, ChipSel, sysinfo)) continue;
 		BanksPresent  = 1;
 
 		TestAddr = Get_MCTSysAddr(ctrl, ChipSel, sysinfo);
 
-		print_debug_dqs("\t\t\t\tTrainDQSPos: 12 TestAddr ", TestAddr, 4); 
+		print_debug_dqs("\t\t\t\tTrainDQSPos: 12 TestAddr ", TestAddr, 4);
 
-	        //set fs and use fs prefix to access the mem
+		//set fs and use fs prefix to access the mem
 		set_FSBASE(TestAddr>>24);
 
 		if(Direction == DQS_READDIR) {
@@ -1160,28 +1160,28 @@
 		}
 
 		for(DQSDelay = 0; DQSDelay < 48; DQSDelay++ ){
-			print_debug_dqs("\t\t\t\t\tTrainDQSPos: 141 DQSDelay ", DQSDelay, 5); 
+			print_debug_dqs("\t\t\t\t\tTrainDQSPos: 141 DQSDelay ", DQSDelay, 5);
 			if(MutualCSPassW[DQSDelay] == 0) continue; //skip current delay value if other chipselects have failed all 8 bytelanes
 			SetDQSDelayAllCSR(ctrl, channel, Direction, DQSDelay);
-			print_debug_dqs("\t\t\t\t\tTrainDQSPos: 142 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); 
+			print_debug_dqs("\t\t\t\t\tTrainDQSPos: 142 MutualCSPassW ", MutualCSPassW[DQSDelay], 5);
 			if(Direction == DQS_WRITEDIR) {
 				print_debug_dqs("\t\t\t\t\tTrainDQSPos: 143 for write", 0, 5);
-				WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a); 
+				WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a);
 			}
 			print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", Pattern, 5);
-			ReadDQSTestPattern(TestAddr<<8, Pattern); 
+			ReadDQSTestPattern(TestAddr<<8, Pattern);
 			print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5);
 			MutualCSPassW[DQSDelay] &= CompareDQSTestPattern(channel, TestAddr<<8, Pattern, buf_a); //0: fail, 1=pass
-			print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); 
+			print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 MutualCSPassW ", MutualCSPassW[DQSDelay], 5);
 			SetTargetWTIO(TestAddr);
-			FlushDQSTestPattern(TestAddr<<8, Pattern); 
+			FlushDQSTestPattern(TestAddr<<8, Pattern);
 			ResetTargetWTIO();
 		}
 	}
 
-	if(BanksPresent) 
+	if(BanksPresent)
 	for(ByteLane = 0; ByteLane < 8; ByteLane++) {
-		print_debug_dqs("\t\t\t\tTrainDQSPos: 31 ByteLane ",ByteLane, 4); 
+		print_debug_dqs("\t\t\t\tTrainDQSPos: 31 ByteLane ",ByteLane, 4);
 
 		LastTest = DQS_FAIL;
 		RnkDlySeqPassMax = 0;
@@ -1190,8 +1190,8 @@
 		for(DQSDelay=0; DQSDelay<48; DQSDelay++) {
 			if(MutualCSPassW[DQSDelay] & (1<<ByteLane)) {
 
-				print_debug_dqs("\t\t\t\t\tTrainDQSPos: 321 DQSDelay ", DQSDelay, 5); 
-				print_debug_dqs("\t\t\t\t\tTrainDQSPos: 322 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); 
+				print_debug_dqs("\t\t\t\t\tTrainDQSPos: 321 DQSDelay ", DQSDelay, 5);
+				print_debug_dqs("\t\t\t\t\tTrainDQSPos: 322 MutualCSPassW ", MutualCSPassW[DQSDelay], 5);
 
 				RnkDlySeqPassMax = DQSDelay;
 				if(LastTest == DQS_FAIL) {
@@ -1207,165 +1207,165 @@
 				LastTest = DQS_FAIL;
 			}
 		}
-		print_debug_dqs("\t\t\t\tTrainDQSPos: 33 RnkDlySeqPassMax ", RnkDlySeqPassMax, 4); 
+		print_debug_dqs("\t\t\t\tTrainDQSPos: 33 RnkDlySeqPassMax ", RnkDlySeqPassMax, 4);
 
 		if(RnkDlySeqPassMax == 0) {
 			Errors |= SB_NODQSPOS; // no passing window
 		}
 		else {
-			print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMax ", RnkDlyFilterMax, 4); 
-			print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMin ", RnkDlyFilterMin, 4); 
+			print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMax ", RnkDlyFilterMax, 4);
+			print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMin ", RnkDlyFilterMin, 4);
 			if((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW){
 				Errors |= SB_SMALLDQS;
 			}
 			else {
 				unsigned middle_dqs;
-				middle_dqs = MiddleDQS(RnkDlyFilterMin, RnkDlyFilterMax); 
-				print_debug_dqs("\t\t\t\tTrainDQSPos: 35 middle_dqs ",middle_dqs, 4); 
+				middle_dqs = MiddleDQS(RnkDlyFilterMin, RnkDlyFilterMax);
+				print_debug_dqs("\t\t\t\tTrainDQSPos: 35 middle_dqs ",middle_dqs, 4);
 				SetDQSDelayCSR(ctrl, channel, ByteLane, Direction, middle_dqs);
 				save_dqs_delay(channel, ByteLane, Direction, dqs_delay_a, middle_dqs);
 			}
-		}	
+		}
 
 	}
 
 	print_debug_dqs("\t\t\tTrainDQSPos: end", 0xff, 3);
-	
+
 	return Errors;
-	
 
+
 }
 
 static unsigned TrainReadDQS(const struct mem_controller *ctrl, unsigned channel, unsigned pattern, uint8_t *buf_a, uint8_t *dqs_delay_a, struct sys_info *sysinfo)
 {
-	print_debug_dqs("\t\tTrainReadPos", 0, 2); 
-	return TrainDQSPos(ctrl, channel, DQS_READDIR, pattern, buf_a, dqs_delay_a, sysinfo);	
+	print_debug_dqs("\t\tTrainReadPos", 0, 2);
+	return TrainDQSPos(ctrl, channel, DQS_READDIR, pattern, buf_a, dqs_delay_a, sysinfo);
 }
 
 static unsigned TrainWriteDQS(const struct mem_controller *ctrl, unsigned channel, unsigned pattern, uint8_t *buf_a, uint8_t *dqs_delay_a, struct sys_info *sysinfo)
 {
 	print_debug_dqs("\t\tTrainWritePos", 0, 2);
-        return TrainDQSPos(ctrl, channel, DQS_WRITEDIR, pattern, buf_a, dqs_delay_a, sysinfo);
+	return TrainDQSPos(ctrl, channel, DQS_WRITEDIR, pattern, buf_a, dqs_delay_a, sysinfo);
 }
 
 
 
 static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info *sysinfo)
 {
-        static const uint32_t TestPatternJD1a[] = {
+	static const uint32_t TestPatternJD1a[] = {
 					0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, // QW0-1, ALL-EVEN
-                                        0x00000000,0x00000000,0x00000000,0x00000000, // QW2-3, ALL-EVEN
-                                        0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, // QW4-5, ALL-EVEN
-                                        0x00000000,0x00000000,0x00000000,0x00000000, // QW6-7, ALL-EVEN
-                                        0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW0-1, DQ0-ODD
-                                        0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW2-3, DQ0-ODD
-                                        0x01010101,0x01010101,0xFeFeFeFe,0xFeFeFeFe, // QW4-5, DQ0-ODD
-                                        0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW6-7, DQ0-ODD
-                                        0x02020202,0x02020202,0x02020202,0x02020202, // QW0-1, DQ1-ODD
-                                        0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW2-3, DQ1-ODD
-                                        0xFdFdFdFd,0xFdFdFdFd,0x02020202,0x02020202, // QW4-5, DQ1-ODD
-                                        0x02020202,0x02020202,0x02020202,0x02020202, // QW6-7, DQ1-ODD
-                                        0x04040404,0x04040404,0xfBfBfBfB,0xfBfBfBfB, // QW0-1, DQ2-ODD
-                                        0x04040404,0x04040404,0x04040404,0x04040404, // QW2-3, DQ2-ODD
-                                        0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW4-5, DQ2-ODD
-                                        0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW6-7, DQ2-ODD
-                                        0x08080808,0x08080808,0xF7F7F7F7,0xF7F7F7F7, // QW0-1, DQ3-ODD
-                                        0x08080808,0x08080808,0x08080808,0x08080808, // QW2-3, DQ3-ODD
-                                        0xF7F7F7F7,0xF7F7F7F7,0x08080808,0x08080808, // QW4-5, DQ3-ODD
-                                        0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW6-7, DQ3-ODD
-                                        0x10101010,0x10101010,0x10101010,0x10101010, // QW0-1, DQ4-ODD
-                                        0xeFeFeFeF,0xeFeFeFeF,0x10101010,0x10101010, // QW2-3, DQ4-ODD
-                                        0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW4-5, DQ4-ODD
-                                        0xeFeFeFeF,0xeFeFeFeF,0x10101010,0x10101010, // QW6-7, DQ4-ODD
-                                        0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW0-1, DQ5-ODD
-                                        0xdFdFdFdF,0xdFdFdFdF,0x20202020,0x20202020, // QW2-3, DQ5-ODD
-                                        0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW4-5, DQ5-ODD
-                                        0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW6-7, DQ5-ODD
-                                        0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW0-1, DQ6-ODD
-                                        0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW2-3, DQ6-ODD
-                                        0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW4-5, DQ6-ODD
-                                        0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW6-7, DQ6-ODD
-                                        0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW0-1, DQ7-ODD
-                                        0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW2-3, DQ7-ODD
-                                        0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW4-5, DQ7-ODD
-                                        0x80808080,0x80808080,0x80808080,0x80808080  // QW6-7, DQ7-ODD
-                };
-        static const uint32_t TestPatternJD1b[] = {
+					0x00000000,0x00000000,0x00000000,0x00000000, // QW2-3, ALL-EVEN
+					0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, // QW4-5, ALL-EVEN
+					0x00000000,0x00000000,0x00000000,0x00000000, // QW6-7, ALL-EVEN
+					0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW0-1, DQ0-ODD
+					0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW2-3, DQ0-ODD
+					0x01010101,0x01010101,0xFeFeFeFe,0xFeFeFeFe, // QW4-5, DQ0-ODD
+					0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW6-7, DQ0-ODD
+					0x02020202,0x02020202,0x02020202,0x02020202, // QW0-1, DQ1-ODD
+					0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW2-3, DQ1-ODD
+					0xFdFdFdFd,0xFdFdFdFd,0x02020202,0x02020202, // QW4-5, DQ1-ODD
+					0x02020202,0x02020202,0x02020202,0x02020202, // QW6-7, DQ1-ODD
+					0x04040404,0x04040404,0xfBfBfBfB,0xfBfBfBfB, // QW0-1, DQ2-ODD
+					0x04040404,0x04040404,0x04040404,0x04040404, // QW2-3, DQ2-ODD
+					0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW4-5, DQ2-ODD
+					0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW6-7, DQ2-ODD
+					0x08080808,0x08080808,0xF7F7F7F7,0xF7F7F7F7, // QW0-1, DQ3-ODD
+					0x08080808,0x08080808,0x08080808,0x08080808, // QW2-3, DQ3-ODD
+					0xF7F7F7F7,0xF7F7F7F7,0x08080808,0x08080808, // QW4-5, DQ3-ODD
+					0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW6-7, DQ3-ODD
+					0x10101010,0x10101010,0x10101010,0x10101010, // QW0-1, DQ4-ODD
+					0xeFeFeFeF,0xeFeFeFeF,0x10101010,0x10101010, // QW2-3, DQ4-ODD
+					0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW4-5, DQ4-ODD
+					0xeFeFeFeF,0xeFeFeFeF,0x10101010,0x10101010, // QW6-7, DQ4-ODD
+					0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW0-1, DQ5-ODD
+					0xdFdFdFdF,0xdFdFdFdF,0x20202020,0x20202020, // QW2-3, DQ5-ODD
+					0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW4-5, DQ5-ODD
+					0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW6-7, DQ5-ODD
+					0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW0-1, DQ6-ODD
+					0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW2-3, DQ6-ODD
+					0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW4-5, DQ6-ODD
+					0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW6-7, DQ6-ODD
+					0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW0-1, DQ7-ODD
+					0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW2-3, DQ7-ODD
+					0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW4-5, DQ7-ODD
+					0x80808080,0x80808080,0x80808080,0x80808080  // QW6-7, DQ7-ODD
+		};
+	static const uint32_t TestPatternJD1b[] = {
 					0x00000000,0x00000000,0x00000000,0x00000000, // QW0,CHA-B, ALL-EVEN
-                                        0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, // QW1,CHA-B, ALL-EVEN
-                                        0x00000000,0x00000000,0x00000000,0x00000000, // QW2,CHA-B, ALL-EVEN
-                                        0x00000000,0x00000000,0x00000000,0x00000000, // QW3,CHA-B, ALL-EVEN
-                                        0x00000000,0x00000000,0x00000000,0x00000000, // QW4,CHA-B, ALL-EVEN
-                                        0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, // QW5,CHA-B, ALL-EVEN
-                                        0x00000000,0x00000000,0x00000000,0x00000000, // QW6,CHA-B, ALL-EVEN
-                                        0x00000000,0x00000000,0x00000000,0x00000000, // QW7,CHA-B, ALL-EVEN
-                                        0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW0,CHA-B, DQ0-ODD
-                                        0x01010101,0x01010101,0x01010101,0x01010101, // QW1,CHA-B, DQ0-ODD
-                                        0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW2,CHA-B, DQ0-ODD
-                                        0x01010101,0x01010101,0x01010101,0x01010101, // QW3,CHA-B, DQ0-ODD
-                                        0x01010101,0x01010101,0x01010101,0x01010101, // QW4,CHA-B, DQ0-ODD
-                                        0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW5,CHA-B, DQ0-ODD
-                                        0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW6,CHA-B, DQ0-ODD
-                                        0x01010101,0x01010101,0x01010101,0x01010101, // QW7,CHA-B, DQ0-ODD
-                                    	0x02020202,0x02020202,0x02020202,0x02020202, // QW0,CHA-B, DQ1-ODD
-                                    	0x02020202,0x02020202,0x02020202,0x02020202, // QW1,CHA-B, DQ1-ODD
-                                        0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW2,CHA-B, DQ1-ODD
-                                        0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW3,CHA-B, DQ1-ODD
-                                    	0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW4,CHA-B, DQ1-ODD
-                                    	0x02020202,0x02020202,0x02020202,0x02020202, // QW5,CHA-B, DQ1-ODD
-                                        0x02020202,0x02020202,0x02020202,0x02020202, // QW6,CHA-B, DQ1-ODD
-                                        0x02020202,0x02020202,0x02020202,0x02020202, // QW7,CHA-B, DQ1-ODD
-                                        0x04040404,0x04040404,0x04040404,0x04040404, // QW0,CHA-B, DQ2-ODD
-                                        0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW1,CHA-B, DQ2-ODD
-                                        0x04040404,0x04040404,0x04040404,0x04040404, // QW2,CHA-B, DQ2-ODD
-                                        0x04040404,0x04040404,0x04040404,0x04040404, // QW3,CHA-B, DQ2-ODD
-                                        0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW4,CHA-B, DQ2-ODD
-                                        0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW5,CHA-B, DQ2-ODD
-                                        0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW6,CHA-B, DQ2-ODD
-                                        0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW7,CHA-B, DQ2-ODD
-                                        0x08080808,0x08080808,0x08080808,0x08080808, // QW0,CHA-B, DQ3-ODD
-                                        0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW1,CHA-B, DQ3-ODD
-                                        0x08080808,0x08080808,0x08080808,0x08080808, // QW2,CHA-B, DQ3-ODD
-                                        0x08080808,0x08080808,0x08080808,0x08080808, // QW3,CHA-B, DQ3-ODD
-                                        0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW4,CHA-B, DQ3-ODD
-                                        0x08080808,0x08080808,0x08080808,0x08080808, // QW5,CHA-B, DQ3-ODD
-                                        0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW6,CHA-B, DQ3-ODD
-                                        0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW7,CHA-B, DQ3-ODD
-                                        0x10101010,0x10101010,0x10101010,0x10101010, // QW0,CHA-B, DQ4-ODD
-                                        0x10101010,0x10101010,0x10101010,0x10101010, // QW1,CHA-B, DQ4-ODD
-                                        0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW2,CHA-B, DQ4-ODD
-                                        0x10101010,0x10101010,0x10101010,0x10101010, // QW3,CHA-B, DQ4-ODD
-                                        0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW4,CHA-B, DQ4-ODD
-                                        0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW5,CHA-B, DQ4-ODD
-                                        0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW6,CHA-B, DQ4-ODD
-                                        0x10101010,0x10101010,0x10101010,0x10101010, // QW7,CHA-B, DQ4-ODD
-                                        0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW0,CHA-B, DQ5-ODD
-                                        0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW1,CHA-B, DQ5-ODD
-                                        0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW2,CHA-B, DQ5-ODD
-                                        0x20202020,0x20202020,0x20202020,0x20202020, // QW3,CHA-B, DQ5-ODD
-                                        0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW4,CHA-B, DQ5-ODD
-                                        0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW5,CHA-B, DQ5-ODD
-                                        0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW6,CHA-B, DQ5-ODD
-                                        0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW7,CHA-B, DQ5-ODD
-                                        0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW0,CHA-B, DQ6-ODD
-                                        0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW1,CHA-B, DQ6-ODD
-                                        0x40404040,0x40404040,0x40404040,0x40404040, // QW2,CHA-B, DQ6-ODD
-                                        0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW3,CHA-B, DQ6-ODD
-                                        0x40404040,0x40404040,0x40404040,0x40404040, // QW4,CHA-B, DQ6-ODD
-                                        0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW5,CHA-B, DQ6-ODD
-                                        0x40404040,0x40404040,0x40404040,0x40404040, // QW6,CHA-B, DQ6-ODD
-                                        0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW7,CHA-B, DQ6-ODD
-                                        0x80808080,0x80808080,0x80808080,0x80808080, // QW0,CHA-B, DQ7-ODD
-                                        0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW1,CHA-B, DQ7-ODD
-                                        0x80808080,0x80808080,0x80808080,0x80808080, // QW2,CHA-B, DQ7-ODD
-                                        0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW3,CHA-B, DQ7-ODD
-                                        0x80808080,0x80808080,0x80808080,0x80808080, // QW4,CHA-B, DQ7-ODD
-                                        0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW5,CHA-B, DQ7-ODD
-                                        0x80808080,0x80808080,0x80808080,0x80808080, // QW6,CHA-B, DQ7-ODD
-                                        0x80808080,0x80808080,0x80808080,0x80808080  // QW7,CHA-B, DQ7-ODD
-                };
-        uint8_t pattern_buf_x[64 * 18 + 16]; // We need to two cache line So have more 16 bytes to keep 16 byte alignment */
-        uint8_t *buf_a;
+					0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, // QW1,CHA-B, ALL-EVEN
+					0x00000000,0x00000000,0x00000000,0x00000000, // QW2,CHA-B, ALL-EVEN
+					0x00000000,0x00000000,0x00000000,0x00000000, // QW3,CHA-B, ALL-EVEN
+					0x00000000,0x00000000,0x00000000,0x00000000, // QW4,CHA-B, ALL-EVEN
+					0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, // QW5,CHA-B, ALL-EVEN
+					0x00000000,0x00000000,0x00000000,0x00000000, // QW6,CHA-B, ALL-EVEN
+					0x00000000,0x00000000,0x00000000,0x00000000, // QW7,CHA-B, ALL-EVEN
+					0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW0,CHA-B, DQ0-ODD
+					0x01010101,0x01010101,0x01010101,0x01010101, // QW1,CHA-B, DQ0-ODD
+					0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW2,CHA-B, DQ0-ODD
+					0x01010101,0x01010101,0x01010101,0x01010101, // QW3,CHA-B, DQ0-ODD
+					0x01010101,0x01010101,0x01010101,0x01010101, // QW4,CHA-B, DQ0-ODD
+					0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW5,CHA-B, DQ0-ODD
+					0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW6,CHA-B, DQ0-ODD
+					0x01010101,0x01010101,0x01010101,0x01010101, // QW7,CHA-B, DQ0-ODD
+				    	0x02020202,0x02020202,0x02020202,0x02020202, // QW0,CHA-B, DQ1-ODD
+				    	0x02020202,0x02020202,0x02020202,0x02020202, // QW1,CHA-B, DQ1-ODD
+					0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW2,CHA-B, DQ1-ODD
+					0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW3,CHA-B, DQ1-ODD
+				    	0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW4,CHA-B, DQ1-ODD
+				    	0x02020202,0x02020202,0x02020202,0x02020202, // QW5,CHA-B, DQ1-ODD
+					0x02020202,0x02020202,0x02020202,0x02020202, // QW6,CHA-B, DQ1-ODD
+					0x02020202,0x02020202,0x02020202,0x02020202, // QW7,CHA-B, DQ1-ODD
+					0x04040404,0x04040404,0x04040404,0x04040404, // QW0,CHA-B, DQ2-ODD
+					0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW1,CHA-B, DQ2-ODD
+					0x04040404,0x04040404,0x04040404,0x04040404, // QW2,CHA-B, DQ2-ODD
+					0x04040404,0x04040404,0x04040404,0x04040404, // QW3,CHA-B, DQ2-ODD
+					0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW4,CHA-B, DQ2-ODD
+					0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW5,CHA-B, DQ2-ODD
+					0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW6,CHA-B, DQ2-ODD
+					0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW7,CHA-B, DQ2-ODD
+					0x08080808,0x08080808,0x08080808,0x08080808, // QW0,CHA-B, DQ3-ODD
+					0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW1,CHA-B, DQ3-ODD
+					0x08080808,0x08080808,0x08080808,0x08080808, // QW2,CHA-B, DQ3-ODD
+					0x08080808,0x08080808,0x08080808,0x08080808, // QW3,CHA-B, DQ3-ODD
+					0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW4,CHA-B, DQ3-ODD
+					0x08080808,0x08080808,0x08080808,0x08080808, // QW5,CHA-B, DQ3-ODD
+					0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW6,CHA-B, DQ3-ODD
+					0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW7,CHA-B, DQ3-ODD
+					0x10101010,0x10101010,0x10101010,0x10101010, // QW0,CHA-B, DQ4-ODD
+					0x10101010,0x10101010,0x10101010,0x10101010, // QW1,CHA-B, DQ4-ODD
+					0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW2,CHA-B, DQ4-ODD
+					0x10101010,0x10101010,0x10101010,0x10101010, // QW3,CHA-B, DQ4-ODD
+					0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW4,CHA-B, DQ4-ODD
+					0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW5,CHA-B, DQ4-ODD
+					0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW6,CHA-B, DQ4-ODD
+					0x10101010,0x10101010,0x10101010,0x10101010, // QW7,CHA-B, DQ4-ODD
+					0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW0,CHA-B, DQ5-ODD
+					0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW1,CHA-B, DQ5-ODD
+					0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW2,CHA-B, DQ5-ODD
+					0x20202020,0x20202020,0x20202020,0x20202020, // QW3,CHA-B, DQ5-ODD
+					0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW4,CHA-B, DQ5-ODD
+					0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW5,CHA-B, DQ5-ODD
+					0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW6,CHA-B, DQ5-ODD
+					0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW7,CHA-B, DQ5-ODD
+					0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW0,CHA-B, DQ6-ODD
+					0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW1,CHA-B, DQ6-ODD
+					0x40404040,0x40404040,0x40404040,0x40404040, // QW2,CHA-B, DQ6-ODD
+					0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW3,CHA-B, DQ6-ODD
+					0x40404040,0x40404040,0x40404040,0x40404040, // QW4,CHA-B, DQ6-ODD
+					0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW5,CHA-B, DQ6-ODD
+					0x40404040,0x40404040,0x40404040,0x40404040, // QW6,CHA-B, DQ6-ODD
+					0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW7,CHA-B, DQ6-ODD
+					0x80808080,0x80808080,0x80808080,0x80808080, // QW0,CHA-B, DQ7-ODD
+					0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW1,CHA-B, DQ7-ODD
+					0x80808080,0x80808080,0x80808080,0x80808080, // QW2,CHA-B, DQ7-ODD
+					0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW3,CHA-B, DQ7-ODD
+					0x80808080,0x80808080,0x80808080,0x80808080, // QW4,CHA-B, DQ7-ODD
+					0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW5,CHA-B, DQ7-ODD
+					0x80808080,0x80808080,0x80808080,0x80808080, // QW6,CHA-B, DQ7-ODD
+					0x80808080,0x80808080,0x80808080,0x80808080  // QW7,CHA-B, DQ7-ODD
+		};
+	uint8_t pattern_buf_x[64 * 18 + 16]; // We need to two cache line So have more 16 bytes to keep 16 byte alignment */
+	uint8_t *buf_a;
 
 	unsigned pattern;
 	uint32_t dword;
@@ -1377,25 +1377,25 @@
 	unsigned is_Width128 = sysinfo->meminfo[ctrl->node_id].is_Width128;
 	uint8_t *dqs_delay_a = &sysinfo->dqs_delay_a[ctrl->node_id * 2*2*9]; //channel 2, direction 2 , bytelane *9
 
-        //enable SSE2
-        enable_sse2();
+	//enable SSE2
+	enable_sse2();
 
-        //wrap32dis
-        set_wrap32dis();
+	//wrap32dis
+	set_wrap32dis();
 
-        //disable ECC temp
-        dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
-        ecc_bit = dword & DCL_DimmEccEn;
-        dword &= ~(DCL_DimmEccEn);
-        pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword);
+	//disable ECC temp
+	dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	ecc_bit = dword & DCL_DimmEccEn;
+	dword &= ~(DCL_DimmEccEn);
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword);
 
 	//SetupDqsPattern
 	buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (~0xf));
 
 	if(is_Width128){
 		pattern = 1;
-	        for(i=0;i<16*18;i++) {
-                	*((uint32_t *)(buf_a + i*4)) = TestPatternJD1b[i];
+		for(i=0;i<16*18;i++) {
+			*((uint32_t *)(buf_a + i*4)) = TestPatternJD1b[i];
        		 }
 	}
 	else {
@@ -1403,10 +1403,10 @@
 		for(i=0; i<16*9;i++) {
 			*((uint32_t *)(buf_a + i*4)) = TestPatternJD1a[i];
 		}
-		
+
 	}
 
-	print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0); 
+	print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0);
 
 	print_debug_addr("TrainDQSRdWrPos: buf_a:", buf_a);
 
@@ -1419,46 +1419,46 @@
 	}
 
 	while( (channel<2) && (!Errors)) {
-		print_debug_dqs("\tTrainDQSRdWrPos: 1 channel ",channel, 1); 
+		print_debug_dqs("\tTrainDQSRdWrPos: 1 channel ",channel, 1);
 		for(DQSWrDelay = 0; DQSWrDelay < 48; DQSWrDelay++) {
 			unsigned err;
 			SetDQSDelayAllCSR(ctrl, channel, DQS_WRITEDIR, DQSWrDelay);
-			print_debug_dqs("\t\tTrainDQSRdWrPos: 21 DQSWrDelay ", DQSWrDelay, 2); 
+			print_debug_dqs("\t\tTrainDQSRdWrPos: 21 DQSWrDelay ", DQSWrDelay, 2);
 			err= TrainReadDQS(ctrl, channel, pattern, buf_a, dqs_delay_a, sysinfo);
-			print_debug_dqs("\t\tTrainDQSRdWrPos: 22 err ",err, 2); 
+			print_debug_dqs("\t\tTrainDQSRdWrPos: 22 err ",err, 2);
 			if(err == 0) break;
 			Errors |= err;
 		}
 
-		print_debug_dqs("\tTrainDQSRdWrPos: 3 DQSWrDelay ", DQSWrDelay, 1); 
+		print_debug_dqs("\tTrainDQSRdWrPos: 3 DQSWrDelay ", DQSWrDelay, 1);
 
 		if(DQSWrDelay < 48) {
 			Errors = TrainWriteDQS(ctrl, channel, pattern, buf_a, dqs_delay_a, sysinfo);
-			print_debug_dqs("\tTrainDQSRdWrPos: 4 Errors ", Errors, 1); 
+			print_debug_dqs("\tTrainDQSRdWrPos: 4 Errors ", Errors, 1);
 
 		}
 		channel++;
 		if(!is_Width128){
-			//FIXME: 64MuxMode??	
+			//FIXME: 64MuxMode??
 			channel++; // skip channel if 64-bit mode
 		}
 	}
 
-        //Enable ECC again
-        dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
-        dword &= ~(DCL_DimmEccEn);
-        dword |= ecc_bit;
-        pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword);
+	//Enable ECC again
+	dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dword &= ~(DCL_DimmEccEn);
+	dword |= ecc_bit;
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword);
 
-        //Clear wrap32dis
+	//Clear wrap32dis
 
-        clear_wrap32dis();
+	clear_wrap32dis();
 
-        //restore SSE2 setting
-        disable_sse2();
+	//restore SSE2 setting
+	disable_sse2();
 
-	print_debug_dqs("TrainDQSRdWrPos: ", 5, 0); 
-	
+	print_debug_dqs("TrainDQSRdWrPos: ", 5, 0);
+
 	return Errors;
 
 }
@@ -1469,16 +1469,16 @@
 
 static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned ByteLane1, unsigned InterFactor, unsigned Direction, uint8_t *dqs_delay_a)
 /* InterFactor: 0: 100% ByteLane 0
-                0x80: 50% between ByteLane 0 and 1
+		0x80: 50% between ByteLane 0 and 1
 		0xff: 99.6% ByteLane 1 and 0.4% like 0
 */
 {
 	unsigned DQSDelay0, DQSDelay1;
 	unsigned DQSDelay;
-	
+
 	DQSDelay0 = get_dqs_delay(channel, ByteLane0, Direction, dqs_delay_a);
-	DQSDelay1 = get_dqs_delay(channel, ByteLane1, Direction, dqs_delay_a); 
-	
+	DQSDelay1 = get_dqs_delay(channel, ByteLane1, Direction, dqs_delay_a);
+
 	if(DQSDelay0>DQSDelay1) {
 		DQSDelay = DQSDelay0 - DQSDelay1;
 		InterFactor = 0xff - InterFactor;
@@ -1491,19 +1491,19 @@
 
 	DQSDelay >>= 8; // /255
 
-        if(DQSDelay0>DQSDelay1) {
-                DQSDelay += DQSDelay1;
-        }
-        else {
-                DQSDelay += DQSDelay0;
-        }
+	if(DQSDelay0>DQSDelay1) {
+		DQSDelay += DQSDelay1;
+	}
+	else {
+		DQSDelay += DQSDelay0;
+	}
 
 	return DQSDelay;
 
 }
 
 static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info *sysinfo)
-{	
+{
 	unsigned channel;
 	unsigned ByteLane;
 	unsigned Direction;
@@ -1521,7 +1521,7 @@
 			Direction = direction[i];
 			lane0 = 4; lane1 = 5; ratio = 0;
 			dqs_delay = CalcEccDQSPos(channel, lane0, lane1, ratio, Direction, dqs_delay_a);
-			print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction==DQS_READDIR? " R dqs_delay":" W dqs_delay",  dqs_delay, 2); 
+			print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction==DQS_READDIR? " R dqs_delay":" W dqs_delay",  dqs_delay, 2);
 			SetDQSDelayCSR(ctrl, channel, ByteLane, Direction, dqs_delay);
 			save_dqs_delay(channel, ByteLane, Direction, dqs_delay_a, dqs_delay);
 		}
@@ -1530,92 +1530,92 @@
 
 static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo)
 {
-	print_debug_dqs("\r\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0); 
+	print_debug_dqs("\r\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0);
 	if(TrainRcvrEn(ctrl, Pass, sysinfo)) {
 		return 1;
 	}
-	print_debug_dqs("\r\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0); 
+	print_debug_dqs("\r\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0);
 	return 0;
-	
+
 }
 static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo)
 {
-	print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); 
+	print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0);
 	if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) {
-                print_err("\r\nDQS Training Rd Wr failed ctrl"); print_err_hex8(ctrl->node_id); print_err("\r\n");
+		print_err("\r\nDQS Training Rd Wr failed ctrl"); print_err_hex8(ctrl->node_id); print_err("\r\n");
 		return 1;
 	}
 	else {
 		SetEccDQSRdWrPos(ctrl, sysinfo);
 	}
-	print_debug_dqs("\r\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0); 
+	print_debug_dqs("\r\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0);
 	return 0;
-	
+
 }
 
 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
 static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl, tsc_t *tsc0, struct sys_info *sysinfo)
 {
-        tsc_t tsc1[8];
+	tsc_t tsc1[8];
 	unsigned cpu_f0_f1[8];
 	int i;
 
-        print_debug_addr("dqs_timing: tsc1[8] :", tsc1);
+	print_debug_addr("dqs_timing: tsc1[8] :", tsc1);
 
-        for(i = 0; i < controllers; i++) {
-                if (!sysinfo->ctrl_present[i])
-                        continue;
+	for(i = 0; i < controllers; i++) {
+		if (!sysinfo->ctrl_present[i])
+			continue;
 
-                /* Skip everything if I don't have any memory on this controller */
+		/* Skip everything if I don't have any memory on this controller */
 		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-                uint32_t dword;
+		uint32_t dword;
 
-                cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i);
+		cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i);
 
-                if(!cpu_f0_f1[i]) continue;
+		if(!cpu_f0_f1[i]) continue;
 
-                dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
-                dword &= ~DC_DqsRcvEnTrain;
-                pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
+		dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
+		dword &= ~DC_DqsRcvEnTrain;
+		pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
 
-                dword = pci_read_config32(ctrl[i].f2, DRAM_INIT);
-                dword |= DI_EnDramInit;
-                pci_write_config32(ctrl[i].f2, DRAM_INIT, dword);
-                dword &= ~DI_EnDramInit;
-                pci_write_config32(ctrl[i].f2, DRAM_INIT, dword);
+		dword = pci_read_config32(ctrl[i].f2, DRAM_INIT);
+		dword |= DI_EnDramInit;
+		pci_write_config32(ctrl[i].f2, DRAM_INIT, dword);
+		dword &= ~DI_EnDramInit;
+		pci_write_config32(ctrl[i].f2, DRAM_INIT, dword);
 
-                tsc1[i] = rdtsc();
-                print_debug_dqs_tsc("begin: tsc1", i, tsc1[i].hi, tsc1[i].lo, 2);
+		tsc1[i] = rdtsc();
+		print_debug_dqs_tsc("begin: tsc1", i, tsc1[i].hi, tsc1[i].lo, 2);
 
-                dword = tsc1[i].lo + tsc0[i].lo;
-                if((dword<tsc1[i].lo) || (dword<tsc0[i].lo)) {
-                        tsc1[i].hi++;
-                }
-                tsc1[i].lo = dword;
-                tsc1[i].hi+= tsc0[i].hi;
+		dword = tsc1[i].lo + tsc0[i].lo;
+		if((dword<tsc1[i].lo) || (dword<tsc0[i].lo)) {
+			tsc1[i].hi++;
+		}
+		tsc1[i].lo = dword;
+		tsc1[i].hi+= tsc0[i].hi;
 
-                print_debug_dqs_tsc("end  : tsc1", i, tsc1[i].hi, tsc1[i].lo, 2);
+		print_debug_dqs_tsc("end  : tsc1", i, tsc1[i].hi, tsc1[i].lo, 2);
 
-        }
+	}
 
-        for(i = 0; i < controllers; i++) {
-                if (!sysinfo->ctrl_present[i])
-                        continue;
+	for(i = 0; i < controllers; i++) {
+		if (!sysinfo->ctrl_present[i])
+			continue;
 
-                /* Skip everything if I don't have any memory on this controller */
+		/* Skip everything if I don't have any memory on this controller */
 		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
 		if(!cpu_f0_f1[i]) continue;
 
-                tsc_t tsc;
+		tsc_t tsc;
 
-                do {
-                        tsc = rdtsc();
-                } while ((tsc1[i].hi>tsc.hi) || ((tsc1[i].hi==tsc.hi) && (tsc1[i].lo>tsc.lo)));
+		do {
+			tsc = rdtsc();
+		} while ((tsc1[i].hi>tsc.hi) || ((tsc1[i].hi==tsc.hi) && (tsc1[i].lo>tsc.lo)));
 
-                print_debug_dqs_tsc("end  : tsc ", i, tsc.hi, tsc.lo, 2);
-        }
+		print_debug_dqs_tsc("end  : tsc ", i, tsc.hi, tsc.lo, 2);
+	}
 
 }
 
@@ -1624,211 +1624,211 @@
 
 /* setting variable mtrr, comes from linux kernel source */
 static void set_var_mtrr_dqs(
-        unsigned int reg, unsigned long basek, unsigned long sizek,
-        unsigned char type, unsigned address_bits)
+	unsigned int reg, unsigned long basek, unsigned long sizek,
+	unsigned char type, unsigned address_bits)
 {
-        msr_t base, mask;
-        unsigned address_mask_high;
+	msr_t base, mask;
+	unsigned address_mask_high;
 
-        address_mask_high = ((1u << (address_bits - 32u)) - 1u);
+	address_mask_high = ((1u << (address_bits - 32u)) - 1u);
 
-        base.hi = basek >> 22;
-        base.lo  = basek << 10;
+	base.hi = basek >> 22;
+	base.lo  = basek << 10;
 
-        if (sizek < 4*1024*1024) {
-                mask.hi = address_mask_high;
-                mask.lo = ~((sizek << 10) -1);
-        }
-        else {
-                mask.hi = address_mask_high & (~((sizek >> 22) -1));
-                mask.lo = 0;
-        }
+	if (sizek < 4*1024*1024) {
+		mask.hi = address_mask_high;
+		mask.lo = ~((sizek << 10) -1);
+	}
+	else {
+		mask.hi = address_mask_high & (~((sizek >> 22) -1));
+		mask.lo = 0;
+	}
 
-        if (reg >= 8)
-                return;
+	if (reg >= 8)
+		return;
 
-        if (sizek == 0) {
-                msr_t zero;
-                zero.lo = zero.hi = 0;
-                /* The invalid bit is kept in the mask, so we simply clear the
-                   relevant mask register to disable a range. */
-                wrmsr (MTRRphysMask_MSR(reg), zero);
-        } else {
-                /* Bit 32-35 of MTRRphysMask should be set to 1 */
-                base.lo |= type;
-                mask.lo |= 0x800;
-                wrmsr (MTRRphysBase_MSR(reg), base);
-                wrmsr (MTRRphysMask_MSR(reg), mask);
-        }
+	if (sizek == 0) {
+		msr_t zero;
+		zero.lo = zero.hi = 0;
+		/* The invalid bit is kept in the mask, so we simply clear the
+		   relevant mask register to disable a range. */
+		wrmsr (MTRRphysMask_MSR(reg), zero);
+	} else {
+		/* Bit 32-35 of MTRRphysMask should be set to 1 */
+		base.lo |= type;
+		mask.lo |= 0x800;
+		wrmsr (MTRRphysBase_MSR(reg), base);
+		wrmsr (MTRRphysMask_MSR(reg), mask);
+	}
 }
 
 
 /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
 static inline unsigned int fms(unsigned int x)
 {
-        int r;
+	int r;
 
-        __asm__("bsrl %1,%0\n\t"
-                "jnz 1f\n\t"
-                "movl $0,%0\n"
-                "1:" : "=r" (r) : "g" (x));
-        return r;
+	__asm__("bsrl %1,%0\n\t"
+		"jnz 1f\n\t"
+		"movl $0,%0\n"
+		"1:" : "=r" (r) : "g" (x));
+	return r;
 }
 
 /* fms: find least sigificant bit set */
 static inline unsigned int fls(unsigned int x)
 {
-        int r;
+	int r;
 
-        __asm__("bsfl %1,%0\n\t"
-                "jnz 1f\n\t"
-                "movl $32,%0\n"
-                "1:" : "=r" (r) : "g" (x));
-        return r;
+	__asm__("bsfl %1,%0\n\t"
+		"jnz 1f\n\t"
+		"movl $32,%0\n"
+		"1:" : "=r" (r) : "g" (x));
+	return r;
 }
 
 static unsigned int range_to_mtrr(unsigned int reg,
-        unsigned long range_startk, unsigned long range_sizek,
-        unsigned long next_range_startk, unsigned char type, unsigned address_bits)
+	unsigned long range_startk, unsigned long range_sizek,
+	unsigned long next_range_startk, unsigned char type, unsigned address_bits)
 {
-        if (!range_sizek || (reg >= 8)) {
-                return reg;
-        }
-        while(range_sizek) {
-                unsigned long max_align, align;
-                unsigned long sizek;
-                /* Compute the maximum size I can make a range */
-                max_align = fls(range_startk);
-                align = fms(range_sizek);
-                if (align > max_align) {
-                        align = max_align;
-                }
-                sizek = 1 << align;
+	if (!range_sizek || (reg >= 8)) {
+		return reg;
+	}
+	while(range_sizek) {
+		unsigned long max_align, align;
+		unsigned long sizek;
+		/* Compute the maximum size I can make a range */
+		max_align = fls(range_startk);
+		align = fms(range_sizek);
+		if (align > max_align) {
+			align = max_align;
+		}
+		sizek = 1 << align;
 #if MEM_TRAIN_SEQ != 1
 	#if CONFIG_USE_PRINTK_IN_CAR
-                printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n",
-                        reg, range_startk >>10, sizek >> 10,
-                        (type==MTRR_TYPE_UNCACHEABLE)?"UC":
-                            ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
-                        );
+		printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n",
+			reg, range_startk >>10, sizek >> 10,
+			(type==MTRR_TYPE_UNCACHEABLE)?"UC":
+			    ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
+			);
 	#else
-                print_debug("Setting variable MTRR "); print_debug_hex8(reg); print_debug(", base: "); print_debug_hex16(range_startk>>10); 
-			print_debug("MB, range: "); print_debug_hex16(sizek >> 10); print_debug("MB, type "); 
+		print_debug("Setting variable MTRR "); print_debug_hex8(reg); print_debug(", base: "); print_debug_hex16(range_startk>>10);
+			print_debug("MB, range: "); print_debug_hex16(sizek >> 10); print_debug("MB, type ");
 			print_debug( (type==MTRR_TYPE_UNCACHEABLE)?"UC\r\n":
-                                      ((type==MTRR_TYPE_WRBACK)?"WB\r\n":"Other\r\n")
-                                   );
+				      ((type==MTRR_TYPE_WRBACK)?"WB\r\n":"Other\r\n")
+				   );
 	#endif
 #endif
-                set_var_mtrr_dqs(reg++, range_startk, sizek, type, address_bits);
-                range_startk += sizek;
-                range_sizek -= sizek;
-                if (reg >= 8)
-                        break;
-        }
-        return reg;
+		set_var_mtrr_dqs(reg++, range_startk, sizek, type, address_bits);
+		range_startk += sizek;
+		range_sizek -= sizek;
+		if (reg >= 8)
+			break;
+	}
+	return reg;
 }
 
 static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k)
 {
-        msr_t msr;
+	msr_t msr;
 
-        /* Now set top of memory */
-        msr.lo = (tom2_k & 0x003fffff) << 10;
-        msr.hi = (tom2_k & 0xffc00000) >> 22;
-        wrmsr(TOP_MEM2, msr);
+	/* Now set top of memory */
+	msr.lo = (tom2_k & 0x003fffff) << 10;
+	msr.hi = (tom2_k & 0xffc00000) >> 22;
+	wrmsr(TOP_MEM2, msr);
 
-        msr.lo = (tom_k & 0x003fffff) << 10;
-        msr.hi = (tom_k & 0xffc00000) >> 22;
-        wrmsr(TOP_MEM, msr);
+	msr.lo = (tom_k & 0x003fffff) << 10;
+	msr.hi = (tom_k & 0xffc00000) >> 22;
+	wrmsr(TOP_MEM, msr);
 }
 
 static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k){
-        unsigned reg;
-        msr_t msr;
+	unsigned reg;
+	msr_t msr;
 
 #if 0
-        //still enable from cache_as_ram.inc
-        msr = rdmsr(SYSCFG_MSR);
-        msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-        wrmsr(SYSCFG_MSR,msr);
+	//still enable from cache_as_ram.inc
+	msr = rdmsr(SYSCFG_MSR);
+	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYSCFG_MSR,msr);
 #endif
 
-        //[0,512k), [512k, 640k)
-        msr.hi = 0x1e1e1e1e;
-        msr.lo = msr.hi;
-        wrmsr(0x250, msr);
-        wrmsr(0x258, msr);
+	//[0,512k), [512k, 640k)
+	msr.hi = 0x1e1e1e1e;
+	msr.lo = msr.hi;
+	wrmsr(0x250, msr);
+	wrmsr(0x258, msr);
 
-        //[1M, TOM)
-        reg = range_to_mtrr(2, 0, tom_k,4*1024*1024, MTRR_TYPE_WRBACK, 40);
+	//[1M, TOM)
+	reg = range_to_mtrr(2, 0, tom_k,4*1024*1024, MTRR_TYPE_WRBACK, 40);
 
-        //[4G, TOM2)
-        if(tom2_k) {
-                //enable tom2 and type
-                msr = rdmsr(SYSCFG_MSR);
-                msr.lo |= (1<<21) | (1<<22); //MtrrTom2En and Tom2ForceMemTypeWB
-                wrmsr(SYSCFG_MSR, msr);
-        }
+	//[4G, TOM2)
+	if(tom2_k) {
+		//enable tom2 and type
+		msr = rdmsr(SYSCFG_MSR);
+		msr.lo |= (1<<21) | (1<<22); //MtrrTom2En and Tom2ForceMemTypeWB
+		wrmsr(SYSCFG_MSR, msr);
+	}
 
 }
 
 static void clear_mtrr_dqs(unsigned tom2_k){
-        msr_t msr;
-        unsigned i;
+	msr_t msr;
+	unsigned i;
 
-        //still enable from cache_as_ram.inc
-        msr = rdmsr(SYSCFG_MSR);
-        msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-        wrmsr(SYSCFG_MSR,msr);
+	//still enable from cache_as_ram.inc
+	msr = rdmsr(SYSCFG_MSR);
+	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYSCFG_MSR,msr);
 
-        //[0,512k), [512k, 640k)
-        msr.hi = 0;
-        msr.lo = msr.hi;
-        wrmsr(0x250, msr);
-        wrmsr(0x258, msr);
+	//[0,512k), [512k, 640k)
+	msr.hi = 0;
+	msr.lo = msr.hi;
+	wrmsr(0x250, msr);
+	wrmsr(0x258, msr);
 
-        //[1M, TOM)
-        for(i=0x204;i<0x210;i++) {
-                wrmsr(i, msr);
-        }
+	//[1M, TOM)
+	for(i=0x204;i<0x210;i++) {
+		wrmsr(i, msr);
+	}
 
-        //[4G, TOM2)
-        if(tom2_k) {
-                //enable tom2 and type
-                msr = rdmsr(SYSCFG_MSR);
-                msr.lo &= ~((1<<21) | (1<<22)); //MtrrTom2En and Tom2ForceMemTypeWB
-                wrmsr(SYSCFG_MSR, msr);
-        }
+	//[4G, TOM2)
+	if(tom2_k) {
+		//enable tom2 and type
+		msr = rdmsr(SYSCFG_MSR);
+		msr.lo &= ~((1<<21) | (1<<22)); //MtrrTom2En and Tom2ForceMemTypeWB
+		wrmsr(SYSCFG_MSR, msr);
+	}
 }
 
 static void set_htic_bit(unsigned i, unsigned val, unsigned bit)
 {
-        uint32_t dword;
-        dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL);
-        dword &= ~(1<<bit);
-        dword |= ((val & 1) <<bit);
-        pci_write_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL, dword);
+	uint32_t dword;
+	dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL);
+	dword &= ~(1<<bit);
+	dword |= ((val & 1) <<bit);
+	pci_write_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL, dword);
 }
 
 
 static unsigned get_htic_bit(unsigned i, unsigned bit)
 {
-        uint32_t dword;
-        dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL);
-        dword &= (1<<bit);
-        return dword;
+	uint32_t dword;
+	dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL);
+	dword &= (1<<bit);
+	return dword;
 }
 
 static void wait_till_sysinfo_in_ram(void)
 {
-        while(1) {
-                if(get_htic_bit(0, 9)) return;
-        }
+	while(1) {
+		if(get_htic_bit(0, 9)) return;
+	}
 }
 
 static void set_sysinfo_in_ram(unsigned val)
 {
-        set_htic_bit(0, val, 9);
+	set_htic_bit(0, val, 9);
 }
 
 
@@ -1845,32 +1845,32 @@
 
 	tsc_t tsc[5];
 
-        //need to enable mtrr, so dqs training could access the test address
-        setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
+	//need to enable mtrr, so dqs training could access the test address
+	setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
 
-        for(i = 0; i < controllers; i++) {
-                if (!sysinfo->ctrl_present[ i ])
-                        continue;
+	for(i = 0; i < controllers; i++) {
+		if (!sysinfo->ctrl_present[ i ])
+			continue;
 
-                /* Skip everything if I don't have any memory on this controller */
-                if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
+		/* Skip everything if I don't have any memory on this controller */
+		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
 		fill_mem_cs_sysinfo(i, ctrl+i, sysinfo);
 	}
 
 	tsc[0] = rdtsc();
-        for(i = 0; i < controllers; i++) {
-                if (!sysinfo->ctrl_present[ i ])
-                        continue;
+	for(i = 0; i < controllers; i++) {
+		if (!sysinfo->ctrl_present[ i ])
+			continue;
 
-                /* Skip everything if I don't have any memory on this controller */
+		/* Skip everything if I don't have any memory on this controller */
 		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-                print_debug("DQS Training:RcvrEn:Pass1: ");
-                print_debug_hex8(i);
-                if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out;
-       	        print_debug(" done\r\n");
-        }
+		print_debug("DQS Training:RcvrEn:Pass1: ");
+		print_debug_hex8(i);
+		if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out;
+       		print_debug(" done\r\n");
+	}
 
 	tsc[1] = rdtsc();
 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
@@ -1878,33 +1878,33 @@
 #endif
 
 	tsc[2] = rdtsc();
-        for(i = 0; i < controllers; i++) {
-                if (!sysinfo->ctrl_present[i])
-                        continue;
+	for(i = 0; i < controllers; i++) {
+		if (!sysinfo->ctrl_present[i])
+			continue;
 
-                /* Skip everything if I don't have any memory on this controller */
+		/* Skip everything if I don't have any memory on this controller */
 		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-                print_debug("DQS Training:DQSPos: ");
-                print_debug_hex8(i);
-                if(train_DqsPos(ctrl+i, sysinfo)) goto out;
-                print_debug(" done\r\n");
-        }
+		print_debug("DQS Training:DQSPos: ");
+		print_debug_hex8(i);
+		if(train_DqsPos(ctrl+i, sysinfo)) goto out;
+		print_debug(" done\r\n");
+	}
 
 	tsc[3] = rdtsc();
-        for(i = 0; i < controllers; i++) {
-                if (!sysinfo->ctrl_present[i])
-                        continue;
+	for(i = 0; i < controllers; i++) {
+		if (!sysinfo->ctrl_present[i])
+			continue;
 
-                /* Skip everything if I don't have any memory on this controller */
+		/* Skip everything if I don't have any memory on this controller */
 		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-                print_debug("DQS Training:RcvrEn:Pass2: ");
-                print_debug_hex8(i);
-                if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
-                print_debug(" done\r\n");
+		print_debug("DQS Training:RcvrEn:Pass2: ");
+		print_debug_hex8(i);
+		if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
+		print_debug(" done\r\n");
 		sysinfo->mem_trained[i]=1;
-        }
+	}
 
 out:
 	tsc[4] = rdtsc();
@@ -1916,82 +1916,82 @@
 	}
 
 
-	
+
 }
 
 #endif
 
 
-#if MEM_TRAIN_SEQ > 0 
+#if MEM_TRAIN_SEQ > 0
 
 static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info *sysinfo, unsigned v)
 {
 
-        int ii;
+	int ii;
 
-         tsc_t tsc[4];
+	 tsc_t tsc[4];
 
 	if(sysinfo->mem_trained[i] != 0x80) return;
 
 #if MEM_TRAIN_SEQ == 1
-        //need to enable mtrr, so dqs training could access the test address
-        setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
+	//need to enable mtrr, so dqs training could access the test address
+	setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
 #endif
 
 	fill_mem_cs_sysinfo(i, ctrl, sysinfo);
 
 	if(v) {
-	        tsc[0] = rdtsc();
+		tsc[0] = rdtsc();
 
-	        print_debug("set DQS timing:RcvrEn:Pass1: ");
-	        print_debug_hex8(i);
+		print_debug("set DQS timing:RcvrEn:Pass1: ");
+		print_debug_hex8(i);
 	}
-        if(train_DqsRcvrEn(ctrl, 1,  sysinfo)) {
+	if(train_DqsRcvrEn(ctrl, 1,  sysinfo)) {
 		sysinfo->mem_trained[i]=0x81; //
 		goto out;
 	}
 
 	if(v) {
-	        print_debug(" done\r\n");
-        	tsc[1] = rdtsc();
-	        print_debug("set DQS timing:DQSPos: ");
-	        print_debug_hex8(i);
+		print_debug(" done\r\n");
+		tsc[1] = rdtsc();
+		print_debug("set DQS timing:DQSPos: ");
+		print_debug_hex8(i);
 	}
 
-        if(train_DqsPos(ctrl, sysinfo)) {
+	if(train_DqsPos(ctrl, sysinfo)) {
 		sysinfo->mem_trained[i]=0x82; //
 		goto out;
 	}
-	
+
 	if(v) {
-	        print_debug(" done\r\n");
-	        tsc[2] = rdtsc();
+		print_debug(" done\r\n");
+		tsc[2] = rdtsc();
 
-	        print_debug("set DQS timing:RcvrEn:Pass2: ");
-	        print_debug_hex8(i);
+		print_debug("set DQS timing:RcvrEn:Pass2: ");
+		print_debug_hex8(i);
 	}
-        if(train_DqsRcvrEn(ctrl, 2,  sysinfo)){
+	if(train_DqsRcvrEn(ctrl, 2,  sysinfo)){
 		sysinfo->mem_trained[i]=0x83; //
 		goto out;
 	}
 
 	if(v) {
-	        print_debug(" done\r\n");
+		print_debug(" done\r\n");
 
-	        tsc[3] = rdtsc();
+		tsc[3] = rdtsc();
 	}
 
 out:
 #if MEM_TRAIN_SEQ == 1
-        clear_mtrr_dqs(sysinfo->tom2_k);
+	clear_mtrr_dqs(sysinfo->tom2_k);
 #endif
 
 	if(v) {
-	        for(ii=0;ii<4;ii++) {
-        	      print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii,  tsc[ii].hi, tsc[ii].lo);
-	        }
+		for(ii=0;ii<4;ii++) {
+		      print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii,  tsc[ii].hi, tsc[ii].lo);
+		}
 	}
-	
+
 	if(sysinfo->mem_trained[i] == 0x80) {
 		sysinfo->mem_trained[i]=1;
 	}

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_test.c	2008-10-02 19:20:22 UTC (rev 3632)
@@ -51,7 +51,7 @@
 	unsigned addr;
 	uint32_t value;
 	addr = dev | where;
-	value =  pci_register[addr] | 
+	value =  pci_register[addr] |
 		(pci_register[addr + 1]  << 8) |
 		(pci_register[addr + 2]  << 16) |
 		(pci_register[addr + 3]  << 24);
@@ -128,23 +128,23 @@
 
 unsigned long log2(unsigned long x)
 {
-        // assume 8 bits per byte.
-        unsigned long i = 1 << (sizeof(x)*8 - 1);
-        unsigned long pow = sizeof(x) * 8 - 1;
+	// assume 8 bits per byte.
+	unsigned long i = 1 << (sizeof(x)*8 - 1);
+	unsigned long pow = sizeof(x) * 8 - 1;
 
-        if (! x) {
+	if (! x) {
 		static const char errmsg[] = " called with invalid parameter of 0\n";
 		write(STDERR_FILENO, __func__, sizeof(__func__) - 1);
 		write(STDERR_FILENO, errmsg, sizeof(errmsg) - 1);
-                hlt();
-        }
-        for(; i > x; i >>= 1, pow--)
-                ;
+		hlt();
+	}
+	for(; i > x; i >>= 1, pow--)
+		;
 
-        return pow;
+	return pow;
 }
 
-typedef struct msr_struct 
+typedef struct msr_struct
 {
 	unsigned lo;
 	unsigned hi;
@@ -188,10 +188,10 @@
 }
 
 
-static uint8_t spd_mt4lsdt464a[256] = 
+static uint8_t spd_mt4lsdt464a[256] =
 {
-	0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70, 
-	0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01, 
+	0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70,
+	0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01,
 	0x01, 0x00, 0x0E, 0x75, 0x54, 0x00, 0x00, 0x0F, 0x0E, 0x0F,
 
 	0x25, 0x08, 0x15, 0x08, 0x15, 0x08, 0x00, 0x12, 0x01, 0x4E,
@@ -200,46 +200,46 @@
 	0x06, 0x07, 0x08, 0x09, 0x00,
 };
 
-static uint8_t spd_micron_512MB_DDR333[256] = 
+static uint8_t spd_micron_512MB_DDR333[256] =
 {
-	0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60, 
-	0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01, 
-	0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 
-	0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff, 
-	0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31, 
-	0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, 
-	0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 
+	0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60,
+	0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
+	0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
+	0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31,
+	0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43,
+	0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff 
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff
 };
 
-static uint8_t spd_micron_256MB_DDR333[256] = 
+static uint8_t spd_micron_256MB_DDR333[256] =
 {
-	0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60, 
-	0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01, 
-	0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 
+	0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60,
+	0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
+	0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
 	0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x3c, 0x48, 0x30, 0x23, 0x50, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x58, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36, 
+	0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36,
 	0x34, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, 0x31,
 	0x20, 0x01, 0x00, 0x03, 0x19, 0x17, 0x05, 0xb2, 0xf4, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -247,17 +247,17 @@
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 };
 
 #define MAX_DIMMS 16
@@ -273,7 +273,7 @@
 	}
 	else {
 		device -= 0x50;
-		
+
 		if (address > 256) {
 			result = -1;
 		}
@@ -390,13 +390,13 @@
 #endif
 
 	raminit_main();
-	
+
 #if 0
 	print_debug("spd_count: ");
 	print_debug_hex32(spd_count);
 	print_debug("\r\n");
 #endif
-	
+
 }
 
 
@@ -413,10 +413,10 @@
 	print_debug("\r\nSPD will fail after: ");
 	print_debug_hex32(spd_fail_count);
 	print_debug(" accesses.\r\n");
-	
+
 	memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
 	memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
-	
+
 	raminit_main();
 
  done:
@@ -429,7 +429,7 @@
 	for(i = 0; i < 0x48; i++) {
 		do_test2(i);
 	}
-	
+
 }
 
 int main(int argc, char **argv)

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/reset_test.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/reset_test.c	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/reset_test.c	2008-10-02 19:20:22 UTC (rev 3632)
@@ -54,29 +54,29 @@
 
 static unsigned node_link_to_bus(unsigned node, unsigned link)
 {
-        unsigned reg;
+	unsigned reg;
 
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue;
-                }
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {
-                        return (config_map >> 16) & 0xff;
-                }
-        }
-        return 0;
+	for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+		unsigned config_map;
+		config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
+		if ((config_map & 3) != 3) {
+			continue;
+		}
+		if ((((config_map >> 4) & 7) == node) &&
+			(((config_map >> 8) & 3) == link))
+		{
+			return (config_map >> 16) & 0xff;
+		}
+	}
+	return 0;
 }
 
 static unsigned get_sblk(void)
 {
-        uint32_t reg;
-        /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
-        reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
-        return ((reg>>8) & 3) ;
+	uint32_t reg;
+	/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
+	reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
+	return ((reg>>8) & 3) ;
 }
 
 static unsigned get_sbbusn(unsigned sblk)

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/resourcemap.c	2008-10-02 19:20:22 UTC (rev 3632)
@@ -139,7 +139,7 @@
 	 *	   1 = base/limit registers i are read-only
 	 * [ 7: 4] Reserved
 	 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-	 *	   This field defines the upper address bits of a 40bit address 
+	 *	   This field defines the upper address bits of a 40bit address
 	 *	   that defines the start of memory-mapped I/O region i
 	 */
 	PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
@@ -195,7 +195,7 @@
 	 * [ 3: 2] Reserved
 	 * [ 4: 4] VGA Enable
 	 *	   0 = VGA matches Disabled
-	 *	   1 = matches all address < 64K and where A[9:0] is in the 
+	 *	   1 = matches all address < 64K and where A[9:0] is in the
 	 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 	 * [ 5: 5] ISA Enable
 	 *	   0 = ISA matches Disabled
@@ -203,7 +203,7 @@
 	 *	       from matching agains this base/limit pair
 	 * [11: 6] Reserved
 	 * [24:12] PCI I/O Base i
-	 *	   This field defines the start of PCI I/O region n 
+	 *	   This field defines the start of PCI I/O region n
 	 * [31:25] Reserved
 	 */
 	PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/setup_resource_map.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/setup_resource_map.c	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/setup_resource_map.c	2008-10-02 19:20:22 UTC (rev 3632)
@@ -1,44 +1,44 @@
 #define RES_DEBUG 0
 
 static void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base)
-{       
-        int i;
+{
+	int i;
 //      print_debug("setting up resource map offset....");
 #if 0
-        print_debug("\r\n");
+	print_debug("\r\n");
 #endif
-        for(i = 0; i < max; i += 3) {
-                device_t dev;
-                unsigned where;
-                unsigned long reg;
+	for(i = 0; i < max; i += 3) {
+		device_t dev;
+		unsigned where;
+		unsigned long reg;
 #if 0
 	#if CONFIG_USE_PRINTK_IN_CAR
-                prink_debug("%08x <- %08x\r\n", register_values[i] +  offset_pci_dev, register_values[i+2]);
-        #else
-                print_debug_hex32(register_values[i] + offset_pci_dev);
-                print_debug(" <-");
-                print_debug_hex32(register_values[i+2]);
-                print_debug("\r\n");
-        #endif
+		prink_debug("%08x <- %08x\r\n", register_values[i] +  offset_pci_dev, register_values[i+2]);
+	#else
+		print_debug_hex32(register_values[i] + offset_pci_dev);
+		print_debug(" <-");
+		print_debug_hex32(register_values[i+2]);
+		print_debug("\r\n");
+	#endif
 #endif
-                dev = (register_values[i] & ~0xfff) + offset_pci_dev;
-                where = register_values[i] & 0xfff;
-                reg = pci_read_config32(dev, where);
-                reg &= register_values[i+1];
-                reg |= register_values[i+2] + offset_io_base;
-                pci_write_config32(dev, where, reg);
+		dev = (register_values[i] & ~0xfff) + offset_pci_dev;
+		where = register_values[i] & 0xfff;
+		reg = pci_read_config32(dev, where);
+		reg &= register_values[i+1];
+		reg |= register_values[i+2] + offset_io_base;
+		pci_write_config32(dev, where, reg);
 #if 0
-                reg = pci_read_config32(register_values[i]);
-                reg &= register_values[i+1];
-                reg |= register_values[i+2] & ~register_values[i+1];
-                pci_write_config32(register_values[i], reg);
+		reg = pci_read_config32(register_values[i]);
+		reg &= register_values[i+1];
+		reg |= register_values[i+2] & ~register_values[i+1];
+		pci_write_config32(register_values[i], reg);
 #endif
-        }
+	}
 //      print_debug("done.\r\n");
 }
 
 #define RES_PCI_IO 0x10
-#define RES_PORT_IO_8 0x22 
+#define RES_PORT_IO_8 0x22
 #define RES_PORT_IO_32 0x20
 #define RES_MEM_IO 0x40
 
@@ -57,29 +57,29 @@
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
 	#if CONFIG_USE_PRINTK_IN_CAR
-                printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n", 
-			i>>2, register_values[i], 
-			register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), 
-			register_values[i+2], 
+		printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
+			i>>2, register_values[i],
+			register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
+			register_values[i+2],
 			register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
 			);
-	#else		
-                print_debug_hex16(i>>2);
-                print_debug(": ");
-                print_debug_hex8(register_values[i]);
-                print_debug(" ");
-                print_debug_hex32(register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0) );
-                print_debug(" <- & ");
-                print_debug_hex32(register_values[i+2]);
-                print_debug(" | ");
-                print_debug_hex32(register_values[i+3] + 
+	#else
+		print_debug_hex16(i>>2);
+		print_debug(": ");
+		print_debug_hex8(register_values[i]);
+		print_debug(" ");
+		print_debug_hex32(register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0) );
+		print_debug(" <- & ");
+		print_debug_hex32(register_values[i+2]);
+		print_debug(" | ");
+		print_debug_hex32(register_values[i+3] +
 			(((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
 			);
-                print_debug("\r\n");
+		print_debug("\r\n");
 	#endif
 #endif
 		switch (register_values[i]) {
-		case RES_PCI_IO: //PCI 
+		case RES_PCI_IO: //PCI
 			{
 			device_t dev;
 			unsigned where;
@@ -115,7 +115,7 @@
 			}
 			break;
 #if 0
-		case RES_MEM_IO: //mem 
+		case RES_MEM_IO: //mem
 			{
 			unsigned where;
 			unsigned long reg;
@@ -127,10 +127,10 @@
 			}
 			break;
 #endif
-		
+
 		} // switch
-			
-			
+
+
 	}
 
 #if RES_DEBUG
@@ -138,195 +138,195 @@
 #endif
 }
 static void setup_resource_map_x(const unsigned int *register_values, int max)
-{                       
-        int i;
+{
+	int i;
 
 #if RES_DEBUG
-        print_debug("setting up resource map ex offset....");
+	print_debug("setting up resource map ex offset....");
 
 #endif
 
 #if RES_DEBUG
-        print_debug("\r\n");
+	print_debug("\r\n");
 #endif
-        for(i = 0; i < max; i += 4) {
+	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
 	#if CONFIG_USE_PRINTK_IN_CAR
-                printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
-                        i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
-        #else
-                print_debug_hex16(i/4);
-                print_debug(": ");
-                print_debug_hex8(register_values[i]);
-                print_debug(" ");
-                print_debug_hex32(register_values[i+1]);
-                print_debug(" <- & ");
-                print_debug_hex32(register_values[i+2]);
-                print_debug(" | ");
-                print_debug_hex32(register_values[i+3]);
-                print_debug("\r\n");
-        #endif
+		printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
+			i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
+	#else
+		print_debug_hex16(i/4);
+		print_debug(": ");
+		print_debug_hex8(register_values[i]);
+		print_debug(" ");
+		print_debug_hex32(register_values[i+1]);
+		print_debug(" <- & ");
+		print_debug_hex32(register_values[i+2]);
+		print_debug(" | ");
+		print_debug_hex32(register_values[i+3]);
+		print_debug("\r\n");
+	#endif
 #endif
-                switch (register_values[i]) {
-                case RES_PCI_IO: //PCI 
-                        {
-                        device_t dev;
-                        unsigned where;
-                        unsigned long reg;
-                        dev = register_values[i+1] & ~0xfff;
-                        where = register_values[i+1] & 0xfff;
-                        reg = pci_read_config32(dev, where);
-                        reg &= register_values[i+2];
-                        reg |= register_values[i+3];
-                        pci_write_config32(dev, where, reg);
-                        }
-                        break;
-                case RES_PORT_IO_8: // io 8
-                        {
-                        unsigned where;
-                        unsigned reg;
-                        where = register_values[i+1];
-                        reg = inb(where);
-                        reg &= register_values[i+2];
-                        reg |= register_values[i+3];
-                        outb(reg, where);
-                        }
-                        break;
-                case RES_PORT_IO_32:  //io32
-                        {
-                        unsigned where;
-                        unsigned long reg;
-                        where = register_values[i+1];
-                        reg = inl(where);
-                        reg &= register_values[i+2];
-                        reg |= register_values[i+3];
-                        outl(reg, where);
-                        }
-                        break;
+		switch (register_values[i]) {
+		case RES_PCI_IO: //PCI
+			{
+			device_t dev;
+			unsigned where;
+			unsigned long reg;
+			dev = register_values[i+1] & ~0xfff;
+			where = register_values[i+1] & 0xfff;
+			reg = pci_read_config32(dev, where);
+			reg &= register_values[i+2];
+			reg |= register_values[i+3];
+			pci_write_config32(dev, where, reg);
+			}
+			break;
+		case RES_PORT_IO_8: // io 8
+			{
+			unsigned where;
+			unsigned reg;
+			where = register_values[i+1];
+			reg = inb(where);
+			reg &= register_values[i+2];
+			reg |= register_values[i+3];
+			outb(reg, where);
+			}
+			break;
+		case RES_PORT_IO_32:  //io32
+			{
+			unsigned where;
+			unsigned long reg;
+			where = register_values[i+1];
+			reg = inl(where);
+			reg &= register_values[i+2];
+			reg |= register_values[i+3];
+			outl(reg, where);
+			}
+			break;
 #if 0
-                case RES_MEM_IO: //mem 
-                        {
-                        unsigned where;
-                        unsigned long reg;
-                        where = register_values[i+1];
-                        reg = read32(where);
-                        reg &= register_values[i+2];
-                        reg |= register_values[i+3];
-                        write32( where, reg);
-                        }
-                        break;
+		case RES_MEM_IO: //mem
+			{
+			unsigned where;
+			unsigned long reg;
+			where = register_values[i+1];
+			reg = read32(where);
+			reg &= register_values[i+2];
+			reg |= register_values[i+3];
+			write32( where, reg);
+			}
+			break;
 #endif
 
-                } // switch
+		} // switch
 
 
-        }
+	}
 
 #if RES_DEBUG
-        print_debug("done.\r\n");
+	print_debug("done.\r\n");
 #endif
 }
 
 static void setup_iob_resource_map(const unsigned int *register_values, int max)
 {
-        int i;
-        
+	int i;
+
 	for(i = 0; i < max; i += 3) {
-                unsigned where;
+		unsigned where;
 		unsigned reg;
-                
+
 		where = register_values[i];
 #if 0
-                udelay(2000);
-                print_debug_hex16(where);
+		udelay(2000);
+		print_debug_hex16(where);
 #endif
-                reg = inb(where);
+		reg = inb(where);
 #if 0
-                print_debug("=");
-                print_debug_hex8(reg);
+		print_debug("=");
+		print_debug_hex8(reg);
 #endif
 
-                reg &= register_values[i+1];
-                reg |= register_values[i+2];
+		reg &= register_values[i+1];
+		reg |= register_values[i+2];
 #if 0
-                print_debug(" <-  ");
-                print_debug_hex8(reg);
+		print_debug(" <-  ");
+		print_debug_hex8(reg);
 #endif
-                outb(reg, where);
+		outb(reg, where);
 #if 0
 
-                print_debug(" -> ");
+		print_debug(" -> ");
 		reg = inb(where);
-                print_debug_hex8(reg);
+		print_debug_hex8(reg);
 		print_debug("\r\n");
 #endif
-        }
+	}
 }
 
 static void setup_io_resource_map(const unsigned int *register_values, int max)
 {
-        int i;
-        
+	int i;
+
 	for(i = 0; i < max; i += 3) {
-                unsigned where;
+		unsigned where;
 		unsigned long reg;
-                
+
 		where = register_values[i];
 #if 0
-                udelay(2000);
-                print_debug_hex16(where);
+		udelay(2000);
+		print_debug_hex16(where);
 #endif
 
-                reg = inl(where);
+		reg = inl(where);
 #if 0
 		udelay(2000);
-                print_debug("=");
-                print_debug_hex32(reg);
+		print_debug("=");
+		print_debug_hex32(reg);
 #endif
-                reg &= register_values[i+1];
-                reg |= register_values[i+2];
+		reg &= register_values[i+1];
+		reg |= register_values[i+2];
 
 #if 0
 		udelay(2000);
-                print_debug(" <-  ");
-                print_debug_hex32(reg);
+		print_debug(" <-  ");
+		print_debug_hex32(reg);
 #endif
-                outl(reg, where);
+		outl(reg, where);
 #if 0
 		udelay(2000);
-                print_debug(" -> ");
-                reg = inl(where);
-                print_debug_hex32(reg);
+		print_debug(" -> ");
+		reg = inl(where);
+		print_debug_hex32(reg);
 		print_debug("\r\n");
 #endif
-        }
+	}
 }
 
 #if 0
 static void setup_mem_resource_map(const unsigned int *register_values, int max)
 {
-        int i;
-        
+	int i;
+
 	for(i = 0; i < max; i += 3) {
-                unsigned where;
+		unsigned where;
 		unsigned long reg;
 #if 0
-                print_debug_hex32(register_values[i]);
-                print_debug(" <-");
-                print_debug_hex32(register_values[i+2]);
+		print_debug_hex32(register_values[i]);
+		print_debug(" <-");
+		print_debug_hex32(register_values[i+2]);
 #endif
-                where = register_values[i];
-                reg = read32(where);
-                reg &= register_values[i+1];
-                reg |= register_values[i+2];
-                write32( where, reg);
+		where = register_values[i];
+		reg = read32(where);
+		reg &= register_values[i+1];
+		reg |= register_values[i+2];
+		write32( where, reg);
 #if 0
-                print_debug(" RB ");
-                reg = read32(where);
-                print_debug_hex32(reg);
-                print_debug("\r\n");
+		print_debug(" RB ");
+		reg = read32(where);
+		print_debug_hex32(reg);
+		print_debug("\r\n");
 #endif
-        }
+	}
 }
 #endif
 

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/spd_ddr2.h
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/spd_ddr2.h	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/spd_ddr2.h	2008-10-02 19:20:22 UTC (rev 3632)
@@ -1,7 +1,7 @@
 /*   SPDs for DDR2 SDRAM */
-#define SPD_MEM_TYPE	 2                                     
-	#define SPD_MEM_TYPE_SDRAM_DDR    0x07        
-	#define SPD_MEM_TYPE_SDRAM_DDR2   0x08     
+#define SPD_MEM_TYPE	 2
+	#define SPD_MEM_TYPE_SDRAM_DDR    0x07
+	#define SPD_MEM_TYPE_SDRAM_DDR2   0x08
 
 #define SPD_DIMM_TYPE    20 	/* x  bit0 or bit4 =1 mean registered*/
 	#define SPD_DIMM_TYPE_RDIMM	(1<<0)
@@ -11,9 +11,9 @@
 	#define SPD_DIMM_TYPE_mRDIMM	(1<<4)
 	#define SPD_DIMM_TYPE_mUDIMM	(1<<5)
 #define SPD_MOD_ATTRIB      21
-	#define SPD_MOD_ATTRIB_DIFCK    0x20           
-	#define SPD_MOD_ATTRIB_REGADC   0x11   /* x */   
-	#define SPD_MOD_ATTRIB_PROBE    0x40  
+	#define SPD_MOD_ATTRIB_DIFCK    0x20
+	#define SPD_MOD_ATTRIB_REGADC   0x11   /* x */
+	#define SPD_MOD_ATTRIB_PROBE    0x40
 
 #define SPD_DEV_ATTRIB   22  /* Device attributes --- general */
 #define SPD_DIMM_CONF_TYPE     11
@@ -22,16 +22,16 @@
 
 #define SPD_ROW_NUM        3        /* Number of Row addresses */
 #define SPD_COL_NUM        4	    /* Number of Column addresses */
-#define SPD_BANK_NUM      17        /* SDRAM Device attributes - Number of Banks on SDRAM device, it could be 0x4, 0x8, so address lines for that would be 2, and 3 */ 
- 
-#define SPD_MOD_ATTRIB_RANK      5       /* include Number of Ranks bit [2:0], Package (bit4, 1=stack, 0=planr), Height bit[7:5] */ 
+#define SPD_BANK_NUM      17        /* SDRAM Device attributes - Number of Banks on SDRAM device, it could be 0x4, 0x8, so address lines for that would be 2, and 3 */
+
+#define SPD_MOD_ATTRIB_RANK      5       /* include Number of Ranks bit [2:0], Package (bit4, 1=stack, 0=planr), Height bit[7:5] */
 	#define SPD_MOD_ATTRIB_RANK_NUM_SHIFT 0
-	#define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07 
+	#define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07
 		#define SPD_MOD_ATTRIB_RANK_NUM_BASE 1
 		#define SPD_MOD_ATTRIB_RANK_NUM_MIN 1
 		#define SPD_MOD_ATTRIB_RANK_NUM_MAX 8
 
-#define SPD_RANK_SIZE      31       /* Only one bit is set */ 
+#define SPD_RANK_SIZE      31       /* Only one bit is set */
 	#define SPD_RANK_SIZE_1GB   (1<<0)
 	#define SPD_RANK_SIZE_2GB   (1<<1)
 	#define SPD_RANK_SIZE_4GB   (1<<2)
@@ -58,7 +58,7 @@
 #define SPD_TRAS        30
 #define SPD_TWR         36            /* x */
 #define SPD_TWTR        37            /* x */
-#define SPD_TRTP        38            /* x */  
+#define SPD_TRTP        38            /* x */
 
 #define SPD_TRC         41            /* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)]  ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}*/
 #define SPD_TRFC        42	      /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] + (val40 & 1)*256*/

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/ssdt.dsl
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/ssdt.dsl	2008-10-02 18:19:17 UTC (rev 3631)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/ssdt.dsl	2008-10-02 19:20:22 UTC (rev 3632)
@@ -10,45 +10,45 @@
 
     Scope (\_SB.PCI0)
     {
-         Name (BUSN, Package (0x04)
-        {
-            0x11111111,
-            0x22222222,
-            0x33333333,
-            0x44444444
-        })
-        Name (MMIO, Package (0x10)
-        {
-            0x11111111,
-            0x22222222,
-            0x33333333,
-            0x44444444,
-            0x55555555,
-            0x66666666,
-            0x77777777,
-            0x88888888,
-            0x99999999,
-            0xaaaaaaaa,
-            0xbbbbbbbb,
-            0xcccccccc,
-            0xdddddddd,
-            0xeeeeeeee,
-            0x11111111,
-            0x22222222
-        })
-        Name (PCIO, Package (0x08)
-        {
-            0x77777777,
-            0x88888888,
-            0x99999999,
-            0xaaaaaaaa,
-            0xbbbbbbbb,
-            0xcccccccc,
-            0xdddddddd,
-            0xeeeeeeee
-        })
-        Name (SBLK, 0x11)
-        Name (TOM1, 0xaaaaaaaa)
+	 Name (BUSN, Package (0x04)
+	{
+	    0x11111111,
+	    0x22222222,
+	    0x33333333,
+	    0x44444444
+	})
+	Name (MMIO, Package (0x10)
+	{
+	    0x11111111,
+	    0x22222222,
+	    0x33333333,
+	    0x44444444,
+	    0x55555555,
+	    0x66666666,
+	    0x77777777,
+	    0x88888888,
+	    0x99999999,
+	    0xaaaaaaaa,
+	    0xbbbbbbbb,
+	    0xcccccccc,
+	    0xdddddddd,
+	    0xeeeeeeee,
+	    0x11111111,
+	    0x22222222
+	})
+	Name (PCIO, Package (0x08)
+	{
+	    0x77777777,
+	    0x88888888,
+	    0x99999999,
+	    0xaaaaaaaa,
+	    0xbbbbbbbb,
+	    0xcccccccc,
+	    0xdddddddd,
+	    0xeeeeeeee
+	})
+	Name (SBLK, 0x11)
+	Name (TOM1, 0xaaaaaaaa)
 	Name (SBDN, 0xbbbbbbbb)
 	Name (HCLK, Package (0x08)
 	{
@@ -56,22 +56,22 @@
 	    0x22222222,
 	    0x33333333,
 	    0x44444444,
-            0x55555555,
-            0x66666666,
-            0x77777777,
-            0x88888888
+	    0x55555555,
+	    0x66666666,
+	    0x77777777,
+	    0x88888888
 	})
-        Name (HCDN, Package (0x08)
-        {
-            0x11111111,
-            0x22222222,
-            0x33333333,
-            0x44444444,
-            0x55555555,
-            0x66666666,
-            0x77777777,
-            0x88888888
-        })
+	Name (HCDN, Package (0x08)
+	{
+	    0x11111111,
+	    0x22222222,
+	    0x33333333,
+	    0x44444444,
+	    0x55555555,
+	    0x66666666,
+	    0x77777777,
+	    0x88888888
+	})
 	Name (CBST, 0x88)
     }
 }




From svn at coreboot.org  Thu Oct  2 21:21:40 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Oct 2008 21:21:40 +0200
Subject: [coreboot] r3633 - in trunk/coreboot-v2/src/superio: smsc/lpc47b397
	winbond/w83627hf
Message-ID: <mailman.2162.1355071391.16123.coreboot@coreboot.org>

Author: myles
Date: 2008-10-02 21:21:30 +0200 (Thu, 02 Oct 2008)
New Revision: 3633

Modified:
   trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397.h
   trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c
   trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c
   trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c
   trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c
   trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf.h
   trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf_early_serial.c
Log:
Whitespace cleanup (trivial).

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397.h
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397.h	2008-10-02 19:20:22 UTC (rev 3632)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397.h	2008-10-02 19:21:30 UTC (rev 3633)
@@ -1,7 +1,7 @@
-#define LPC47B397_FDC              0   /* Floppy */
-#define LPC47B397_PP               3   /* Parallel Port */
-#define LPC47B397_SP1              4   /* Com1 */
-#define LPC47B397_SP2              5   /* Com2 */
-#define LPC47B397_KBC              7   /* Keyboard & Mouse */
-#define LPC47B397_HWM		   8   /* HW Monitor */
-#define LPC47B397_RT              10   /* Runtime reg*/
+#define LPC47B397_FDC		0	/* Floppy */
+#define LPC47B397_PP		3	/* Parallel Port */
+#define LPC47B397_SP1		4	/* Com1 */
+#define LPC47B397_SP2		5	/* Com2 */
+#define LPC47B397_KBC		7	/* Keyboard & Mouse */
+#define LPC47B397_HWM		8	/* HW Monitor */
+#define LPC47B397_RT		10	/* Runtime reg*/

Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c	2008-10-02 19:20:22 UTC (rev 3632)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c	2008-10-02 19:21:30 UTC (rev 3633)
@@ -2,9 +2,10 @@
 {
 	outb(value,iobase+offset);
 }
+
 static unsigned lpc47b397_gpio_offset_in(unsigned iobase, unsigned offset)
 {
-        return inb(iobase+offset);
+	return inb(iobase+offset);
 }
 
 //for GP60-GP64, GP66-GP85
@@ -13,13 +14,13 @@
 
 static void lpc47b397_gpio_index_out(unsigned iobase, unsigned index, unsigned value)
 {
-        outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX);
+	outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX);
 	outb(value, iobase+LPC47B397_GPIO_CNTL_DATA);
 }
+
 static unsigned lpc47b397_gpio_index_in(unsigned iobase, unsigned index)
 {
 	outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX);
-        return inb(iobase+LPC47B397_GPIO_CNTL_DATA);
+	return inb(iobase+LPC47B397_GPIO_CNTL_DATA);
 }
 
-

Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c	2008-10-02 19:20:22 UTC (rev 3632)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c	2008-10-02 19:21:30 UTC (rev 3633)
@@ -3,12 +3,14 @@
 
 static inline void pnp_enter_conf_state(device_t dev) {
 	unsigned port = dev>>8;
-        outb(0x55, port);
+	outb(0x55, port);
 }
+
 static void pnp_exit_conf_state(device_t dev) {
 	unsigned port = dev>>8;
-        outb(0xaa, port);
+	outb(0xaa, port);
 }
+
 static void lpc47b397_enable_serial(device_t dev, unsigned iobase)
 {
 	pnp_enter_conf_state(dev);

Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c	2008-10-02 19:20:22 UTC (rev 3632)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c	2008-10-02 19:21:30 UTC (rev 3633)
@@ -1,7 +1,7 @@
 /* Copyright 2000  AG Electronics Ltd. */
 /* Copyright 2003-2004 Linux Networx */
-/* Copyright 2004 Tyan 
- */ 
+/* Copyright 2004 Tyan
+ */
 
 /* This code is distributed without warranty under the GPL v2 (see COPYING) */
 
@@ -20,32 +20,32 @@
 
 
 static void pnp_enter_conf_state(device_t dev) {
-        outb(0x55, dev->path.u.pnp.port);
+	outb(0x55, dev->path.u.pnp.port);
 }
 static void pnp_exit_conf_state(device_t dev) {
-        outb(0xaa, dev->path.u.pnp.port);
+	outb(0xaa, dev->path.u.pnp.port);
 }
 
 static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value)
 {
-        outb(reg, port_base);
-        outb(value, port_base + 1);
+	outb(reg, port_base);
+	outb(value, port_base + 1);
 }
 
 static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg)
 {
-        outb(reg, port_base);
-        return inb(port_base + 1);
+	outb(reg, port_base);
+	return inb(port_base + 1);
 }
 
 static void enable_hwm_smbus(device_t dev) {
 	/* enable SensorBus register access */
-        uint8_t reg, value;
-        reg = 0xf0; 
-        value = pnp_read_config(dev, reg);
-        value |= 0x01;
-        pnp_write_config(dev, reg, value);
-} 
+	uint8_t reg, value;
+	reg = 0xf0;
+	value = pnp_read_config(dev, reg);
+	value |= 0x01;
+	pnp_write_config(dev, reg, value);
+}
 
 
 static void lpc47b397_init(device_t dev)
@@ -57,7 +57,7 @@
 	}
 	conf = dev->chip_info;
 	switch(dev->path.u.pnp.device) {
-	case LPC47B397_SP1: 
+	case LPC47B397_SP1:
 		res0 = find_resource(dev, PNP_IDX_IO0);
 		init_uart8250(res0->base, &conf->com1);
 		break;
@@ -71,51 +71,51 @@
 		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
 		break;
 	}
-	
+
 }
 
 void lpc47b397_pnp_set_resources(device_t dev)
 {
 
-	pnp_enter_conf_state(dev);  
+	pnp_enter_conf_state(dev);
 
 	pnp_set_resources(dev);
 
 #if 0
-        dump_pnp_device(dev);
+	dump_pnp_device(dev);
 #endif
-                
-        pnp_exit_conf_state(dev);  
-        
-}       
-        
+
+	pnp_exit_conf_state(dev);
+
+}
+
 void lpc47b397_pnp_enable_resources(device_t dev)
-{       
+{
 
-        pnp_enter_conf_state(dev);
+	pnp_enter_conf_state(dev);
 
-        pnp_enable_resources(dev);
+	pnp_enable_resources(dev);
 
-        switch(dev->path.u.pnp.device) {
-        case LPC47B397_HWM:
-                printk_debug("lpc47b397 SensorBus Register Access enabled\r\n");
+	switch(dev->path.u.pnp.device) {
+	case LPC47B397_HWM:
+		printk_debug("lpc47b397 SensorBus Register Access enabled\r\n");
 		pnp_set_logical_device(dev);
-                enable_hwm_smbus(dev);
-                break;
-        }
+		enable_hwm_smbus(dev);
+		break;
+	}
 
-#if 0  
-        dump_pnp_device(dev);
+#if 0
+	dump_pnp_device(dev);
 #endif
 
-        pnp_exit_conf_state(dev);
+	pnp_exit_conf_state(dev);
 
 }
 
 void lpc47b397_pnp_enable(device_t dev)
 {
 
-	pnp_enter_conf_state(dev);   
+	pnp_enter_conf_state(dev);
 
 	pnp_set_logical_device(dev);
 
@@ -126,8 +126,8 @@
 		pnp_set_enable(dev, 0);
 	}
 
-	pnp_exit_conf_state(dev);  
-	
+	pnp_exit_conf_state(dev);
+
 }
 
 static struct device_operations ops = {
@@ -149,60 +149,60 @@
 
 static int lsmbus_read_byte(device_t dev, uint8_t address)
 {
-        unsigned device;
-        struct resource *res;
+	unsigned device;
+	struct resource *res;
 	int result;
 
-        device = dev->path.u.i2c.device;
+	device = dev->path.u.i2c.device;
 
-        res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
+	res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
 
 	pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0?
-	
+
 	result = pnp_read_index(res->base+SB_INDEX, address); // we only read it one byte one time
-        
-        return result;
+
+	return result;
 }
 
 static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
-{       
-        unsigned device;
-        struct resource *res;
-        
-        device = dev->path.u.i2c.device;
+{
+	unsigned device;
+	struct resource *res;
+
+	device = dev->path.u.i2c.device;
 	res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
 
-        pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0?
+	pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0?
 
-        pnp_write_index(res->base+SB_INDEX, address, val); // we only write it one byte one time
-        
-        return 0;
+	pnp_write_index(res->base+SB_INDEX, address, val); // we only write it one byte one time
+
+	return 0;
 }
 
 static struct smbus_bus_operations lops_smbus_bus = {
-//        .recv_byte  = lsmbus_recv_byte,
-//        .send_byte  = lsmbus_send_byte,
-        .read_byte  = lsmbus_read_byte,
-        .write_byte = lsmbus_write_byte,
+//	.recv_byte  = lsmbus_recv_byte,
+//	.send_byte  = lsmbus_send_byte,
+	.read_byte  = lsmbus_read_byte,
+	.write_byte = lsmbus_write_byte,
 };
 static struct device_operations ops_hwm = {
-        .read_resources   = pnp_read_resources,
-        .set_resources    = lpc47b397_pnp_set_resources,
-        .enable_resources = lpc47b397_pnp_enable_resources,
-        .enable           = lpc47b397_pnp_enable,
-        .init             = lpc47b397_init,
+	.read_resources   = pnp_read_resources,
+	.set_resources    = lpc47b397_pnp_set_resources,
+	.enable_resources = lpc47b397_pnp_enable_resources,
+	.enable           = lpc47b397_pnp_enable,
+	.init             = lpc47b397_init,
 	.scan_bus         = scan_static_bus,
 	.ops_smbus_bus    = &lops_smbus_bus,
 };
 
 static struct pnp_info pnp_dev_info[] = {
-        { &ops, LPC47B397_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-        { &ops, LPC47B397_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-        { &ops, LPC47B397_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-        { &ops, LPC47B397_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-        { &ops, LPC47B397_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+	{ &ops, LPC47B397_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &ops, LPC47B397_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &ops, LPC47B397_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, LPC47B397_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, LPC47B397_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
 	{ &ops_hwm, LPC47B397_HWM,  PNP_IO0, { 0x7f0, 0 }, },
-        { &ops, LPC47B397_RT,   PNP_IO0, { 0x780, 0 }, },
+	{ &ops, LPC47B397_RT,   PNP_IO0, { 0x780, 0 }, },
 };
 
 static void enable_dev(struct device *dev)

Modified: trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c	2008-10-02 19:20:22 UTC (rev 3632)
+++ trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c	2008-10-02 19:21:30 UTC (rev 3633)
@@ -1,6 +1,6 @@
 /* Copyright 2000  AG Electronics Ltd. */
 /* Copyright 2003-2004 Linux Networx */
-/* Copyright 2004 Tyan 
+/* Copyright 2004 Tyan
    By LYH change from PC87360 */
 /* This code is distributed without warranty under the GPL v2 (see COPYING) */
 
@@ -18,27 +18,27 @@
 #include "w83627hf.h"
 
 
-static void pnp_enter_ext_func_mode(device_t dev) 
+static void pnp_enter_ext_func_mode(device_t dev)
 {
-        outb(0x87, dev->path.u.pnp.port);
-        outb(0x87, dev->path.u.pnp.port);
+	outb(0x87, dev->path.u.pnp.port);
+	outb(0x87, dev->path.u.pnp.port);
 }
-static void pnp_exit_ext_func_mode(device_t dev) 
+static void pnp_exit_ext_func_mode(device_t dev)
 {
-        outb(0xaa, dev->path.u.pnp.port);
+	outb(0xaa, dev->path.u.pnp.port);
 }
 
 static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value)
 {
-        outb(reg, port_base);
-        outb(value, port_base + 1);
+	outb(reg, port_base);
+	outb(value, port_base + 1);
 }
 
 static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg)
 {
-        outb(reg, port_base);
-        return inb(port_base + 1);
-}       
+	outb(reg, port_base);
+	return inb(port_base + 1);
+}
 
 static void enable_hwm_smbus(device_t dev) {
 	/* set the pin 91,92 as I2C bus */
@@ -56,14 +56,14 @@
 
 	get_option(&power_on, "power_on_after_fail");
 	pnp_enter_ext_func_mode(dev);
-	pnp_write_index(dev->path.u.pnp.port,7,0x0a); 
+	pnp_write_index(dev->path.u.pnp.port,7,0x0a);
 	value = pnp_read_config(dev, 0xE4);
 	value &= ~(3<<5);
 	if(power_on) {
 		value |= (1<<5);
 	}
 	pnp_write_config(dev, 0xE4, value);
-        pnp_exit_ext_func_mode(dev);  
+	pnp_exit_ext_func_mode(dev);
 }
 
 static void init_hwm(unsigned long base)
@@ -72,16 +72,16 @@
 	int i;
 
 	unsigned  hwm_reg_values[] = {
-/*	      reg  mask  data */
-              0x40, 0xff, 0x81,  /* start HWM */
-              0x48, 0xaa, 0x2a,  /* set SMBus base to 0x54>>1	*/
-              0x4a, 0x21, 0x21,  /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */
-              0x4e, 0x80, 0x00,  
-              0x43, 0x00, 0xff,
-              0x44, 0x00, 0x3f,
-              0x4c, 0xbf, 0x18,
-              0x4d, 0xff, 0x80   /* turn off beep */
-                                                                            
+/*		reg  mask  data */
+		0x40, 0xff, 0x81,  /* start HWM */
+		0x48, 0xaa, 0x2a,  /* set SMBus base to 0x54>>1	*/
+		0x4a, 0x21, 0x21,  /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */
+		0x4e, 0x80, 0x00,
+		0x43, 0x00, 0xff,
+		0x44, 0x00, 0x3f,
+		0x4c, 0xbf, 0x18,
+		0x4d, 0xff, 0x80   /* turn off beep */
+
 	};
 
 	for(i = 0; i<  ARRAY_SIZE(hwm_reg_values); i+=3 ) { 
@@ -105,7 +105,7 @@
 	}
 	conf = dev->chip_info;
 	switch(dev->path.u.pnp.device) {
-	case W83627HF_SP1: 
+	case W83627HF_SP1:
 		res0 = find_resource(dev, PNP_IDX_IO0);
 		init_uart8250(res0->base, &conf->com1);
 		break;
@@ -118,50 +118,50 @@
 		res1 = find_resource(dev, PNP_IDX_IO1);
 		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
 		break;
-        case W83627HF_HWM:
-                res0 = find_resource(dev, PNP_IDX_IO0);
+	case W83627HF_HWM:
+		res0 = find_resource(dev, PNP_IDX_IO0);
 #define HWM_INDEX_PORT 5
-                init_hwm(res0->base + HWM_INDEX_PORT);
-                break;
-        case W83627HF_ACPI:
-                init_acpi(dev);
-                break;
+		init_hwm(res0->base + HWM_INDEX_PORT);
+		break;
+	case W83627HF_ACPI:
+		init_acpi(dev);
+		break;
 	}
 }
 
 void w83627hf_pnp_set_resources(device_t dev)
 {
-	pnp_enter_ext_func_mode(dev);  
+	pnp_enter_ext_func_mode(dev);
 	pnp_set_resources(dev);
-        pnp_exit_ext_func_mode(dev);  
-        
-}       
-        
+	pnp_exit_ext_func_mode(dev);
+
+}
+
 void w83627hf_pnp_enable_resources(device_t dev)
-{       
-        pnp_enter_ext_func_mode(dev);  
-	pnp_enable_resources(dev);               
-        switch(dev->path.u.pnp.device) {
+{
+	pnp_enter_ext_func_mode(dev);
+	pnp_enable_resources(dev);
+	switch(dev->path.u.pnp.device) {
 	case W83627HF_HWM:
 		printk_debug("w83627hf hwm smbus enabled\n");
 		enable_hwm_smbus(dev);
 		break;
 	}
-        pnp_exit_ext_func_mode(dev);  
+	pnp_exit_ext_func_mode(dev);
 
 }
 
 void w83627hf_pnp_enable(device_t dev)
 {
 
-        if (!dev->enabled) {
-                pnp_enter_ext_func_mode(dev);   
+	if (!dev->enabled) {
+		pnp_enter_ext_func_mode(dev);
 
-                pnp_set_logical_device(dev);
-                pnp_set_enable(dev, 0);
+		pnp_set_logical_device(dev);
+		pnp_set_enable(dev, 0);
 
-                pnp_exit_ext_func_mode(dev);  
-        }
+		pnp_exit_ext_func_mode(dev);
+	}
 }
 
 static struct device_operations ops = {
@@ -173,18 +173,18 @@
 };
 
 static struct pnp_info pnp_dev_info[] = {
-        { &ops, W83627HF_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-        { &ops, W83627HF_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-        { &ops, W83627HF_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-        { &ops, W83627HF_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-        // No 4 { 0,},
-        { &ops, W83627HF_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
-        { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-        { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
-        { &ops, W83627HF_GPIO2, },
-        { &ops, W83627HF_GPIO3, },
-        { &ops, W83627HF_ACPI, },
-        { &ops, W83627HF_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
+	{ &ops, W83627HF_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &ops, W83627HF_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &ops, W83627HF_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, W83627HF_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	// No 4 { 0,},
+	{ &ops, W83627HF_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+	{ &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
+	{ &ops, W83627HF_GPIO2, },
+	{ &ops, W83627HF_GPIO3, },
+	{ &ops, W83627HF_ACPI, },
+	{ &ops, W83627HF_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
 };
 
 static void enable_dev(struct device *dev)

Modified: trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf.h
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf.h	2008-10-02 19:20:22 UTC (rev 3632)
+++ trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf.h	2008-10-02 19:21:30 UTC (rev 3633)
@@ -18,10 +18,10 @@
 #define W83627HF_GPEVR		0xf2
 #define W83627HF_GPCFG2		0xf3
 #define W83627HF_EXTCFG		0xf4
-#define W83627HF_IOEXT1A		0xf5
-#define W83627HF_IOEXT1B		0xf6
-#define W83627HF_IOEXT2A		0xf7
-#define W83627HF_IOEXT2B		0xf8
+#define W83627HF_IOEXT1A	0xf5
+#define W83627HF_IOEXT1B	0xf6
+#define W83627HF_IOEXT2A	0xf7
+#define W83627HF_IOEXT2B	0xf8
 
 #define W83627HF_GPDO_0		0x00
 #define W83627HF_GPDI_0		0x01
@@ -40,26 +40,26 @@
 #define W83627HF_GPDO_5		0x0e
 #define W83627HF_GPDI_5		0x0f
 #define W83627HF_GPDO_6		0x10
-#define W83627HF_GPDO_7A		0x11
-#define W83627HF_GPDO_7B		0x12
-#define W83627HF_GPDO_7C		0x13
-#define W83627HF_GPDO_7D		0x14
-#define W83627HF_GPDI_7A		0x15
-#define W83627HF_GPDI_7B		0x16
-#define W83627HF_GPDI_7C		0x17
-#define W83627HF_GPDI_7D		0x18
+#define W83627HF_GPDO_7A	0x11
+#define W83627HF_GPDO_7B	0x12
+#define W83627HF_GPDO_7C	0x13
+#define W83627HF_GPDO_7D	0x14
+#define W83627HF_GPDI_7A	0x15
+#define W83627HF_GPDI_7B	0x16
+#define W83627HF_GPDI_7C	0x17
+#define W83627HF_GPDI_7D	0x18
 
 #define W83627HF_XIOCNF		0xf0
-#define W83627HF_XIOBA1H		0xf1
-#define W83627HF_XIOBA1L		0xf2
+#define W83627HF_XIOBA1H	0xf1
+#define W83627HF_XIOBA1L	0xf2
 #define W83627HF_XIOSIZE1	0xf3
-#define W83627HF_XIOBA2H		0xf4
-#define W83627HF_XIOBA2L		0xf5
+#define W83627HF_XIOBA2H	0xf4
+#define W83627HF_XIOBA2L	0xf5
 #define W83627HF_XIOSIZE2	0xf6
 #define W83627HF_XMEMCNF1	0xf7
 #define W83627HF_XMEMCNF2	0xf8
-#define W83627HF_XMEMBAH		0xf9
-#define W83627HF_XMEMBAL		0xfa
+#define W83627HF_XMEMBAH	0xf9
+#define W83627HF_XMEMBAL	0xfa
 #define W83627HF_XMEMSIZE	0xfb
 #define W83627HF_XIRQMAP1	0xfc
 #define W83627HF_XIRQMAP2	0xfd

Modified: trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf_early_serial.c
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf_early_serial.c	2008-10-02 19:20:22 UTC (rev 3632)
+++ trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf_early_serial.c	2008-10-02 19:21:30 UTC (rev 3633)
@@ -1,17 +1,19 @@
 #include <arch/romcc_io.h>
 #include "w83627hf.h"
 
-static inline void pnp_enter_ext_func_mode(device_t dev) 
+static inline void pnp_enter_ext_func_mode(device_t dev)
 {
 	unsigned port = dev>>8;
-        outb(0x87, port);
-        outb(0x87, port);
+	outb(0x87, port);
+	outb(0x87, port);
 }
-static void pnp_exit_ext_func_mode(device_t dev) 
+
+static void pnp_exit_ext_func_mode(device_t dev)
 {
 	unsigned port = dev>>8;
-        outb(0xaa, port);
+	outb(0xaa, port);
 }
+
 static void w83627hf_enable_serial(device_t dev, unsigned iobase)
 {
 	pnp_enter_ext_func_mode(dev);




From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  2 21:37:03 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 02 Oct 2008 21:37:03 +0200
Subject: [coreboot] r3631 -
	trunk/coreboot-v2/src/southbridge/nvidia/ck804
In-Reply-To: <20081002181937.672gmx1@mx018.gmx.net>
References: <20081002181937.672gmx1@mx018.gmx.net>
Message-ID: <48E522DF.70701@gmx.net>

Hi Uwe,

thanks for cleaning up the codeing style.
However, it seems that indent also did some readability damage. Could
you perhaps fix up these places?
Review follows.

Regards,
Carl-Daniel


On 02.10.2008 20:19, svn at coreboot.org wrote:
> Author: uwe
> Date: 2008-10-02 20:19:17 +0200 (Thu, 02 Oct 2008)
> New Revision: 3631
>
> Log:
> CK804 coding-style fixed based on an 'indent' run (trivial).
>
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
> Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
>
>
>
> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -1,8 +1,7 @@
>  #ifndef CK804_CHIP_H
>  #define CK804_CHIP_H
>  
> -struct southbridge_nvidia_ck804_config
> -{
> +struct southbridge_nvidia_ck804_config {
>  	unsigned int usb1_hc_reset : 1;
>  	unsigned int ide0_enable : 1;
>  	unsigned int ide1_enable : 1;
> @@ -16,4 +15,4 @@
>  struct chip_operations;
>  extern struct chip_operations southbridge_nvidia_ck804_ops;
>  
> -#endif /* CK804_CHIP_H */
> +#endif
>   

Was the change above intentional?


> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -4,9 +4,7 @@
>   */
>  
>  #include <console/console.h>
> -
>  #include <arch/io.h>
> -
>  #include <device/device.h>
>  #include <device/pci.h>
>  #include <device/pci_ids.h>
> @@ -15,178 +13,167 @@
>  
>  static uint32_t final_reg;
>  
> -static device_t find_lpc_dev( device_t dev,  unsigned devfn) 
> +static device_t find_lpc_dev(device_t dev, unsigned devfn)
>  {
> -
>  	device_t lpc_dev;
>  
> -        lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
> +	lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
> +	if (!lpc_dev)
> +		return lpc_dev;
>  
> -        if ( !lpc_dev ) return lpc_dev;
> +	if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA)
> +		|| ((lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC)
> +		&& (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO)
> +		&& (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE)))
> +	{
> +		uint32_t id;
> +		id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
> +		if ((id != (PCI_VENDOR_ID_NVIDIA |
> +		      (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16)))
> +		    && (id != (PCI_VENDOR_ID_NVIDIA |
> +			 (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16)))
> +		    && (id != (PCI_VENDOR_ID_NVIDIA |
> +			 (PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16))))
> +		{
> +			lpc_dev = 0;
> +		}
> +	}
>  
> -        if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || (
> -		(lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC) &&
> -                (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO) &&
> -                (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE)) ) {
> -                	uint32_t id;
> -                        id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
> -                        if ( (id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) &&
> -                        	(id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16))) &&
> -				(id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16)))
> -				) {
> -                               lpc_dev = 0;
> -        		}
> -        }
> -
>  	return lpc_dev;
>  }
>  
>  void ck804_enable(device_t dev)
>  {
>  	device_t lpc_dev;
> -	unsigned index = 0;
> -	unsigned index2 = 0;
> +	unsigned index = 0, index2 = 0, deviceid, vendorid, devfn;
>   

Confusing, see also below.

>  	uint32_t reg_old, reg;
>  	uint8_t byte;
> -	unsigned deviceid;
> -	unsigned vendorid;
>  
> -        struct southbridge_nvidia_ck804_config *conf;
> -        conf = dev->chip_info;
> +	struct southbridge_nvidia_ck804_config *conf;
> +	conf = dev->chip_info;
>  
> -	unsigned devfn;
> -
> -	if(dev->device==0x0000) {
> +	if (dev->device == 0x0000) {
>  		vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
> -		deviceid = (vendorid>>16) & 0xffff;
> -//		vendorid &= 0xffff;
> +		deviceid = (vendorid >> 16) & 0xffff;
> +		/* vendorid &= 0xffff; */
>  	} else {
> -//		vendorid = dev->vendor;
> +		/* vendorid = dev->vendor; */
>  		deviceid = dev->device;
>  	}
>  
>  	devfn = (dev->path.u.pci.devfn) & ~7;
> -	switch(deviceid) {
> -		case PCI_DEVICE_ID_NVIDIA_CK804_SM:
> -			index = 16;
> -			break;
> -		case PCI_DEVICE_ID_NVIDIA_CK804_USB:
> -			devfn -= (1<<3);
> -			index = 8;
> -			break;
> -                case PCI_DEVICE_ID_NVIDIA_CK804_USB2:
> -                        devfn -= (1<<3);
> -                        index = 20;
> -                        break;
> -                case PCI_DEVICE_ID_NVIDIA_CK804_NIC:
> -                        devfn -= (9<<3);
> -                        index = 10;
> -			dev->rom_address = conf->nic_rom_address;
> -                        break;
> -                case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE:
> -                        devfn -= (9<<3);
> -                        index = 10;
> -                        dev->rom_address = conf->nic_rom_address;
> -                        break;
> -                case PCI_DEVICE_ID_NVIDIA_CK804_ACI:
> -                        devfn -= (3<<3);
> -                        index = 12;
> -                        break;
> -                case PCI_DEVICE_ID_NVIDIA_CK804_MCI:
> -                        devfn -= (3<<3);
> -                        index = 13;
> -                        break;
> -                case PCI_DEVICE_ID_NVIDIA_CK804_IDE:
> -                        devfn -= (5<<3);
> -                        index = 14;
> -			dev->rom_address = conf->raid_rom_address;
> -                        break;
> -                case PCI_DEVICE_ID_NVIDIA_CK804_SATA0:
> -                        devfn -= (6<<3);
> -                        index = 22;
> -                        break;
> -                case PCI_DEVICE_ID_NVIDIA_CK804_SATA1:
> -                        devfn -= (7<<3);
> -                        index = 18;
> -                        break;
> -                case PCI_DEVICE_ID_NVIDIA_CK804_PCI:
> -                        devfn -= (8<<3);
> -                        index = 15;
> -                        break;
> -		case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E:
> -			devfn -= (0xa<<3);
> -			index2 = 19;
> -			break;
> -		default:
> -			index = 0;
> +	switch (deviceid) {
> +	case PCI_DEVICE_ID_NVIDIA_CK804_SM:
> +		index = 16;
> +		break;
> +	case PCI_DEVICE_ID_NVIDIA_CK804_USB:
> +		devfn -= (1 << 3);
> +		index = 8;
> +		break;
> +	case PCI_DEVICE_ID_NVIDIA_CK804_USB2:
> +		devfn -= (1 << 3);
> +		index = 20;
> +		break;
> +	case PCI_DEVICE_ID_NVIDIA_CK804_NIC:
> +		devfn -= (9 << 3);
> +		index = 10;
> +		dev->rom_address = conf->nic_rom_address;
> +		break;
> +	case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE:
> +		devfn -= (9 << 3);
> +		index = 10;
> +		dev->rom_address = conf->nic_rom_address;
> +		break;
> +	case PCI_DEVICE_ID_NVIDIA_CK804_ACI:
> +		devfn -= (3 << 3);
> +		index = 12;
> +		break;
> +	case PCI_DEVICE_ID_NVIDIA_CK804_MCI:
> +		devfn -= (3 << 3);
> +		index = 13;
> +		break;
> +	case PCI_DEVICE_ID_NVIDIA_CK804_IDE:
> +		devfn -= (5 << 3);
> +		index = 14;
> +		dev->rom_address = conf->raid_rom_address;
> +		break;
> +	case PCI_DEVICE_ID_NVIDIA_CK804_SATA0:
> +		devfn -= (6 << 3);
> +		index = 22;
> +		break;
> +	case PCI_DEVICE_ID_NVIDIA_CK804_SATA1:
> +		devfn -= (7 << 3);
> +		index = 18;
> +		break;
> +	case PCI_DEVICE_ID_NVIDIA_CK804_PCI:
> +		devfn -= (8 << 3);
> +		index = 15;
> +		break;
> +	case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E:
> +		devfn -= (0xa << 3);
> +		index2 = 19;
> +		break;
> +	default:
> +		index = 0;
>  	}
>  
> -	if(index2!=0) {
> +	if (index2 != 0) {
>  		int i;
> -		for(i=0;i<4;i++) {
> -			lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
> -			if(!lpc_dev) continue;
> +		for (i = 0; i < 4; i++) {
> +			lpc_dev = find_lpc_dev(dev, devfn - (i << 3));
> +			if (!lpc_dev)
> +				continue;
>  			index2 -= i;
>  			break;
>  		}
>  
> -		if ( lpc_dev ) {
> -	                reg_old = reg =  pci_read_config32(lpc_dev, 0xe4);
> -
> -			if (!dev->enabled) { 
> -				reg |= (1<<index2);
> -			}
> -
> -                	if (reg != reg_old) {
> -                        	pci_write_config32(lpc_dev, 0xe4, reg);
> -                	}
> +		if (lpc_dev) {
> +			reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
> +			if (!dev->enabled)
> +				reg |= (1 << index2);
> +			if (reg != reg_old)
> +				pci_write_config32(lpc_dev, 0xe4, reg);
>  		}
>  
>  		index2 = 0;
>  		return;
>  	}
>  
> -
>  	lpc_dev = find_lpc_dev(dev, devfn);
> +	if (!lpc_dev)
> +		return;
>  
> -	if ( !lpc_dev )	return; 
> -
> -        if ( index == 0) {
> -
> +	if (index == 0) {
>  		final_reg = pci_read_config32(lpc_dev, 0xe8);
> -		final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<10)|(1<<12)|(1<<13)|(1<<14)|(1<<22)|(1<<18)|(1<<15));
> -		pci_write_config32(lpc_dev, 0xe8, final_reg); 
> +		final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 10)
> +			| (1 << 12) | (1 << 13) | (1 << 14) | (1 << 22)
> +			| (1 << 18) | (1 << 15));
> +		pci_write_config32(lpc_dev, 0xe8, final_reg);
>  
> -                reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
> -                reg |= (1<<20);
> -                if (reg != reg_old) {
> -                        pci_write_config32(lpc_dev, 0xe4, reg);
> -                }
> +		reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
> +		reg |= (1 << 20);
> +		if (reg != reg_old)
> +			pci_write_config32(lpc_dev, 0xe4, reg);
>  
> -                byte = pci_read_config8(lpc_dev, 0x74);
> -                byte |= ((1<<1)); 
> -                pci_write_config8(dev, 0x74, byte);
> +		byte = pci_read_config8(lpc_dev, 0x74);
> +		byte |= ((1 << 1));
> +		pci_write_config8(dev, 0x74, byte);
>  
> -                byte = pci_read_config8(lpc_dev, 0xdd);
> -                byte |= ((1<<0)|(1<<3)); 
> -                pci_write_config8(dev, 0xdd, byte);
> +		byte = pci_read_config8(lpc_dev, 0xdd);
> +		byte |= ((1 << 0) | (1 << 3));
> +		pci_write_config8(dev, 0xdd, byte);
>  
>  		return;
> +	}
>  
> -        }
> +	if (!dev->enabled)
> +		final_reg |= (1 << index);
>  
> -	if (!dev->enabled) {
> -                final_reg |= (1 << index);
> -        }
> -
> -	if(index == 10 ) { 
> +	if (index == 10) {
>  		reg_old = pci_read_config32(lpc_dev, 0xe8);
> -        	if (final_reg != reg_old) {
> -                	pci_write_config32(lpc_dev, 0xe8, final_reg);
> -        	}
> -
> +		if (final_reg != reg_old)
> +			pci_write_config32(lpc_dev, 0xe8, final_reg);
>  	}
> -
>  }
>  
>  struct chip_operations southbridge_nvidia_ck804_ops = {
>
> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -5,4 +5,4 @@
>  
>  void ck804_enable(device_t dev);
>  
> -#endif /* CK804_H */
> +#endif
>   

Comment removal.

> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -2,6 +2,7 @@
>   * Copyright 2004 Tyan Computer
>   *  by yhlu at tyan.com
>   */
> +
>  #include <console/console.h>
>  #include <device/device.h>
>  #include <device/pci.h>
> @@ -11,19 +12,19 @@
>  
>  static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
>  {
> -        pci_write_config32(dev, 0x40,
> -                ((device & 0xffff) << 16) | (vendor & 0xffff));
> +	pci_write_config32(dev, 0x40,
> +			   ((device & 0xffff) << 16) | (vendor & 0xffff));
>  }
>  
>  static struct pci_operations lops_pci = {
> -        .set_subsystem = lpci_set_subsystem,
> +	.set_subsystem = lpci_set_subsystem,
>  };
>  
> -static struct device_operations ac97audio_ops  = {
> +static struct device_operations ac97audio_ops = {
>  	.read_resources   = pci_dev_read_resources,
>  	.set_resources    = pci_dev_set_resources,
>  	.enable_resources = pci_dev_enable_resources,
> -//	.enable           = ck804_enable,
> +	// .enable        = ck804_enable,
>   

This actually kills readable indentation.

>  	.init             = 0,
>  	.scan_bus         = 0,
>  	.ops_pci          = &lops_pci,
> @@ -35,12 +36,11 @@
>  	.device = PCI_DEVICE_ID_NVIDIA_CK804_ACI,
>  };
>  
> -
> -static struct device_operations ac97modem_ops  = {
> +static struct device_operations ac97modem_ops = {
>  	.read_resources   = pci_dev_read_resources,
>  	.set_resources    = pci_dev_set_resources,
>  	.enable_resources = pci_dev_enable_resources,
> -//	.enable           = ck804_enable,
> +	// .enable        = ck804_enable,
>   

Same here.

>  	.init             = 0,
>  	.scan_bus         = 0,
>  	.ops_pci          = &lops_pci,
>
> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -2,6 +2,7 @@
>   * Copyright 2004 Tyan Computer
>   *  by yhlu at tyan.com
>   */
> +
>  static int set_ht_link_ck804(uint8_t ht_c_num)
>  {
>  	unsigned vendorid = 0x10de;
> @@ -9,10 +10,10 @@
>  	return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
>  }
>  
> -static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
> +static void setup_ss_table(unsigned index, unsigned where, unsigned control,
> +			   const unsigned int *register_values, int max)
>  {
>  	int i;
> -
>  	unsigned val;
>  
>  	val = inl(control);
> @@ -21,7 +22,7 @@
>  
>  	outl(0, index);
>  
> -	for(i = 0; i < max; i++) {
> +	for (i = 0; i < max; i++) {
>  		unsigned long reg;
>  		reg = register_values[i];
>  		outl(reg, where);
> @@ -29,67 +30,61 @@
>  	val = inl(control);
>  	val |= 1;
>  	outl(val, control);
> -
>  }
>  
>  #define ANACTRL_IO_BASE 0x7000
>  #define ANACTRL_REG_POS 0x68
>  
> -
>  #define SYSCTRL_IO_BASE 0x6000
>  #define SYSCTRL_REG_POS 0x64
>  
>  /*
> -	16 1 1 2 :0
> -	 8 8 2 2 :1
> -	 8 8 4   :2
> -	 8 4 4 4 :3
> -	16 4     :4
> + *	16 1 1 2 :0
> + *	 8 8 2 2 :1
> + *	 8 8 4   :2
> + *	 8 4 4 4 :3
> + *	16 4     :4
>  */
>  
>  #ifndef CK804_PCI_E_X
> -	#define CK804_PCI_E_X 4
> +#define CK804_PCI_E_X 4
>  #endif
>  
>  #if CK804_NUM > 1
> -	#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE+0x8000)
> -	#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE+0x8000)
> -
> -	#ifndef CK804B_BUSN
> -		#define CK804B_BUSN 0x80
> -	#endif
> -
> -	#ifndef CK804B_PCI_E_X
> -		#define CK804B_PCI_E_X 4
> -	#endif
> +#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000)
> +#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000)
> +#ifndef CK804B_BUSN
> +#define CK804B_BUSN 0x80
>  #endif
> +#ifndef CK804B_PCI_E_X
> +#define CK804B_PCI_E_X 4
> +#endif
> +#endif
>  
>  #ifndef CK804_USE_NIC
> -	#define CK804_USE_NIC 0
> +#define CK804_USE_NIC 0
>  #endif
>  
>  #ifndef CK804_USE_ACI
> -	#define CK804_USE_ACI 0
> +#define CK804_USE_ACI 0
>  #endif
>  
>  #define CK804_CHIP_REV 3
>  
>  #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
> -	#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
> +#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
>  #else
> -	#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
> +#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
>  #endif
>  
>  #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
> -	#define CK804B_DEVN_BASE 1
> +#define CK804B_DEVN_BASE 1
>  #else
> -	#define CK804B_DEVN_BASE CK804_DEVN_BASE
> +#define CK804B_DEVN_BASE CK804_DEVN_BASE
>  #endif
>  
> -
>  static void ck804_early_set_port(void)
>  {
> -
>  	static const unsigned int ctrl_devport_conf[] = {
>  		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
>  #if CK804_NUM > 1
> @@ -103,12 +98,10 @@
>  	};
>  
>  	setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf));
> -
>  }
>  
>  static void ck804_early_clear_port(void)
>  {
> -
>  	static const unsigned int ctrl_devport_conf_clear[] = {
>  		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
>  #if CK804_NUM > 1
> @@ -122,84 +115,70 @@
>  	};
>  
>  	setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear));
> -
>  }
>  
>  static void ck804_early_setup(void)
>  {
> -
>  	static const unsigned int ctrl_conf[] = {
>  
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000,
>  
> -
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,
> -
> -
>  #if CK804_NUM > 1
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
>  #endif
>  
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,
>  
> -
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
> -
> -
>  #if CK804_NUM > 1
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,
>  #endif
>  
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,
>  
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
> -	RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
> -
>  #if CK804_NUM > 1
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
> -	RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,
>  #endif
>  
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,
>  
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
> -
>  #if CK804_NUM > 1
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,
>  #endif
>  
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100,
>  
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
> -
> -
> -
>  #if CK804_NUM > 1
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff,
>  #endif
>  
> -
>  	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
>  	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
>  	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
> @@ -208,139 +187,125 @@
>  	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
>  
>  	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32),
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16),
> +	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32),
> +	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16),
>  
>  #if CK804_NUM > 1
> -
>  	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
>  	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
>  	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
>  	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
>  	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
>  	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
> -
>  #endif
>  
> -
>  	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
>  #if CK804_NUM > 1
>  	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
>  #endif
>  
> -	// Activate master port on primary SATA controller
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x50), ~(0x1f000013), 0x15000013,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x64), ~(0x00000001), 0x00000001,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x68), ~(0x02000000), 0x02000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x70), ~(0x000f0000), 0x00040000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xa0), ~(0x000001ff), 0x00000150,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x7c), ~(0x00000010), 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xd0), ~(0xf0000000), 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xe0), ~(0xf0000000), 0x00000000,
> +	/* Activate master port on primary SATA controller. */
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x50), ~(0x1f000013), 0x15000013,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x64), ~(0x00000001), 0x00000001,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x68), ~(0x02000000), 0x02000000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x70), ~(0x000f0000), 0x00040000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xa0), ~(0x000001ff), 0x00000150,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0x7c), ~(0x00000010), 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xd0), ~(0xf0000000), 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 7, 0, 0xe0), ~(0xf0000000), 0x00000000,
>  
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,
>  #if  CK804_NUM > 1
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
> -
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,
>  #endif
>  
> -
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
> +	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
>  #if CK804_NUM > 1
> -	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
> +	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
>  #endif
>  
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
> +	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
>  #if CK804_NUM > 1
> -	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
> +	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
>  #endif
>  
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
> +	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
>  
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8),
> +	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),
>  #if CK804_NUM > 1
> -	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8),
> +	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
>  #endif
>  
> -
> -
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
> +	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
> +	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
>  #if CK804_USE_NIC == 1
> -	RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
> +	RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
> +	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
> +	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
> +	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23),
>  #endif
>  
>  #if CK804_USE_ACI == 1
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
> +	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
> +	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
>  #endif
>  
>  #if CK804_NUM > 1
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
> +	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2),
>  #endif
>  
> -
>  #if CK804_NUM > 1
> -	#if CK804_USE_NIC == 1
> -		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
> -		RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
> -		RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
> -		RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
> -		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
> -	#endif
> +#if CK804_USE_NIC == 1
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
> +	RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
> +	RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
> +	RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
> +	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23),
>  #endif
> +#endif
>  
> -
> -
>  #ifdef CK804_MB_SETUP
>  	CK804_MB_SETUP
>  #endif
> -
>  	};
>  
> -
> -
>  	setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf));
>  
> -	setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
> -	setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
> -	setup_ss_table(ANACTRL_IO_BASE+0xc0, ANACTRL_IO_BASE+0xc4, ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
> +	setup_ss_table(ANACTRL_IO_BASE + 0x40, ANACTRL_IO_BASE + 0x44, ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64);
> +	setup_ss_table(ANACTRL_IO_BASE + 0xb0, ANACTRL_IO_BASE + 0xb4, ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64);
> +	setup_ss_table(ANACTRL_IO_BASE + 0xc0, ANACTRL_IO_BASE + 0xc4, ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64);
>  
>  #if CK804_NUM > 1
> -	setup_ss_table(CK804B_ANACTRL_IO_BASE+0x40, CK804B_ANACTRL_IO_BASE+0x44, CK804B_ANACTRL_IO_BASE+0x48, pcie_ss_tbl,64);
> -	setup_ss_table(CK804B_ANACTRL_IO_BASE+0xb0, CK804B_ANACTRL_IO_BASE+0xb4, CK804B_ANACTRL_IO_BASE+0xb8, sata_ss_tbl,64);
> -	setup_ss_table(CK804B_ANACTRL_IO_BASE+0xc0, CK804B_ANACTRL_IO_BASE+0xc4, CK804B_ANACTRL_IO_BASE+0xc8, cpu_ss_tbl,64);
> +	setup_ss_table(CK804B_ANACTRL_IO_BASE + 0x40, CK804B_ANACTRL_IO_BASE + 0x44, CK804B_ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64);
> +	setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xb0, CK804B_ANACTRL_IO_BASE + 0xb4, CK804B_ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64);
> +	setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64);
>  #endif
>  
>  #if 0
>  	dump_io_resources(ANACTRL_IO_BASE);
>  	dump_io_resources(SYSCTRL_IO_BASE);
>  #endif
> -
>  }
>  
>  static int ck804_early_setup_x(void)
> @@ -369,4 +334,3 @@
>  	outb(0x06, 0x0cf9);
>  #endif
>  }
> -
>
> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -11,365 +11,339 @@
>  	return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
>  }
>  
> -static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
> +static void setup_ss_table(unsigned index, unsigned where, unsigned control,
> +			   const unsigned int *register_values, int max)
>  {
>  	int i;
> -
>  	unsigned val;
> +
>  	val = inl(control);
>  	val &= 0xfffffffe;
>  	outl(val, control);
>  
>  	outl(0, index);
>  
> -	for(i = 0; i < max; i++) {
> +	for (i = 0; i < max; i++) {
>  		unsigned long reg;
> -
>  		reg = register_values[i];
>  		outl(reg, where);
>  	}
> +
>  	val = inl(control);
>  	val |= 1;
>  	outl(val, control);
> -
>  }
>  
>  #define ANACTRL_IO_BASE 0x3000
>  #define ANACTRL_REG_POS 0x68
>  
> -
>  #define SYSCTRL_IO_BASE 0x2000
>  #define SYSCTRL_REG_POS 0x64
>  
>  /*
> -	16 1 1 2 :0
> -	 8 8 2 2 :1
> -	 8 8 4   :2
> -	 8 4 4 4 :3
> -	16 4     :4
> + *	16 1 1 2 :0
> + *	 8 8 2 2 :1
> + *	 8 8 4   :2
> + *	 8 4 4 4 :3
> + *	16 4     :4
>  */
>  
>  #ifndef CK804_PCI_E_X
> -	#define CK804_PCI_E_X 4
> +#define CK804_PCI_E_X 4
>  #endif
>  
> -	/* we will use the offset in setup_resource_map_x_offset and setup_resource_map_offset */
> -	#define CK804B_ANACTRL_IO_BASE 0x3000
> -	#define CK804B_SYSCTRL_IO_BASE 0x2000
> +/*
> + * We will use the offset in setup_resource_map_x_offset and
> + * setup_resource_map_offset.
> + */
> +#define CK804B_ANACTRL_IO_BASE 0x3000
> +#define CK804B_SYSCTRL_IO_BASE 0x2000
>  
> -	#ifdef CK804B_BUSN
> -		#undef CK804B_BUSN
> -	#endif
> -	#define CK804B_BUSN 0x0
> +#ifdef CK804B_BUSN
> +#undef CK804B_BUSN
> +#endif
> +#define CK804B_BUSN 0x0
>  
> -	#ifndef CK804B_PCI_E_X
> -		#define CK804B_PCI_E_X 4
> -	#endif
> +#ifndef CK804B_PCI_E_X
> +#define CK804B_PCI_E_X 4
> +#endif
>  
>  #ifndef CK804_USE_NIC
> -	#define CK804_USE_NIC 0
> +#define CK804_USE_NIC 0
>  #endif
>  
>  #ifndef CK804_USE_ACI
> -	#define CK804_USE_ACI 0
> +#define CK804_USE_ACI 0
>  #endif
>  
>  #define CK804_CHIP_REV 3
>  
>  #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
> -	#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
> +#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
>  #else
> -	#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
> +#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
>  #endif
>  
>  #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
> -	#define CK804B_DEVN_BASE 1
> +#define CK804B_DEVN_BASE 1
>  #else
> -	#define CK804B_DEVN_BASE CK804_DEVN_BASE
> +#define CK804B_DEVN_BASE CK804_DEVN_BASE
>  #endif
>  
> -static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, unsigned *io_base)
> +static void ck804_early_set_port(unsigned ck804_num, unsigned *busn,
> +				 unsigned *io_base)
>  {
> -
>  	static const unsigned int ctrl_devport_conf[] = {
> -		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
> -		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
> +		PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
> +		PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
>  	};
>  
>  	static const unsigned int ctrl_devport_conf_b[] = {
> -		PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
> -		PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
> +		PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
> +		PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
>  	};
>  
>  	int j;
> -	for(j = 0; j < ck804_num; j++ ) {
> -		if(busn[j]==0) { //sb chain
> +	for (j = 0; j < ck804_num; j++) {
> +		if (busn[j] == 0) {	//sb chain
>  			setup_resource_map_offset(ctrl_devport_conf,
>  				ARRAY_SIZE(ctrl_devport_conf),
> -				PCI_DEV(busn[j], 0, 0) , io_base[j]);
> +				PCI_DEV(busn[j], 0, 0), io_base[j]);
>  			continue;
>  		}
>  		setup_resource_map_offset(ctrl_devport_conf_b,
> -			ARRAY_SIZE(ctrl_devport_conf_b),
> -			PCI_DEV(busn[j], 0, 0) , io_base[j]);
> +					  ARRAY_SIZE(ctrl_devport_conf_b),
> +					  PCI_DEV(busn[j], 0, 0), io_base[j]);
>  	}
>  }
>  
> -static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, unsigned *io_base)
> +static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn,
> +				   unsigned *io_base)
>  {
> -
>  	static const unsigned int ctrl_devport_conf_clear[] = {
> -		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
> -		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
> +		PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
> +		PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
>  	};
>  
>  	static const unsigned int ctrl_devport_conf_clear_b[] = {
> -		PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
> -		PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
> +		PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
> +		PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
>  	};
>  
>  	int j;
> -	for(j = 0; j < ck804_num; j++ ) {
> -		if(busn[j]==0) { //sb chain
> +	for (j = 0; j < ck804_num; j++) {
> +		if (busn[j] == 0) {	//sb chain
>  			setup_resource_map_offset(ctrl_devport_conf_clear,
>  				ARRAY_SIZE(ctrl_devport_conf_clear),
> -				PCI_DEV(busn[j], 0, 0) , io_base[j]);
> +				PCI_DEV(busn[j], 0, 0), io_base[j]);
>  			continue;
>  		}
>  		setup_resource_map_offset(ctrl_devport_conf_clear_b,
> -			ARRAY_SIZE(ctrl_devport_conf_clear_b),
> -			PCI_DEV(busn[j], 0, 0) , io_base[j]);
> +					  ARRAY_SIZE(ctrl_devport_conf_clear_b),
> +					  PCI_DEV(busn[j], 0, 0), io_base[j]);
>  	}
> -
> -
>  }
>  
> -
> -static void ck804_early_setup(unsigned ck804_num, unsigned *busn, unsigned *io_base)
> +static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
> +			      unsigned *io_base)
>  {
> -
>  	static const unsigned int ctrl_conf_master[] = {
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000,
>  
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,
>  
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,
>  
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,
>  
> -
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
> -	RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
> -
> -
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
> -
> -
>  #ifdef CK804_MB_SETUP
> -	CK804_MB_SETUP
> +		CK804_MB_SETUP
>  #endif
> -
> -
>  #if CK804_NUM > 1
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
> -
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100,
>  #endif
>  
>  #if CK804_NUM == 1
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
> -
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100,
>  #endif
>  
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
> +		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
> +		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
> +		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
> +		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
> +		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
> +		RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
>  
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32),
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16),
> +		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,
> +		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32),
> +		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16),
>  
> +		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
>  
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,
>  
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
> +		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
>  
> +// PANTA	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
>  
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
> +		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
>  
> -//PANTA		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
> +		RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),
>  
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
> -
> -	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8),
> -
> -
>  //SYSCTRL
> -
> -
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
> +		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
> +		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
>  #if CK804_USE_NIC == 1
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
> -	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
> +		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
> +		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
> +		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
> +		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23),
>  #endif
>  
>  #if CK804_USE_ACI == 1
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
> +		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
> +		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
>  #endif
>  
>  #if CK804_NUM > 1
> -	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
> +		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2),
>  #endif
> -
> -
>  	};
>  
> -
> -
> -
>  	static const unsigned int ctrl_conf_slave[] = {
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
>  
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,
>  
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,
>  
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,
>  
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff,
>  
> +		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
> +		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
> +		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
> +		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
> +		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
> +		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
>  
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
> -	RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
> +		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
>  
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,
>  
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,
> +		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
>  
> -	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
> -	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
> -	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
> -	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
> -	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
> -	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
> +//PANTA		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
>  
> -	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
> +		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
>  
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
> -	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
> +		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
>  
> -
> -	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
> -
> -//PANTA		RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
> -
> -	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
> -
> -	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8),
> -
> -	#if CK804_USE_NIC == 1
> -		RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
> -		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
> -		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
> -		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
> -		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
> -	#endif
> -
> +#if CK804_USE_NIC == 1
> +		RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE + 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
> +		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
> +		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
> +		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
> +		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23),
> +#endif
>  	};
>  
>  	int j;
> -
> -	for(j=0; j<ck804_num; j++) {
> -		if(busn[j] == 0) {
> -			setup_resource_map_x_offset(ctrl_conf_master, ARRAY_SIZE(ctrl_conf_master),
> -				PCI_DEV(busn[0],0,0), io_base[0]);
> +	for (j = 0; j < ck804_num; j++) {
> +		if (busn[j] == 0) {
> +			setup_resource_map_x_offset(ctrl_conf_master,
> +				ARRAY_SIZE(ctrl_conf_master),
> +				PCI_DEV(busn[0], 0, 0), io_base[0]);
>  			continue;
>  		}
>  
> -
> -		setup_resource_map_x_offset(ctrl_conf_slave, ARRAY_SIZE(ctrl_conf_slave),
> -			PCI_DEV(busn[j],0,0), io_base[j]);
> +		setup_resource_map_x_offset(ctrl_conf_slave,
> +					    ARRAY_SIZE(ctrl_conf_slave),
> +					    PCI_DEV(busn[j], 0, 0), io_base[j]);
>  	}
>  
> -	for(j=0; j< ck804_num; j++) {
> -		// PCI-E (XSPLL) SS table 0x40, x044, 0x48
> -		// SATA  (SPPLL) SS table 0xb0, 0xb4, 0xb8
> -		// CPU   (PPLL)  SS table 0xc0, 0xc4, 0xc8
> -		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,
> -			io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
> -		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,
> -			io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
> -//PANTA		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
> -//			io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
> +	for (j = 0; j < ck804_num; j++) {
> +		/* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */
> +		/* SATA  (SPPLL) SS table 0xb0, 0xb4, 0xb8 */
> +		/* CPU   (PPLL)  SS table 0xc0, 0xc4, 0xc8 */
> +		setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40,
> +			       io_base[j] + ANACTRL_IO_BASE + 0x44,
> +			       io_base[j] + ANACTRL_IO_BASE + 0x48,
> +			       pcie_ss_tbl, 64);
> +		setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0,
> +			       io_base[j] + ANACTRL_IO_BASE + 0xb4,
> +			       io_base[j] + ANACTRL_IO_BASE + 0xb8,
> +			       sata_ss_tbl, 64);
> +//PANTA         setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0,
> +//			       io_base[j] + ANACTRL_IO_BASE + 0xc4,
> +//			       io_base[j] + ANACTRL_IO_BASE + 0xc8,
> +//			       cpu_ss_tbl, 64);
>  	}
> -
> -
>  }
>  
>  static int ck804_early_setup_x(void)
>  {
> -	unsigned busn[4];
> -	unsigned io_base[4];
> -	int ck804_num = 0;
> -	int i;
> +	unsigned busn[4], io_base[4];
> +	int i, ck804_num = 0;
>   

I know it is correct to do write code that way, but I wonder each time
if the code actually means i=0, ck804num=0.

>  
> -	for(i=0;i<4;i++) {
> +	for (i = 0; i < 4; i++) {
>  		uint32_t id;
>  		device_t dev;
> -		if(i == 0) { // SB chain
> -			dev = PCI_DEV(i*0x40, CK804_DEVN_BASE, 0);
> -		}
> -		else {
> -			dev = PCI_DEV(i*0x40, CK804B_DEVN_BASE, 0);
> -		}
> +		if (i == 0) // SB chain
> +			dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0);
> +		else
> +			dev = PCI_DEV(i * 0x40, CK804B_DEVN_BASE, 0);
>  		id = pci_read_config32(dev, PCI_VENDOR_ID);
> -		if(id == 0x005e10de) {
> +		if (id == 0x005e10de) {
>  			busn[ck804_num] = i * 0x40;
>  			io_base[ck804_num] = i * 0x4000;
>  			ck804_num++;
> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -13,61 +13,61 @@
>  static void ide_init(struct device *dev)
>  {
>  	struct southbridge_nvidia_ck804_config *conf;
> -	/* Enable ide devices so the linux ide driver will work */
>  	uint32_t dword;
>  	uint16_t word;
>  	uint8_t byte;
> +
>  	conf = dev->chip_info;
>  
>  	word = pci_read_config16(dev, 0x50);
> -	/* Ensure prefetch is disabled */
> +	/* Ensure prefetch is disabled. */
>  	word &= ~((1 << 15) | (1 << 13));
>  	if (conf->ide1_enable) {
> -		/* Enable secondary ide interface */
> -		word |= (1<<0);
> +		/* Enable secondary IDE interface. */
> +		word |= (1 << 0);
>  		printk_debug("IDE1 \t");
>  	}
>  	if (conf->ide0_enable) {
> -		/* Enable primary ide interface */
> -		word |= (1<<1);
> +		/* Enable primary IDE interface. */
> +		word |= (1 << 1);
>  		printk_debug("IDE0\n");
>  	}
>  
> -	word |= (1<<12);
> -	word |= (1<<14);
> +	word |= (1 << 12);
> +	word |= (1 << 14);
>  
>  	pci_write_config16(dev, 0x50, word);
>  
> -
> -	byte = 0x20 ; // Latency: 64-->32
> +	byte = 0x20;		/* Latency: 64 --> 32 */
>  	pci_write_config8(dev, 0xd, byte);
>  
>  	dword = pci_read_config32(dev, 0xf8);
>  	dword |= 12;
>  	pci_write_config32(dev, 0xf8, dword);
> +
>  #if CONFIG_PCI_ROM_RUN == 1
>  	pci_dev_init(dev);
>  #endif
> -
>  }
>  
>  static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
>  {
>  	pci_write_config32(dev, 0x40,
> -		((device & 0xffff) << 16) | (vendor & 0xffff));
> +			   ((device & 0xffff) << 16) | (vendor & 0xffff));
>  }
> +
>  static struct pci_operations lops_pci = {
>  	.set_subsystem = lpci_set_subsystem,
>  };
>  
> -static struct device_operations ide_ops  = {
> +static struct device_operations ide_ops = {
>  	.read_resources   = pci_dev_read_resources,
>  	.set_resources    = pci_dev_set_resources,
>  	.enable_resources = pci_dev_enable_resources,
> -	.init	     = ide_init,
> -	.scan_bus	 = 0,
> -//	.enable	   = ck804_enable,
> -	.ops_pci	  = &lops_pci,
> +	.init             = ide_init,
> +	.scan_bus         = 0,
> +	// .enable        = ck804_enable,
>   

Indentation was better before.


> +	.ops_pci          = &lops_pci,
>  };
>  
>  static const struct pci_driver ide_driver __pci_driver = {
> @@ -75,4 +75,3 @@
>  	.vendor = PCI_VENDOR_ID_NVIDIA,
>  	.device = PCI_DEVICE_ID_NVIDIA_CK804_IDE,
>  };
> -
>
> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -4,6 +4,7 @@
>   *  by yhlu at tyan.com
>   *  2006.1 yhlu add dest apicid for IRQ0
>   */
> +
>  #include <console/console.h>
>  #include <device/device.h>
>  #include <device/pci.h>
> @@ -44,30 +45,30 @@
>  #define INT		(1 << 8)
>  	/* IO-APIC virtual wire mode configuration */
>  	/* mask, trigger, polarity, destination, delivery, vector */
> -	{   0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
> -	{   1, DISABLED, NONE},
> -	{   2, DISABLED, NONE},
> -	{   3, DISABLED, NONE},
> -	{   4, DISABLED, NONE},
> -	{   5, DISABLED, NONE},
> -	{   6, DISABLED, NONE},
> -	{   7, DISABLED, NONE},
> -	{   8, DISABLED, NONE},
> -	{   9, DISABLED, NONE},
> -	{  10, DISABLED, NONE},
> -	{  11, DISABLED, NONE},
> -	{  12, DISABLED, NONE},
> -	{  13, DISABLED, NONE},
> -	{  14, DISABLED, NONE},
> -	{  15, DISABLED, NONE},
> -	{  16, DISABLED, NONE},
> -	{  17, DISABLED, NONE},
> -	{  18, DISABLED, NONE},
> -	{  19, DISABLED, NONE},
> -	{  20, DISABLED, NONE},
> -	{  21, DISABLED, NONE},
> -	{  22, DISABLED, NONE},
> -	{  23, DISABLED, NONE},
> +	{0,  ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
> +	{1,  DISABLED, NONE},
> +	{2,  DISABLED, NONE},
> +	{3,  DISABLED, NONE},
> +	{4,  DISABLED, NONE},
> +	{5,  DISABLED, NONE},
> +	{6,  DISABLED, NONE},
> +	{7,  DISABLED, NONE},
> +	{8,  DISABLED, NONE},
> +	{9,  DISABLED, NONE},
> +	{10, DISABLED, NONE},
> +	{11, DISABLED, NONE},
> +	{12, DISABLED, NONE},
> +	{13, DISABLED, NONE},
> +	{14, DISABLED, NONE},
> +	{15, DISABLED, NONE},
> +	{16, DISABLED, NONE},
> +	{17, DISABLED, NONE},
> +	{18, DISABLED, NONE},
> +	{19, DISABLED, NONE},
> +	{20, DISABLED, NONE},
> +	{21, DISABLED, NONE},
> +	{22, DISABLED, NONE},
> +	{23, DISABLED, NONE},
>  	/* Be careful and don't write past the end... */
>  };
>  
> @@ -75,23 +76,22 @@
>  {
>  	int i;
>  	unsigned long value_low, value_high;
> -//	unsigned long ioapic_base = 0xfec00000;
> +	/* unsigned long ioapic_base = 0xfec00000; */
>   

I don't get that change. Why did indent use another comment delimiter here?

>  	volatile unsigned long *l;
>  	struct ioapicreg *a = ioapicregvalues;
>  
> -	ioapicregvalues[0].value_high = lapicid()<<(56-32);
> +	ioapicregvalues[0].value_high = lapicid() << (56 - 32);
>  
> -	l = (unsigned long *) ioapic_base;
> +	l = (unsigned long *)ioapic_base;
>  
> -	for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
> -	     i++, a++) {
> +	for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) {
>  		l[0] = (a->reg * 2) + 0x10;
>  		l[4] = a->value_low;
>  		value_low = l[4];
> -		l[0] = (a->reg *2) + 0x11;
> +		l[0] = (a->reg * 2) + 0x11;
>  		l[4] = a->value_high;
>  		value_high = l[4];
> -		if ((i==0) && (value_low == 0xffffffff)) {
> +		if ((i == 0) && (value_low == 0xffffffff)) {
>  			printk_warning("IO APIC not responding.\n");
>  			return;
>  		}
> @@ -117,20 +117,19 @@
>  	uint8_t byte;
>  	uint32_t dword;
>  
> -	/* IO APIC initialization */
> +	/* I/O APIC initialization */
>  	byte = pci_read_config8(dev, 0x74);
> -	byte |= (1<<0); // enable APIC
> +	byte |= (1 << 0);	/* Enable APIC. */
>  	pci_write_config8(dev, 0x74, byte);
> -	dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
> +	dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1);	/* 0x14 */
>  
>  	setup_ioapic(dword);
>  
>  #if 1
>  	dword = pci_read_config32(dev, 0xe4);
> -	dword |= (1<<23);
> +	dword |= (1 << 23);
>  	pci_write_config32(dev, 0xe4, dword);
>  #endif
> -
>  }
>  
>  static void lpc_slave_init(device_t dev)
> @@ -138,132 +137,123 @@
>  	lpc_common_init(dev);
>  }
>  
> -static void rom_dummy_write(device_t dev){
> +static void rom_dummy_write(device_t dev)
> +{
>  	uint8_t old, new;
>  	uint8_t *p;
>  
>  	old = pci_read_config8(dev, 0x88);
>  	new = old | 0xc0;
> -	if (new != old) {
> +	if (new != old)
>  		pci_write_config8(dev, 0x88, new);
> -	}
> -	//  enable write
> +	/* Enable write. */
>  	old = pci_read_config8(dev, 0x6d);
>  	new = old | 0x01;
> -	if (new != old) {
> +	if (new != old)
>  		pci_write_config8(dev, 0x6d, new);
> -	}
>  
> -	/* dummy write */
> -	p = (uint8_t *)0xffffffe0;
> +	/* Dummy write. */
> +	p = (uint8_t *) 0xffffffe0;
>  	old = 0;
>  	*p = old;
>  	old = *p;
>  
> -	//  disable write
> +	/* Disable write. */
>  	old = pci_read_config8(dev, 0x6d);
>  	new = old & 0xfe;
> -	if (new != old) {
> +	if (new != old)
>  		pci_write_config8(dev, 0x6d, new);
> -
> -	}
> -
>  }
> +
>  #if 0
>  static void enable_hpet(struct device *dev)
>  {
>  	unsigned long hpet_address;
>  
> -	pci_write_config32(dev,0x44, 0xfed00001);
> -	hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
> -	printk_debug("enabling HPET @0x%x\n", hpet_address);
> +	pci_write_config32(dev, 0x44, 0xfed00001);
> +	hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
> +	printk_debug("Enabling HPET @0x%x\n", hpet_address);
>  }
>  #endif
>  
>  static void lpc_init(device_t dev)
>  {
> -	uint8_t byte;
> -	uint8_t byte_old;
> -	int on;
> -	int nmi_option;
> +	uint8_t byte, byte_old;
> +	int on, nmi_option;
>  
>  	lpc_common_init(dev);
>  
>  #if CK804_CHIP_REV==1
> -	if(dev->bus->secondary!=1) return;
> +	if (dev->bus->secondary != 1)
> +		return;
>  #endif
>  
>  #if 0
> -	/* posted memory write enable */
> +	/* Posted memory write enable */
>  	byte = pci_read_config8(dev, 0x46);
> -	pci_write_config8(dev, 0x46, byte | (1<<0));
> -
> +	pci_write_config8(dev, 0x46, byte | (1 << 0));
>  #endif
> -	/* power after power fail */
>  
> +	/* power after power fail */
>  	on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
>  	get_option(&on, "power_on_after_fail");
>  	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
>  	byte &= ~0x40;
> -	if (!on) {
> +	if (!on)
>  		byte |= 0x40;
> -	}
>  	pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
> -	printk_info("set power %s after power fail\n", on?"on":"off");
> +	printk_info("set power %s after power fail\n", on ? "on" : "off");
>  
> -	/* Throttle the CPU speed down for testing */
> +	/* Throttle the CPU speed down for testing. */
>  	on = SLOW_CPU_OFF;
>  	get_option(&on, "slow_cpu");
> -	if(on) {
> +	if (on) {
>  		uint16_t pm10_bar;
>  		uint32_t dword;
> -		pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
> -		outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
> +		pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00);
> +		outl(((on << 1) + 0x10), (pm10_bar + 0x10));
>  		dword = inl(pm10_bar + 0x10);
> -		on = 8-on;
> +		on = 8 - on;
>  		printk_debug("Throttling CPU %2d.%1.1d percent.\n",
> -				(on*12)+(on>>1),(on&1)*5);
> +			     (on * 12) + (on >> 1), (on & 1) * 5);
>  	}
> -
>  #if 0
>  // default is enabled
> -	/* Enable Port 92 fast reset */
> +	/* Enable Port 92 fast reset. */
>  	byte = pci_read_config8(dev, 0xe8);
>  	byte |= ~(1 << 3);
>  	pci_write_config8(dev, 0xe8, byte);
>  #endif
>  
> -	/* Enable Error reporting */
> -	/* Set up sync flood detected */
> +	/* Enable Error reporting. */
> +	/* Set up sync flood detected. */
>  	byte = pci_read_config8(dev, 0x47);
>  	byte |= (1 << 1);
>  	pci_write_config8(dev, 0x47, byte);
>  
> -	/* Set up NMI on errors */
> -	byte = inb(0x70); // RTC70
> +	/* Set up NMI on errors. */
> +	byte = inb(0x70);		/* RTC70 */
>  	byte_old = byte;
>  	nmi_option = NMI_OFF;
>  	get_option(&nmi_option, "nmi");
>  	if (nmi_option) {
> -		byte &= ~(1 << 7); /* set NMI */
> +		byte &= ~(1 << 7); /* Set NMI. */
>  	} else {
> -		byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
> +		byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
>  	}
> -	if( byte != byte_old) {
> +	if (byte != byte_old)
>  		outb(0x70, byte);
> -	}
>  
> -	/* Initialize the real time clock */
> +	/* Initialize the real time clock (RTC). */
>  	rtc_init(0);
>  
> -	/* Initialize isa dma */
> +	/* Initialize ISA DMA. */
>  	isa_dma_init();
>  
> -	/* Initialize the High Precision Event Timers */
> -//	enable_hpet(dev);
> +	/* Initialize the High Precision Event Timers (HPET). */
> +	/* enable_hpet(dev); */
>  
>  	rom_dummy_write(dev);
> -
>  }
>  
>  static void ck804_lpc_read_resources(device_t dev)
> @@ -271,43 +261,43 @@
>  	struct resource *res;
>  	unsigned long index;
>  
> -	/* Get the normal pci resources of this device */
> -	pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
> +	/* Get the normal PCI resources of this device. */
> +	/* We got one for APIC, or one more for TRAP. */
> +	pci_dev_read_resources(dev);
>  
> -	/* Get Resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL */
> -	for (index = 0x60; index <= 0x68; index+=4) { // We got another 3.
> +	/* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */
> +	for (index = 0x60; index <= 0x68; index += 4)	/* We got another 3. */
>  		pci_get_resource(dev, index);
> -	}
>  	compact_resources(dev);
>  
> -	/* Add an extra subtractive resource for both memory and I/O */
> +	/* Add an extra subtractive resource for both memory and I/O. */
>  	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
> -	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
> +	res->flags =
> +	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
>  
>  	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
> -	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
> -
> +	res->flags =
> +	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
>  }
>  
>  /**
> - * @brief Enable resources for children devices
> + * Enable resources for children devices.
>   *
> - * @param dev the device whos children's resources are to be enabled
> - *
> - * This function is call by the global enable_resources() indirectly via the
> + * This function is called by the global enable_resources() indirectly via the
>   * device_operation::enable_resources() method of devices.
>   *
>   * Indirect mutual recursion:
>   *      enable_childrens_resources() -> enable_resources()
>   *      enable_resources() -> device_operation::enable_resources()
>   *      device_operation::enable_resources() -> enable_children_resources()
> + *
> + * @param dev The device whose children's resources are to be enabled.
>   */
>  static void ck804_lpc_enable_childrens_resources(device_t dev)
>  {
>  	unsigned link;
>  	uint32_t reg, reg_var[4];
> -	int i;
> -	int var_num = 0;
> +	int i, var_num = 0;
>  
>  	reg = pci_read_config32(dev, 0xa0);
>  
> @@ -315,44 +305,49 @@
>  		device_t child;
>  		for (child = dev->link[link].children; child; child = child->sibling) {
>  			enable_resources(child);
> -			if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
> -				for(i=0;i<child->resources;i++) {
> +			if (child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
> +				for (i = 0; i < child->resources; i++) {
>  					struct resource *res;
> -					unsigned long base, end; // don't need long long
> +					unsigned long base, end;	// don't need long long
>  					res = &child->resource[i];
> -					if(!(res->flags & IORESOURCE_IO)) continue;
> +					if (!(res->flags & IORESOURCE_IO))
> +						continue;
>  					base = res->base;
>  					end = resource_end(res);
> -					printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end);
> -					switch(base) {
> -					case 0x3f8: // COM1
> -						reg |= (1<<0); 	break;
> -					case 0x2f8: // COM2
> -						reg |= (1<<1);  break;
> -					case 0x378: // Parallal 1
> -						reg |= (1<<24); break;
> -					case 0x3f0: // FD0
> -						reg |= (1<<20); break;
> -					case 0x220:  // Aduio 0
> -						reg |= (1<<8); 	break;
> -					case 0x300:  // Midi 0
> -						reg |= (1<<12);	break;
> +					printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n", dev_path(child), base, end);
> +					switch (base) {
> +					case 0x3f8:	// COM1
> +						reg |= (1 << 0);
> +						break;
> +					case 0x2f8:	// COM2
> +						reg |= (1 << 1);
> +						break;
> +					case 0x378:	// Parallel 1
> +						reg |= (1 << 24);
> +						break;
> +					case 0x3f0:	// FD0
> +						reg |= (1 << 20);
> +						break;
> +					case 0x220:	// Audio 0
> +						reg |= (1 << 8);
> +						break;
> +					case 0x300:	// Midi 0
> +						reg |= (1 << 12);
> +						break;
>  					}
> -					if( base == 0x290 || base >= 0x400) {
> -						if(var_num>=4) continue; // only 4 var ; compact them ?
> -						reg |= (1<<(28+var_num));
> -						reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
> +					if (base == 0x290 || base >= 0x400) {
> +						if (var_num >= 4)
> +							continue;	// only 4 var ; compact them ?
> +						reg |= (1 << (28 + var_num));
> +						reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16);
>  					}
>  				}
>  			}
>  		}
>  	}
>  	pci_write_config32(dev, 0xa0, reg);
> -	for(i=0;i<var_num;i++) {
> -		pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
> -	}
> -
> -
> +	for (i = 0; i < var_num; i++)
> +		pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]);
>  }
>  
>  static void ck804_lpc_enable_resources(device_t dev)
> @@ -364,22 +359,23 @@
>  static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
>  {
>  	pci_write_config32(dev, 0x40,
> -		((device & 0xffff) << 16) | (vendor & 0xffff));
> +			   ((device & 0xffff) << 16) | (vendor & 0xffff));
>  }
>  
>  static struct pci_operations lops_pci = {
>  	.set_subsystem = lpci_set_subsystem,
>  };
>  
> -static struct device_operations lpc_ops  = {
> +static struct device_operations lpc_ops = {
>  	.read_resources   = ck804_lpc_read_resources,
>  	.set_resources    = pci_dev_set_resources,
>  	.enable_resources = ck804_lpc_enable_resources,
>  	.init             = lpc_init,
>  	.scan_bus         = scan_static_bus,
> -//	.enable           = ck804_enable,
> +	// .enable        = ck804_enable,
>   

Indentation.

>  	.ops_pci          = &lops_pci,
>  };
> +
>  static const struct pci_driver lpc_driver __pci_driver = {
>  	.ops    = &lpc_ops,
>  	.vendor = PCI_VENDOR_ID_NVIDIA,
> @@ -399,12 +395,12 @@
>  	.device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
>  };
>  #else
> -static struct device_operations lpc_slave_ops  = {
> +static struct device_operations lpc_slave_ops = {
>  	.read_resources   = ck804_lpc_read_resources,
>  	.set_resources    = pci_dev_set_resources,
>  	.enable_resources = pci_dev_enable_resources,
>  	.init             = lpc_slave_init,
> -//	.enable           = ck804_enable,
> +	// .enable        = ck804_enable,
>   

Same here.

>  	.ops_pci          = &lops_pci,
>  };
>  
>
> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -2,6 +2,7 @@
>   * Copyright 2004 Tyan Computer
>   *  by yhlu at tyan.com
>   */
> +
>  #include <console/console.h>
>  #include <device/device.h>
>  #include <device/smbus.h>
> @@ -11,21 +12,16 @@
>  #include <arch/io.h>
>  #include "ck804.h"
>  
> -
>  static void nic_init(struct device *dev)
>  {
> -	uint32_t dword, old;
> -	uint32_t mac_h, mac_l;
> +	uint32_t dword, old, mac_h, mac_l;
>  	int eeprom_valid = 0;
>  	struct southbridge_nvidia_ck804_config *conf;
> -
>  	static uint32_t nic_index = 0;
> -
>  	uint8_t *base;
>  	struct resource *res;
>  
>  	res = find_resource(dev, 0x10);
> -
>  	base = res->base;
>  
>  #define NvRegPhyInterface  0xC0
> @@ -36,37 +32,37 @@
>  	old = dword = pci_read_config32(dev, 0x30);
>  	dword &= ~(0xf);
>  	dword |= 0xf;
> -	if(old != dword) {
> -		pci_write_config32(dev, 0x30 , dword);
> -	}
> +	if (old != dword)
> +		pci_write_config32(dev, 0x30, dword);
>  
>  	conf = dev->chip_info;
>  
> -	if(conf->mac_eeprom_smbus != 0) {
> -//      read MAC address from EEPROM at first
> +	if (conf->mac_eeprom_smbus != 0) {
> +		/* Read MAC address from EEPROM at first. */
>  		struct device *dev_eeprom;
> -		dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
> +		dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus,
> +					   conf->mac_eeprom_addr);
>  
> -		if(dev_eeprom) {
> -		//	if that is valid we will use that
> +		if (dev_eeprom) {
> +			/* If that is valid we will use that. */
>  			unsigned char dat[6];
> -			int status;
> -			int i;
> -			for(i=0;i<6;i++) {
> +			int i, status;
> +			for (i = 0; i < 6; i++) {
>  				status = smbus_read_byte(dev_eeprom, i);
> -				if(status < 0) break;
> +				if (status < 0)
> +					break;
>  				dat[i] = status & 0xff;
>  			}
> -			if(status >= 0) {
> +			if (status >= 0) {
>  				mac_l = 0;
> -				for(i=3;i>=0;i--) {
> +				for (i = 3; i >= 0; i--) {
>  					mac_l <<= 8;
>  					mac_l += dat[i];
>  				}
> -				if(mac_l != 0xffffffff) {
> +				if (mac_l != 0xffffffff) {
>  					mac_l += nic_index;
>  					mac_h = 0;
> -					for(i=5;i>=4;i--) {
> +					for (i = 5; i >= 4; i--) {
>  						mac_h <<= 8;
>  						mac_h += dat[i];
>  					}
> @@ -75,21 +71,22 @@
>  			}
>  		}
>  	}
> -//	if that is invalid we will read that from romstrap
> -	if(!eeprom_valid) {
> +
> +	/* If that is invalid we will read that from romstrap. */
> +	if (!eeprom_valid) {
>  		unsigned long mac_pos;
> -		mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
> +		mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */
>  		mac_l = readl(mac_pos) + nic_index;
>  		mac_h = readl(mac_pos + 4);
>  	}
>  #if 1
> -//      set that into NIC MMIO
> +	/* Set that into NIC MMIO. */
>  #define NvRegMacAddrA  0xA8
>  #define NvRegMacAddrB  0xAC
>  	writel(mac_l, base + NvRegMacAddrA);
>  	writel(mac_h, base + NvRegMacAddrB);
>  #else
> -//	set that into NIC
> +	/* Set that into NIC. */
>  	pci_write_config32(dev, 0xa8, mac_l);
>  	pci_write_config32(dev, 0xac, mac_h);
>  #endif
> @@ -97,35 +94,36 @@
>  	nic_index++;
>  
>  #if CONFIG_PCI_ROM_RUN == 1
> -	pci_dev_init(dev);// it will init option rom
> +	pci_dev_init(dev);	/* It will init Option ROM. */
>  #endif
> -
>  }
>  
>  static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
>  {
>  	pci_write_config32(dev, 0x40,
> -		((device & 0xffff) << 16) | (vendor & 0xffff));
> +			   ((device & 0xffff) << 16) | (vendor & 0xffff));
>  }
>  
>  static struct pci_operations lops_pci = {
>  	.set_subsystem = lpci_set_subsystem,
>  };
>  
> -static struct device_operations nic_ops  = {
> +static struct device_operations nic_ops = {
>  	.read_resources   = pci_dev_read_resources,
>  	.set_resources    = pci_dev_set_resources,
>  	.enable_resources = pci_dev_enable_resources,
>  	.init             = nic_init,
>  	.scan_bus         = 0,
> -//	.enable           = ck804_enable,
> +	// .enable        = ck804_enable,
>   

Indentation.

>  	.ops_pci          = &lops_pci,
>  };
> +
>  static const struct pci_driver nic_driver __pci_driver = {
>  	.ops    = &nic_ops,
>  	.vendor = PCI_VENDOR_ID_NVIDIA,
>  	.device = PCI_DEVICE_ID_NVIDIA_CK804_NIC,
>  };
> +
>  static const struct pci_driver nic_bridge_driver __pci_driver = {
>  	.ops    = &nic_ops,
>  	.vendor = PCI_VENDOR_ID_NVIDIA,
>
> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -12,70 +12,72 @@
>  
>  static void pci_init(struct device *dev)
>  {
> -
>  	uint32_t dword;
>  #if CONFIG_PCI_64BIT_PREF_MEM == 1
>  	device_t pci_domain_dev;
>  	struct resource *mem1, *mem2;
>  #endif
>  
> -	/* System error enable */
>  	dword = pci_read_config32(dev, 0x04);
> -	dword |= (1<<8); /* System error enable */
> -	dword |= (1<<30); /* Clear possible errors */
> +	dword |= (1 << 8);	/* System error enable */
> +	dword |= (1 << 30);	/* Clear possible errors */
>  	pci_write_config32(dev, 0x04, dword);
>  
>  #if 0
>  	word = pci_read_config16(dev, 0x48);
> -	word |= (1<<0); /* MRL2MRM */
> -	word |= (1<<2); /* MR2MRM */
> +	word |= (1 << 0);	/* MRL2MRM */
> +	word |= (1 << 2);	/* MR2MRM */
>  	pci_write_config16(dev, 0x48, word);
>  #endif
>  
>  #if 1
>  	dword = pci_read_config32(dev, 0x4c);
> -	dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
> +	dword |= 0x00440000;	/* TABORT_SER_ENABLE Park Last Enable. */
>  	pci_write_config32(dev, 0x4c, dword);
>  #endif
>  
>  #if CONFIG_PCI_64BIT_PREF_MEM == 1
>  	pci_domain_dev = dev->bus->dev;
> -	while(pci_domain_dev) {
> -		if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break;
> +	while (pci_domain_dev) {
> +		if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)
> +			break;
>  		pci_domain_dev = pci_domain_dev->bus->dev;
>  	}
>  
> -	if(!pci_domain_dev) return; // impossiable
> -	mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit
> -	mem2 = find_resource(pci_domain_dev, 2); // mem
> -	if(mem1->base > mem2->base) {
> -		dword = mem2->base  & (0xffff0000UL);
> +	if (!pci_domain_dev)
> +		return;		/* Impossible */
> +
> +	mem1 = find_resource(pci_domain_dev, 1);	// prefmem, it could be 64bit
> +	mem2 = find_resource(pci_domain_dev, 2);	// mem
> +	if (mem1->base > mem2->base) {
> +		dword = mem2->base & (0xffff0000UL);
>  		printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base);
>  	} else {
> -		dword = mem1->base  & (0xffff0000UL);
> -		printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base);
> +		dword = mem1->base & (0xffff0000UL);
> +		printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n",
> +			     mem1->base);
>  	}
>  #else
>  	dword = dev_root.resource[1].base & (0xffff0000UL);
> -	printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base);
> +	printk_debug("dev_root mem base = 0x%010Lx\n",
> +		     dev_root.resource[1].base);
>  #endif
>  
>  	printk_debug("[0x50] <-- 0x%08x\n", dword);
> -	pci_write_config32(dev, 0x50, dword); //TOM
> -
> +	pci_write_config32(dev, 0x50, dword);	/* TOM */
>  }
>  
>  static struct pci_operations lops_pci = {
>  	.set_subsystem = 0,
>  };
>  
> -static struct device_operations pci_ops  = {
> +static struct device_operations pci_ops = {
>  	.read_resources   = pci_bus_read_resources,
>  	.set_resources    = pci_dev_set_resources,
>  	.enable_resources = pci_bus_enable_resources,
>  	.init             = pci_init,
>  	.scan_bus         = pci_scan_bridge,
> -//	.enable           = ck804_enable,
> +	// .enable        = ck804_enable,
>   

Indentation.

>  	.ops_pci          = &lops_pci,
>  };
>  
> @@ -84,4 +86,3 @@
>  	.vendor = PCI_VENDOR_ID_NVIDIA,
>  	.device = PCI_DEVICE_ID_NVIDIA_CK804_PCI,
>  };
> -
>
> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -12,29 +12,26 @@
>  
>  static void pcie_init(struct device *dev)
>  {
> -
> -	/* Enable pci error detecting */
>  	uint32_t dword;
>  
> -	/* System error enable */
> +	/* Enable PCI error detecting. */
>  	dword = pci_read_config32(dev, 0x04);
> -	dword |= (1<<8); /* System error enable */
> -	dword |= (1<<30); /* Clear possible errors */
> +	dword |= (1 << 8);	/* System error enable */
> +	dword |= (1 << 30);	/* Clear possible errors */
>  	pci_write_config32(dev, 0x04, dword);
> -
>  }
>  
>  static struct pci_operations lops_pci = {
>  	.set_subsystem = 0,
>  };
>  
> -static struct device_operations pcie_ops  = {
> +static struct device_operations pcie_ops = {
>  	.read_resources   = pci_bus_read_resources,
>  	.set_resources    = pci_dev_set_resources,
>  	.enable_resources = pci_bus_enable_resources,
>  	.init             = pcie_init,
>  	.scan_bus         = pci_scan_bridge,
> -//	.enable           = ck804_enable,
> +	// .enable        = ck804_enable,
>   

Indentation.

>  	.ops_pci          = &lops_pci,
>  };
>  
> @@ -43,4 +40,3 @@
>  	.vendor = PCI_VENDOR_ID_NVIDIA,
>  	.device = PCI_DEVICE_ID_NVIDIA_CK804_PCI_E,
>  };
> -
>
> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -15,7 +15,7 @@
>  static void pci_write_config32(device_t dev, unsigned where, unsigned value)
>  {
>  	unsigned addr;
> -	addr = (dev>>4) | where;
> +	addr = (dev >> 4) | where;
>  	outl(0x80000000 | (addr & ~3), 0xCF8);
>  	outl(value, 0xCFC);
>  }
> @@ -23,7 +23,7 @@
>  static unsigned pci_read_config32(device_t dev, unsigned where)
>  {
>  	unsigned addr;
> -	addr = (dev>>4) | where;
> +	addr = (dev >> 4) | where;
>  	outl(0x80000000 | (addr & ~3), 0xCF8);
>  	return inl(0xCFC);
>  }
> @@ -33,8 +33,7 @@
>  void hard_reset(void)
>  {
>  	set_bios_reset();
> -	/* Try rebooting through port 0xcf9 */
> -	outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
> -      	outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
> +	/* Try rebooting through port 0xcf9. */
> +	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
> +	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
>  }
> -
>
> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -2,6 +2,7 @@
>   * Copyright 2004 Tyan Computer
>   *  by yhlu at tyan.com
>   */
> +
>  #include <console/console.h>
>  #include <device/device.h>
>  #include <delay.h>
> @@ -10,7 +11,6 @@
>  #include <device/pci_ops.h>
>  #include "ck804.h"
>  
> -
>  static void sata_com_reset(struct device *dev, unsigned reset)
>  // reset = 1 : reset
>  // reset = 0 : clear
> @@ -23,12 +23,12 @@
>  
>  	printk_debug("base = %08x\r\n", base);
>  
> -	if(reset) {
> -	        *(base + 4) = 0xffffffff;
> -	        *(base + 0x44) = 0xffffffff;
> +	if (reset) {
> +		*(base + 4) = 0xffffffff;
> +		*(base + 0x44) = 0xffffffff;
>  	}
>  
> -	dword = *(base +8);
> +	dword = *(base + 8);
>  	dword &= ~(0xf);
>  	dword |= reset;
>  
> @@ -42,87 +42,89 @@
>  	*(base + 0x48) = dword;
>  #endif
>  
> -	if(reset) return;
> +	if (reset)
> +		return;
>  
> -	dword = *(base+ 0);
> -	printk_debug("*(base+0)=%08x\r\n",dword);
> -	if(dword == 0x113) {
> -		loop = 200000;// 2
> +	dword = *(base + 0);
> +	printk_debug("*(base+0)=%08x\r\n", dword);
> +	if (dword == 0x113) {
> +		loop = 200000;	// 2
>  		do {
> -		        dword = *(base + 4);
> -			if((dword & 0x10000)!=0) break;
> +			dword = *(base + 4);
> +			if ((dword & 0x10000) != 0)
> +				break;
>  			udelay(10);
> -		} while (--loop>0);
> -		printk_debug("loop=%d, *(base+4)=%08x\r\n",loop,  dword);
> +		} while (--loop > 0);
> +		printk_debug("loop=%d, *(base+4)=%08x\r\n", loop, dword);
>  	}
>  
> -	dword = *(base+ 0x40);
> -	printk_debug("*(base+0x40)=%08x\r\n",dword);
> -	if(dword == 0x113) {
> -	        loop = 200000;//2
> -	        do {
> -		        dword = *(base + 0x44);
> -		        if((dword & 0x10000)!=0) break;
> +	dword = *(base + 0x40);
> +	printk_debug("*(base+0x40)=%08x\r\n", dword);
> +	if (dword == 0x113) {
> +		loop = 200000;	//2
> +		do {
> +			dword = *(base + 0x44);
> +			if ((dword & 0x10000) != 0)
> +				break;
>  			udelay(10);
> -		} while (--loop>0);
> -		printk_debug("loop=%d, *(base+0x44)=%08x\r\n",loop,  dword);
> +		} while (--loop > 0);
> +		printk_debug("loop=%d, *(base+0x44)=%08x\r\n", loop, dword);
>  	}
>  }
>  
>  static void sata_init(struct device *dev)
>  {
> -
>  	uint32_t dword;
> +	struct southbridge_nvidia_ck804_config *conf;
>  
> -	struct southbridge_nvidia_ck804_config *conf;
>  	conf = dev->chip_info;
>  
>  	dword = pci_read_config32(dev, 0x50);
> -	/* Ensure prefetch is disabled */
> +	/* Ensure prefetch is disabled. */
>  	dword &= ~((1 << 15) | (1 << 13));
>  	if (conf->sata1_enable) {
> -	        /* Enable secondary SATA interface */
> -	        dword |= (1<<0);
> -	        printk_debug("SATA S \t");
> +		/* Enable secondary SATA interface. */
> +		dword |= (1 << 0);
> +		printk_debug("SATA S \t");
>  	}
>  	if (conf->sata0_enable) {
> -	        /* Enable primary SATA interface */
> -	        dword |= (1<<1);
> -	        printk_debug("SATA P \n");
> +		/* Enable primary SATA interface. */
> +		dword |= (1 << 1);
> +		printk_debug("SATA P \n");
>  	}
>  #if 0
> -//	write back
> -	dword |= (1<<12);
> -	dword |= (1<<14);
> +	/* Write back */
> +	dword |= (1 << 12);
> +	dword |= (1 << 14);
>  #endif
>  
>  #if 0
> -//	ADMA
> -	dword |= (1<<16);
> -	dword |= (1<<17);
> +	/* ADMA */
> +	dword |= (1 << 16);
> +	dword |= (1 << 17);
>  #endif
>  
>  #if 1
> -//DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT.
> -	dword &= ~(0x1f<<24);
> -	dword |= (0x15<<24);
> +	/* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */
> +	dword &= ~(0x1f << 24);
> +	dword |= (0x15 << 24);
>  #endif
>  	pci_write_config32(dev, 0x50, dword);
>  
>  #if 0
> -//SLUMBER_DURING_D3.
> +	/* SLUMBER_DURING_D3 */
>  	dword = pci_read_config32(dev, 0x7c);
> -	dword &=  ~(1<<4);
> +	dword &= ~(1 << 4);
>  	pci_write_config32(dev, 0x7c, dword);
>  
>  	dword = pci_read_config32(dev, 0xd0);
> -	dword &=  ~(0xff<<24);
> -	dword |= (0x68<<24);
> +	dword &= ~(0xff << 24);
> +	dword |= (0x68 << 24);
>  	pci_write_config32(dev, 0xd0, dword);
>  
>  	dword = pci_read_config32(dev, 0xe0);
> -	dword &=  ~(0xff<<24);
> -	dword |= (0x68<<24);
> +	dword &= ~(0xff << 24);
> +	dword |= (0x68 << 24);
>  	pci_write_config32(dev, 0xe0, dword);
>  #endif
>  
> @@ -132,11 +134,11 @@
>  
>  #if 0
>  	dword = pci_read_config32(dev, 0xac);
> -	dword &= ~((1<<13)|(1<<14));
> -	dword |= (1<<13)|(0<<14);
> +	dword &= ~((1 << 13) | (1 << 14));
> +	dword |= (1 << 13) | (0 << 14);
>  	pci_write_config32(dev, 0xac, dword);
>  
> -	sata_com_reset(dev, 1); // for discover some s-atapi device
> +	sata_com_reset(dev, 1);	/* For discover some s-atapi device. */
>  #endif
>  
>  }
> @@ -144,17 +146,18 @@
>  static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
>  {
>  	pci_write_config32(dev, 0x40,
> -	        ((device & 0xffff) << 16) | (vendor & 0xffff));
> +			   ((device & 0xffff) << 16) | (vendor & 0xffff));
>  }
> +
>  static struct pci_operations lops_pci = {
>  	.set_subsystem = lpci_set_subsystem,
>  };
>  
> -static struct device_operations sata_ops  = {
> +static struct device_operations sata_ops = {
>  	.read_resources   = pci_dev_read_resources,
>  	.set_resources    = pci_dev_set_resources,
>  	.enable_resources = pci_dev_enable_resources,
> -//	.enable           = ck804_enable,
> +	// .enable        = ck804_enable,
>  	.init             = sata_init,
>  	.scan_bus         = 0,
>  	.ops_pci          = &lops_pci,
>
> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -2,6 +2,7 @@
>   * Copyright 2004 Tyan Computer
>   *  by yhlu at tyan.com
>   */
> +
>  #include <console/console.h>
>  #include <device/device.h>
>  #include <device/pci.h>
> @@ -68,6 +69,7 @@
>  
>  	return do_smbus_write_byte(res->base, device, address, val);
>  }
> +
>  static struct smbus_bus_operations lops_smbus_bus = {
>  	.recv_byte  = lsmbus_recv_byte,
>  	.send_byte  = lsmbus_send_byte,
> @@ -78,25 +80,26 @@
>  static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
>  {
>  	pci_write_config32(dev, 0x40,
> -		((device & 0xffff) << 16) | (vendor & 0xffff));
> +			   ((device & 0xffff) << 16) | (vendor & 0xffff));
>  }
>  
>  static struct pci_operations lops_pci = {
>  	.set_subsystem = lpci_set_subsystem,
>  };
> +
>  static struct device_operations smbus_ops = {
>  	.read_resources   = pci_dev_read_resources,
>  	.set_resources    = pci_dev_set_resources,
>  	.enable_resources = pci_dev_enable_resources,
>  	.init             = 0,
>  	.scan_bus         = scan_static_bus,
> -//	.enable           = ck804_enable,
> +	// .enable        = ck804_enable,
>   

Indentation.

>  	.ops_pci          = &lops_pci,
>  	.ops_smbus_bus    = &lops_smbus_bus,
>  };
> +
>  static const struct pci_driver smbus_driver __pci_driver = {
>  	.ops    = &smbus_ops,
>  	.vendor = PCI_VENDOR_ID_NVIDIA,
>  	.device = PCI_DEVICE_ID_NVIDIA_CK804_SM,
>  };
> -
>
>
> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -2,6 +2,7 @@
>   * Copyright 2004 Tyan Computer
>   *  by yhlu at tyan.com
>   */
> +
>  #include <console/console.h>
>  #include <device/device.h>
>  #include <device/pci.h>
> @@ -9,34 +10,41 @@
>  #include <device/pci_ops.h>
>  #include "ck804.h"
>  
> -static void usb1_init(struct device *dev) {
> -	struct southbridge_nvidia_ck804_config const * conf=dev->chip_info;
> +static void usb1_init(struct device *dev)
> +{
> +	struct southbridge_nvidia_ck804_config const *conf = dev->chip_info;
>  	if (conf->usb1_hc_reset) {
> -		//Somehow the warm reset does not really resets the USB controller.
> -		//Later, during boot, when the Bus Master bit is set, the USB
> -		//controller trashes the memory, causing weird misbehavior.
> -		//Was detected on Sun Ultra40, where mptable was damaged.
> -		uint32_t bar0=pci_read_config32(dev,0x10);
> -		uint32_t* regs=(uint32_t*)(bar0&~0xfff);
> -		regs[2]|=1;	//OHCI USB HCCommandStatus Register, HostControllerReset bit
> +		/*
> +		 * Somehow the warm reset does not really reset the USB
> +		 * controller. Later, during boot, when the Bus Master bit is
> +		 * set, the USB controller trashes the memory, causing weird
> +		 * misbehavior. Was detected on Sun Ultra40, where mptable
> +		 * was damaged.
> +		 */
> +		uint32_t bar0 = pci_read_config32(dev, 0x10);
> +		uint32_t *regs = (uint32_t *) (bar0 & ~0xfff);
> +
> +		/* OHCI USB HCCommandStatus Register, HostControllerReset bit */
> +		regs[2] |= 1;
>  	}
>  }
>  
>  static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
>  {
>  	pci_write_config32(dev, 0x40,
> -		((device & 0xffff) << 16) | (vendor & 0xffff));
> +			   ((device & 0xffff) << 16) | (vendor & 0xffff));
>  }
> +
>  static struct pci_operations lops_pci = {
>  	.set_subsystem = lpci_set_subsystem,
>  };
>  
> -static struct device_operations usb_ops  = {
> +static struct device_operations usb_ops = {
>  	.read_resources   = pci_dev_read_resources,
>  	.set_resources    = pci_dev_set_resources,
>  	.enable_resources = pci_dev_enable_resources,
>  	.init             = usb1_init,
> -//	.enable           = ck804_enable,
> +	// .enable        = ck804_enable,
>   

Undo the indentation change, please.

>  	.scan_bus         = 0,
>  	.ops_pci          = &lops_pci,
>  };
> @@ -46,4 +54,3 @@
>  	.vendor = PCI_VENDOR_ID_NVIDIA,
>  	.device = PCI_DEVICE_ID_NVIDIA_CK804_USB,
>  };
> -
>
> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c
> ===================================================================
> --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c	2008-10-02 15:42:14 UTC (rev 3630)
> +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c	2008-10-02 18:19:17 UTC (rev 3631)
> @@ -2,6 +2,7 @@
>   * Copyright 2004 Tyan Computer
>   *  by yhlu at tyan.com
>   */
> +
>  #include <console/console.h>
>  #include <device/device.h>
>  #include <device/pci.h>
> @@ -11,7 +12,6 @@
>  
>  static void usb2_init(struct device *dev)
>  {
> -
>  	uint32_t dword;
>  	dword = pci_read_config32(dev, 0xf8);
>  	dword |= 40;
> @@ -21,18 +21,19 @@
>  static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
>  {
>  	pci_write_config32(dev, 0x40,
> -		((device & 0xffff) << 16) | (vendor & 0xffff));
> +			   ((device & 0xffff) << 16) | (vendor & 0xffff));
>  }
> +
>  static struct pci_operations lops_pci = {
>  	.set_subsystem = lpci_set_subsystem,
>  };
>  
> -static struct device_operations usb2_ops  = {
> +static struct device_operations usb2_ops = {
>  	.read_resources   = pci_dev_read_resources,
>  	.set_resources    = pci_dev_set_resources,
>  	.enable_resources = pci_dev_enable_resources,
>  	.init             = usb2_init,
> -//	.enable           = ck804_enable,
> +	// .enable        = ck804_enable,
>   

Undo the indentation change, please.

>  	.scan_bus         = 0,
>  	.ops_pci          = &lops_pci,
>  };
>
>
>   


-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  2 21:55:20 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 02 Oct 2008 21:55:20 +0200
Subject: [coreboot] r3630 build service
In-Reply-To: <E1KlQvR-0001T3-31@khepri.openbios.org>
References: <E1KlQvR-0001T3-31@khepri.openbios.org>
Message-ID: <48E52728.9060405@gmx.net>

Hi Ron,

you accidentially committed the SB600 v3 stuff into the v2 tree. Do you
want to revert or should I take care of that?

Regards,
Carl-Daniel

On 02.10.2008 18:21, coreboot information wrote:
> The developer "rminnich" checked in revision 3630 to
> the coreboot source repository and caused the following 
> changes:
>
> Change Log:
> This is so that people can see it. This is the sb600 for v3. It almost
> certainly won't build -- that comes later. I am hoping to get some
> eyeballs on it for simple errors.
>
> rs690 is next.
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>
>
>
> Build Log:
> Compilation of amd:dbm690t has been broken
> See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3630&device=dbm690t&vendor=am

-- 
http://www.hailfinger.org/




From info at coresystems.de  Thu Oct  2 21:55:37 2008
From: info at coresystems.de (coreboot information)
Date: Thu, 02 Oct 2008 21:55:37 +0200
Subject: [coreboot] r3632 build service
Message-ID: <E1KlUGv-0008W2-KY@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "myles" checked in revision 3632 to
the coreboot source repository and caused the following 
changes:

Change Log:
Whitespace cleanup (trivial).

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Build Log:
Compilation of amd:dbm690t is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3632&device=dbm690t&vendor=amd
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3632&device=j7f24&vendor=jetway
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3632&device=epia-cn&vendor=via


If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Thu Oct  2 22:38:57 2008
From: info at coresystems.de (coreboot information)
Date: Thu, 02 Oct 2008 22:38:57 +0200
Subject: [coreboot] r3633 build service
Message-ID: <E1KlUwr-00034C-8I@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "myles" checked in revision 3633 to
the coreboot source repository and caused the following 
changes:

Change Log:
Whitespace cleanup (trivial).

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Build Log:
Compilation of amd:dbm690t is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3633&device=dbm690t&vendor=amd
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3633&device=j7f24&vendor=jetway
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3633&device=epia-cn&vendor=via


If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From mylesgw at gmail.com  Thu Oct  2 22:44:26 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 2 Oct 2008 14:44:26 -0600
Subject: [coreboot] stop_ap is missing for QEMU, breaks v3 compile
Message-ID: <2831fecf0810021344y2c269f0fsa7e9acd8279daac8@mail.gmail.com>

Make v3 for QEMU build again by adding stop_ap which does nothing.  I'm not
sure this is the right place for it, but it compiles.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From marc.jones at amd.com  Thu Oct  2 22:46:35 2008
From: marc.jones at amd.com (Marc Jones)
Date: Thu, 2 Oct 2008 14:46:35 -0600
Subject: [coreboot] [PATCH] Fix ITE IT8712F pnp_dev_info[] items
In-Reply-To: <20081001132453.GE22678@greenwood>
References: <20081001132453.GE22678@greenwood>
Message-ID: <48E5332B.8060001@amd.com>

Uwe Hermann wrote:
> See patch. The pnp_dev_info[] was incomplete and partly wrong, due to
> me doing blind copy-paste. After checking with the datasheet I _think_
> the contents are correct now, but it would be nice if someone could
> double-check that.
>
> Various other superios have the same problem I'm afraid, I'll post more
> patches later...
>
>
> For parallel port there are _two_ base addresses (0x60/0x61 and 0x62/0x63),
> but most other superios/boards only use the first one (I assume the
> second set is only needed for some non-standard parallel port modes?)
>
>   
Yeah, that is interesting since there is only one IRQ. I have never seen 
a second lpt port used. I would ignore it.

> Also, I left IT8712F_GPIO "empty" like this
>
>   {&ops, IT8712F_GPIO, },
>
> even though it does have 0x60/0x61, 0x62/0x63, and 0x64/0x65 base address
> registers, but those are "SMI# Normal Run Access Base Address" and
> "Simple I/O Base Address" and "Panel Button De-bounce Base Address",
> which I guess we don't need (?)
>
>   
You could put it in for completeness but I doubt it will ever get used.

Why did the io_info.mask change from 0x7f8 to 0xfff8/c/f? That just 
changes the granularity of of the resource? It is not a mask on the 
address. Also, what is io_info.set supposed to do? I didn't find any 
reference to it in the code. Why is it sometimes set to 0x4? It would be 
nice if io_info was documented a little.....


The IO/IRQ/DRQ flags for each device look correct.

Explain the io_info.mask then
Acked-by: Marc Jones <marc.jones at amd.com>
Thanks,
Marc


-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors





From mylesgw at gmail.com  Thu Oct  2 22:58:17 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 2 Oct 2008 14:58:17 -0600
Subject: [coreboot] v3 error messages
Message-ID: <2831fecf0810021358o59f3bb28kd893338e85d83a24@mail.gmail.com>

I can't get v3 for simnow to work with coreinfo as the payload.  I get no
VGA even if I enable it, VGA is never mentioned in the boot log, and it ends
with a triple fault:

cisc-cpu.cpp: CProcessor::GenerateException(): shutdown due to triple fault

Fatal error reached, stopping simulation.  Error message(s) follow:

cisc-cpu.cpp: CProcessor::GenerateException(): shutdown due to triple fault

NOTE:  Simulation cannot be restarted until a reset is asserted.
Simulation state CAN be inspected with the SimNow debugger.

-- end triple fault --

This error shows up in the boot log for simnow 4.4.4pub:
k8_domain_scan_bus
pci_scan_bus start bus 0x0000ce2c, bus->dev 0x0000cbe0
ERROR: pci_scan_bus called with incorrect bus->dev->path.type, path is
PCI_DOMAIN: 0000
PCI: pci_scan_bus for bus 00
pci_scan_bus: old_devices 0x0000cee0, dev for this bus 0x0000cbe0 (domain_0)
PCI: scan devfn 0xc0 to 0xff

It also shows up now in QEMU (it didn't use to.)
pci_domain_scan_bus: calling pci_scan_bus
pci_scan_bus start bus 0x0000ac0c, bus->dev 0x0000a9c0
ERROR: pci_scan_bus called with incorrect bus->dev->path.type, path is
PCI_DOMAIN: 0000
PCI: pci_scan_bus for bus 00

This "Not a multi function device" message is new to QEMU too.
PCI: 00:00.0 [PCI: 8086:1237] enabled
PCI: pci_scan_bus pci_probe_dev returns dev 0x0000b918(dynamic PCI: 00:00.0)
Not a multi function device, or the device is not present. Skip to next
device.
PCI: devfn 0x8
pci_scan_get_dev: list is 0x0008fee0, *list is 0x0000acc0

Has anyone gotten v3 + coreinfo to work on simnow 4.4.4pub?

Thanks,
Myles
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From techie at whiterocker.com  Thu Oct  2 23:13:52 2008
From: techie at whiterocker.com (Chris Kilgour)
Date: Thu, 02 Oct 2008 14:13:52 -0700
Subject: [coreboot] Status of OpenVSA?
In-Reply-To: <48E4A0BF.9050009@ampltd.com>
References: <48E4A0BF.9050009@ampltd.com>
Message-ID: <48E53990.1060303@whiterocker.com>



Stephen Crocker wrote:
> I have been experimenting with the OpenVSA code and have found that it
> becomes stuck on POST code 17.  By adding extra codes, I have narrowed
> this down to the SAVE_STATE macro, which reads the PCI address port
> (cf8).
>
> Furthermore, in order to build it, I had to remove the -Werror flag
> from the Makefile because of several "cast from pointer to integer of
> different size" errors.

Excellent to hear someone is tinkering!  I haven't had time yet to push
openvsa any further along.  Patches are most welcome.

>
> What is the status of the OpenVSA code at the moment?  Are these known
> problems or could it be a problem with my build environment?  Has
> anyone used it successfully?

AFAIK, no one has used it successfully.

Marc at AMD reported problems when he tried it early on, when the
repository was first seeded.  We committed a few patches related to
build environment and licensing, but that's it -- no patches on getting
the code itself fixed up.

Have you got a Geode platform with the FS2 debugger?  It would be great
to get some folks with the time and gear on openvsa.


Chris.



From jordan.crouse at amd.com  Thu Oct  2 23:39:21 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 2 Oct 2008 15:39:21 -0600
Subject: [coreboot] v3 error messages
In-Reply-To: <2831fecf0810021358o59f3bb28kd893338e85d83a24@mail.gmail.com>
References: <2831fecf0810021358o59f3bb28kd893338e85d83a24@mail.gmail.com>
Message-ID: <20081002213921.GC21465@cosmic.amd.com>

On 02/10/08 14:58 -0600, Myles Watson wrote:
> I can't get v3 for simnow to work with coreinfo as the payload.  I get no
> VGA even if I enable it, VGA is never mentioned in the boot log, and it ends
> with a triple fault:
> 
> cisc-cpu.cpp: CProcessor::GenerateException(): shutdown due to triple fault
> 
> Fatal error reached, stopping simulation.  Error message(s) follow:
> 
> cisc-cpu.cpp: CProcessor::GenerateException(): shutdown due to triple fault
> 
> NOTE:  Simulation cannot be restarted until a reset is asserted.
> Simulation state CAN be inspected with the SimNow debugger.
> 
> -- end triple fault --
> 
> This error shows up in the boot log for simnow 4.4.4pub:
> k8_domain_scan_bus
> pci_scan_bus start bus 0x0000ce2c, bus->dev 0x0000cbe0
> ERROR: pci_scan_bus called with incorrect bus->dev->path.type, path is
> PCI_DOMAIN: 0000
> PCI: pci_scan_bus for bus 00
> pci_scan_bus: old_devices 0x0000cee0, dev for this bus 0x0000cbe0 (domain_0)
> PCI: scan devfn 0xc0 to 0xff
> 
> It also shows up now in QEMU (it didn't use to.)
> pci_domain_scan_bus: calling pci_scan_bus
> pci_scan_bus start bus 0x0000ac0c, bus->dev 0x0000a9c0
> ERROR: pci_scan_bus called with incorrect bus->dev->path.type, path is
> PCI_DOMAIN: 0000
> PCI: pci_scan_bus for bus 00
> 
> This "Not a multi function device" message is new to QEMU too.
> PCI: 00:00.0 [PCI: 8086:1237] enabled
> PCI: pci_scan_bus pci_probe_dev returns dev 0x0000b918(dynamic PCI: 00:00.0)
> Not a multi function device, or the device is not present. Skip to next
> device.
> PCI: devfn 0x8
> pci_scan_get_dev: list is 0x0008fee0, *list is 0x0000acc0
> 
> Has anyone gotten v3 + coreinfo to work on simnow 4.4.4pub?

I ran it once, but there were clearly some issues with it.
I got it running with serial, but it was clearly sick.

Can you figure out where it triple faulted?  That would be
useful for debugging.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From rminnich at gmail.com  Thu Oct  2 23:41:27 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 2 Oct 2008 14:41:27 -0700
Subject: [coreboot] v3 error messages
In-Reply-To: <20081002213921.GC21465@cosmic.amd.com>
References: <2831fecf0810021358o59f3bb28kd893338e85d83a24@mail.gmail.com>
	<20081002213921.GC21465@cosmic.amd.com>
Message-ID: <13426df10810021441y12502a92n18759ec0e5520987@mail.gmail.com>

did you get any serial IO?

do a bx fffffff0, reset it, and start it up. I notice I always have to
reset each time I start it. No idea why.

ron



From rminnich at gmail.com  Thu Oct  2 23:43:27 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 2 Oct 2008 14:43:27 -0700
Subject: [coreboot] stop_ap is missing for QEMU, breaks v3 compile
In-Reply-To: <2831fecf0810021344y2c269f0fsa7e9acd8279daac8@mail.gmail.com>
References: <2831fecf0810021344y2c269f0fsa7e9acd8279daac8@mail.gmail.com>
Message-ID: <13426df10810021443k7340509t3919277b7998622e@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

it will be nice if we ever get smp qemu.

ron



From rminnich at gmail.com  Thu Oct  2 23:45:44 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 2 Oct 2008 14:45:44 -0700
Subject: [coreboot] v3 error messages
In-Reply-To: <2831fecf0810021358o59f3bb28kd893338e85d83a24@mail.gmail.com>
References: <2831fecf0810021358o59f3bb28kd893338e85d83a24@mail.gmail.com>
Message-ID: <13426df10810021445r6655bf63ydcc5bd71591d2e18@mail.gmail.com>

On Thu, Oct 2, 2008 at 1:58 PM, Myles Watson <mylesgw at gmail.com> wrote:
> I can't get v3 for simnow to work with coreinfo as the payload.  I get no
> VGA even if I enable it, VGA is never mentioned in the boot log, and it ends
> with a triple fault:
>
> cisc-cpu.cpp: CProcessor::GenerateException(): shutdown due to triple fault
>
> Fatal error reached, stopping simulation.  Error message(s) follow:
>
> cisc-cpu.cpp: CProcessor::GenerateException(): shutdown due to triple fault
>
> NOTE:  Simulation cannot be restarted until a reset is asserted.
> Simulation state CAN be inspected with the SimNow debugger.
>
> -- end triple fault --
>
> This error shows up in the boot log for simnow 4.4.4pub:
> k8_domain_scan_bus
> pci_scan_bus start bus 0x0000ce2c, bus->dev 0x0000cbe0
> ERROR: pci_scan_bus called with incorrect bus->dev->path.type, path is
> PCI_DOMAIN: 0000
> PCI: pci_scan_bus for bus 00
> pci_scan_bus: old_devices 0x0000cee0, dev for this bus 0x0000cbe0 (domain_0)
> PCI: scan devfn 0xc0 to 0xff
>

I'll try it again tonight.

> It also shows up now in QEMU (it didn't use to.)
> pci_domain_scan_bus: calling pci_scan_bus
> pci_scan_bus start bus 0x0000ac0c, bus->dev 0x0000a9c0
> ERROR: pci_scan_bus called with incorrect bus->dev->path.type, path is
> PCI_DOMAIN: 0000
> PCI: pci_scan_bus for bus 00
>
> This "Not a multi function device" message is new to QEMU too.
> PCI: 00:00.0 [PCI: 8086:1237] enabled
> PCI: pci_scan_bus pci_probe_dev returns dev 0x0000b918(dynamic PCI: 00:00.0)
> Not a multi function device, or the device is not present. Skip to next

it's just noise.

I am glad to see you looking at simnow. Keep me posted and I will do
what I can to help. We need more testers (we only have one :-)

ron



From c-d.hailfinger.devel.2006 at gmx.net  Fri Oct  3 00:28:39 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Oct 2008 00:28:39 +0200
Subject: [coreboot] v3 error messages
In-Reply-To: <2831fecf0810021358o59f3bb28kd893338e85d83a24@mail.gmail.com>
References: <2831fecf0810021358o59f3bb28kd893338e85d83a24@mail.gmail.com>
Message-ID: <48E54B17.7020605@gmx.net>

On 02.10.2008 22:58, Myles Watson wrote:
> I can't get v3 for simnow to work with coreinfo as the payload.  I get no
> VGA even if I enable it, VGA is never mentioned in the boot log, and it ends
> with a triple fault:
>
> cisc-cpu.cpp: CProcessor::GenerateException(): shutdown due to triple fault
>
> Fatal error reached, stopping simulation.  Error message(s) follow:
>
> cisc-cpu.cpp: CProcessor::GenerateException(): shutdown due to triple fault
>
> NOTE:  Simulation cannot be restarted until a reset is asserted.
> Simulation state CAN be inspected with the SimNow debugger.
>
> -- end triple fault --
>
> This error shows up in the boot log for simnow 4.4.4pub:
> k8_domain_scan_bus
> pci_scan_bus start bus 0x0000ce2c, bus->dev 0x0000cbe0
> ERROR: pci_scan_bus called with incorrect bus->dev->path.type, path is
> PCI_DOMAIN: 0000
> PCI: pci_scan_bus for bus 00
> pci_scan_bus: old_devices 0x0000cee0, dev for this bus 0x0000cbe0 (domain_0)
> PCI: scan devfn 0xc0 to 0xff
>
> It also shows up now in QEMU (it didn't use to.)
> pci_domain_scan_bus: calling pci_scan_bus
> pci_scan_bus start bus 0x0000ac0c, bus->dev 0x0000a9c0
> ERROR: pci_scan_bus called with incorrect bus->dev->path.type, path is
> PCI_DOMAIN: 0000
>   

Ah yes, the old bug. Very old bug. I added the error message so people
don't wonder why none of the devices in the prebuilt device tree are found.
IIRC Ron wanted to fix that with his device tree rewrite that was
committed some time ago. Oh well.

> PCI: pci_scan_bus for bus 00
>
> This "Not a multi function device" message is new to QEMU too.
> PCI: 00:00.0 [PCI: 8086:1237] enabled
> PCI: pci_scan_bus pci_probe_dev returns dev 0x0000b918(dynamic PCI: 00:00.0)
> Not a multi function device, or the device is not present. Skip to next
> device.
>   

That message should be _INFO. It simply tells you why it skips some
devfn in the scan.

> PCI: devfn 0x8
> pci_scan_get_dev: list is 0x0008fee0, *list is 0x0000acc0
>
> Has anyone gotten v3 + coreinfo to work on simnow 4.4.4pub?
>   

My 64bit machines (needed for Simnow) are down right now and back when
they were working there was no working Simnow target.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Fri Oct  3 03:06:51 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 2 Oct 2008 18:06:51 -0700
Subject: [coreboot] mode 117
Message-ID: <13426df10810021806v385a2b72g2b55c3108914860e@mail.gmail.com>

it's not pretty but this is working to get into mode 117 on the
(private) tree I am using.

It's in the emulator. The 'entering emulator' is what you would see;
the first X86EMU_exec is when we run the vga bios.
 src/devices/emulator/biosemu.c

The way it works is that I put an INT 10 at f0000, followed by a HLT.
It's ok to scribble there because that is the 55aa signature for the
expansion bios -- it's not needed any more, the BIOS is installed.

This appears to work. Tomorrow I'll try scribbling on the frame buffer
and see how it goes.

As Jordan has pointed out,coreboot starts up so fast that I'm going to
need to put a delay in to let the splash screen be visible. But this
is important enough that it is worth doing.

Now I need a modern opteron laptop :-)

thanks
ron
	printk_info("entering emulator\n");

	X86EMU_exec();

	printk_err("Done; now try to set the mode to x117\n");
	X86_AX = 0x4f02;
	X86_BX = 0x117;
	X86_CX = 1;
	X86_DX = 0x0;
	X86_DI = 0;
	X86_EIP = 0x0000;
	X86_CS = initialcs;

	/* Initialize stack and data segment */
	X86_SS = initialcs;
	X86_SP = 0xfffe;
	X86_DS = 0x0040;
	X86_ES = 0x0000;

	/* We need a sane way to return from bios
	 * execution. A hlt instruction and a pointer
	 * to it, both kept on the stack, will do.
	 */
	pushw(0xf4f4);		/* hlt; hlt */
	pushw(X86_SS);
	pushw(X86_SP + 2);
#if 0
   1              	.code16
   2 0000 CD10     		int $0x10
   3 0002 F4       		hlt
   4 0003 F4       		hlt
#endif
	MEM_WB(initialcs<<4+0, 0xCD);
	MEM_WB(initialcs<<4+1, 0x10);
	MEM_WB(initialcs<<4+2, 0xF4);
	MEM_WB(initialcs<<4+3, 0xF4);
//	MEM_WB(initialcs<<4+0, 0xF4);
//	X86EMU_trace_on();

	printk_err("entering emulator\n");

	X86EMU_exec();
	printk_err("Mode should now be set\n");
#endif
}



From techie at whiterocker.com  Fri Oct  3 02:42:02 2008
From: techie at whiterocker.com (Chris Kilgour)
Date: Thu, 02 Oct 2008 17:42:02 -0700
Subject: [coreboot] Exact status of gPXE support?
In-Reply-To: <20081002122631.17400.qmail@stuge.se>
References: <E1KlN3y-00012I-7O@aun.bellman.mea>
	<20081002122631.17400.qmail@stuge.se>
Message-ID: <48E56A5A.9070307@whiterocker.com>


>>    There could possibly exist some code segment in PXElinux that
>>    depends on either 16-bit mode, or lagacy Bios calls, but I do
>>    not a priori know that with any certainty!
>>     
>
> Yes, PXE requires real mode and BIOS interrupt services.
>
>   

For what it's worth, I first was looking at gPXE on coreboot in order to
run PXE, because I had been happily using PXE previously on COTS hardware.

But after realizing that PXE requires a standard real-mode BIOS, I gave
up on PXE under coreboot, and moved to simply booting a mkelfimage
binary transferred over HTTP.  That could be done with etherboot, and I
think that generally people are happy with rom-o-matic ELFs as a
coreboot payload for that purpose.  However, since the gPXE project has
newer things that etherboot will never have (like support for more,
newer ethernet controllers), I felt it was worthwhile to get gPXE
building and booting, at least in a pared-down form, under coreboot.

Chris.





From c-d.hailfinger.devel.2006 at gmx.net  Fri Oct  3 04:31:01 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Oct 2008 04:31:01 +0200
Subject: [coreboot] [PATCH v2] CAR for C7, newest version
Message-ID: <48E583E5.2060701@gmx.net>

Thanks to Jason Zhao we got a skeleton CAR code for VIA C7. I have tried
to clean it up a bit and find justifications for every difference from
x86 and AMD CAR code. I believe this is mostly merge-ready. Although I'd
have preferred to do this for v3 first, we can fix v2 boards with this
change and then move them to v3.
Thanks to Bari Ari for getting the code to me for rewrite/review.

CONFIG_CARTEST shall not be enabled (breaks the build).

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Signed-off-by: Jason Zhao <jasonzhao at viatech.com.cn>

Patch once inline and once attached for your convenience.

Index: LinuxBIOSv2-via_CAR/src/cpu/via/car/cache_as_ram.lds
===================================================================
--- LinuxBIOSv2-via_CAR/src/cpu/via/car/cache_as_ram.lds	(Revision 0)
+++ LinuxBIOSv2-via_CAR/src/cpu/via/car/cache_as_ram.lds	(Revision 0)
@@ -0,0 +1,11 @@
+SECTIONS {
+	.init . : {
+		_init = .;
+		*(.init.text);
+		*(.init.rodata);
+		*(.init.rodata.*);
+		. = ALIGN(16);
+		_einit = .;
+	}
+
+}
Index: LinuxBIOSv2-via_CAR/src/cpu/via/car/cache_as_ram.inc
===================================================================
--- LinuxBIOSv2-via_CAR/src/cpu/via/car/cache_as_ram.inc	(Revision 0)
+++ LinuxBIOSv2-via_CAR/src/cpu/via/car/cache_as_ram.inc	(Revision 0)
@@ -0,0 +1,175 @@
+/* 
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2005 Eswar Nallusamy, LANL
+ * Copyright (C) 2005 Tyan
+ * (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
+ * Copyright (C) 2007 coresystems GmbH
+ * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
+ * Copyright (C) 2007,2008 Carl-Daniel Hailfinger
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Jason Zhao <jasonzhao at viatech.com.cn> for VIA)
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define	CacheSize DCACHE_RAM_SIZE
+#define	CacheBase DCACHE_RAM_BASE
+
+
+#include	<cpu/x86/mtrr.h>
+
+	/* Save the BIST result */
+	movl    %eax, %ebp
+
+CacheAsRam:
+
+	/* disable cache */
+	movl    %cr0, %eax
+	orl    $(0x1<<30),%eax
+	movl    %eax,%cr0
+	invd
+
+	/* Set the default memory type and enable fixed and variable MTRRs */
+	/* FIXME: The block below should not be commented out. Carl-Daniel */
+	/*
+	movl    $MTRRdefType_MSR, %ecx
+	xorl    %edx, %edx
+	/* Enable Variable and Fixed MTRRs */
+	movl    $0x00000c00, %eax
+	wrmsr
+	*/
+
+	/* Clear all MTRRs */
+	xorl    %edx, %edx
+	movl    $fixed_mtrr_msr, %esi
+clear_fixed_var_mtrr:
+	lodsl   (%esi), %eax
+	testl   %eax, %eax
+	jz      clear_fixed_var_mtrr_out
+
+	movl    %eax, %ecx
+	xorl    %eax, %eax
+	wrmsr
+
+	jmp     clear_fixed_var_mtrr
+clear_fixed_var_mtrr_out:
+	/* MTRRPhysBase */
+	movl    $0x200, %ecx
+	xorl    %edx, %edx
+	movl    $(CacheBase|MTRR_TYPE_WRBACK),%eax
+	wrmsr
+
+	/* MTRRPhysMask */
+	movl    $0x201, %ecx
+	/* This assumes we never access addresses above 2^36 in CAR. */
+	movl    $0x0000000f,%edx
+	movl    $(~(CacheSize-1)|0x800),%eax
+	wrmsr
+
+        /* enable write base caching so we can do execute in place
+         * on the flash rom.
+         */
+	/* MTRRPhysBase */
+	movl    $0x202, %ecx
+	xorl    %edx, %edx
+	movl    $(XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax
+	wrmsr
+
+	/* MTRRPhysMask */
+	movl    $0x203, %ecx
+	mo