[coreboot] r876 - in coreboot-v3: device include/device mainboard/gigabyte/m57sli southbridge/nvidia/mcp55 superio/ite/it8716f
svn at coreboot.org
svn at coreboot.org
Wed Oct 1 08:47:52 CEST 2008
Author: rminnich
Date: 2008-10-01 08:47:51 +0200 (Wed, 01 Oct 2008)
New Revision: 876
Added:
coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h
Modified:
coreboot-v3/device/pnp_raw.c
coreboot-v3/include/device/pnp.h
coreboot-v3/mainboard/gigabyte/m57sli/Makefile
coreboot-v3/mainboard/gigabyte/m57sli/initram.c
coreboot-v3/mainboard/gigabyte/m57sli/stage1.c
coreboot-v3/southbridge/nvidia/mcp55/stage1.c
coreboot-v3/superio/ite/it8716f/it8716f.h
Log:
Bringing the m57sli to life. This includes changes to mcp55 and
mainboard that we learned with the serengeti that we needed. New
function in pnp that is for reading. new prototype in pnp.h. New
constants for ite8716f.
This board does not build yet; we are exercising code in k8 north that
the serengeti did not enable. More tomorrow.
Now that we have two boards under way we can hopefully see our way to
getting more put in. The 690 is the obvious next choice.
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Modified: coreboot-v3/device/pnp_raw.c
===================================================================
--- coreboot-v3/device/pnp_raw.c 2008-09-29 17:24:44 UTC (rev 875)
+++ coreboot-v3/device/pnp_raw.c 2008-10-01 06:47:51 UTC (rev 876)
@@ -52,7 +52,8 @@
*
* This is done by writing the register number to the port, and the value
* into port + 1. This code assumes that the data port is always the
- * config-port plus 1, but luckily this is true for pretty much all devices.
+ * config-port plus 1, but luckily this is true for pretty much all devices, since
+ * it is part of the standard.
*
* @param port The device I/O port.
* @param reg The register number.
@@ -65,6 +66,24 @@
}
/**
+ * Read an 8-bit pnp config value
+ *
+ * This is done by writing the register number to the port, and the value
+ * into port + 1. This code assumes that the data port is always the
+ * config-port plus 1, but luckily this is true for pretty much all devices, since
+ * it is part of the standard.
+ *
+ * @param port The device I/O port.
+ * @param reg The register number.
+ * @returns value of the register
+ */
+u8 rawpnp_read_config(u16 port, u8 reg)
+{
+ outb(reg, port);
+ return inb(port + 1);
+}
+
+/**
* Select a logical device.
*
* PNP has up to 16 logical devices. They are selected by writing the
Modified: coreboot-v3/include/device/pnp.h
===================================================================
--- coreboot-v3/include/device/pnp.h 2008-09-29 17:24:44 UTC (rev 875)
+++ coreboot-v3/include/device/pnp.h 2008-10-01 06:47:51 UTC (rev 876)
@@ -27,6 +27,7 @@
void rawpnp_enter_ext_func_mode(u16 port);
void rawpnp_exit_ext_func_mode(u16 port);
void rawpnp_write_config(u16 port, u8 reg, u8 value);
+u8 rawpnp_read_config(u16 port, u8 reg);
void rawpnp_set_logical_device(u16 port, u8 ldn);
void rawpnp_set_enable(u16 port, int enable);
void rawpnp_set_iobase(u16 port, u8 index, u16 iobase);
Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-09-29 17:24:44 UTC (rev 875)
+++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-10-01 06:47:51 UTC (rev 876)
@@ -19,17 +19,25 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
+STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
+ $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
$(src)/mainboard/$(MAINBOARDDIR)/option_table.c \
+ $(src)/arch/x86/stage1_mtrr.c \
+ $(src)/arch/x86/amd/model_fxx/dualcore_id.c \
+ $(src)/arch/x86/amd/model_fxx/stage1.c \
$(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
$(src)/northbridge/amd/k8/coherent_ht.c \
$(src)/northbridge/amd/k8/incoherent_ht.c \
- $(src)/lib/clog2.c
+ $(src)/northbridge/amd/k8/libstage1.c \
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/k8/raminit.c \
$(src)/northbridge/amd/k8/dqs.c \
+ $(src)/northbridge/amd/k8/reset_test.c \
$(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
+ $(src)/arch/x86/amd/model_fxx/dualcore.c \
+ $(src)/arch/x86/amd/model_fxx/fidvid.c \
+ $(src)/arch/x86/amd/model_fxx/init_cpus.c \
$(src)/lib/clog2.c
Modified: coreboot-v3/mainboard/gigabyte/m57sli/initram.c
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/initram.c 2008-09-29 17:24:44 UTC (rev 875)
+++ coreboot-v3/mainboard/gigabyte/m57sli/initram.c 2008-10-01 06:47:51 UTC (rev 876)
@@ -20,7 +20,7 @@
*/
#define _MAINOBJECT
-
+#include <mainboard.h>
#include <types.h>
#include <lib.h>
#include <console.h>
Added: coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h (rev 0)
+++ coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h 2008-10-01 06:47:51 UTC (rev 876)
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ * Constants that are mainboard-defined and do not belong in Kconfig.
+ * We really do not want this stuff to be visible -- it will make it appear that they can be
+ * changed, and they can not.
+ *
+ * Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* we are unsure of these */
+#define DIMM_SOCKETS 4
+#define NODE_NUMS 16
+#define CPU_SOCKET_TYPE SOCKET_AM2
+/* these have been checked against v2 */
+#define MEM_TRAIN_SEQ 1
+#define HW_MEM_HOLE_SIZE_AUTO_INC 1
+#define HW_MEM_HOLE_SIZEK 0x100000
+#define HT_CHAIN_UNITID_BASE 0
+#define HT_CHAIN_END_UNITID_BASE 0x6
+#define SB_HT_CHAIN_ON_BUS0 2
+#define SB_HT_CHAIN_UNITID_OFFSET_ONLY 0
+#define ENABLE_APIC_EXT_ID 0
+#define LIFT_BSP_APIC_ID 1
+#define K8_SET_FIDVID 1
+/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores,
+ * so may don't need to do twice */
+#define K8_SET_FIDVID_CORE0_ONLY 1
+
+/* architecture stuff which ought to be set "somewhere" "SOMEHOW" */
+/* preferably by asking the CPU, not be a DEFINE! */
+#define CPU_ADDR_BITS 40
Modified: coreboot-v3/mainboard/gigabyte/m57sli/stage1.c
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/stage1.c 2008-09-29 17:24:44 UTC (rev 875)
+++ coreboot-v3/mainboard/gigabyte/m57sli/stage1.c 2008-10-01 06:47:51 UTC (rev 876)
@@ -19,22 +19,313 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <mainboard.h>
#include <types.h>
#include <lib.h>
#include <console.h>
#include <device/device.h>
+#include <device/pnp.h>
#include <cpu.h>
-#include <amd/k8/k8.h>
-#include <amd/k8/sysconf.h>
#include <device/pci.h>
#include <string.h>
#include <msr.h>
#include <io.h>
#include <arch/x86/msr.h>
+#include <superio/ite/it8716f/it8716f.h>
+#include <amd/k8/k8.h>
+#include <amd/k8/sysconf.h>
+#define SUPERIO_DEV 0x2e
+#define SERIAL_DEV IT8716F_SP1
+#define GPIO_DEV IT8716F_GPIO
+#define SERIAL_IOBASE 0x3f8
+static const struct rmap register_values[] = {
+ /* Careful set limit registers before base registers which contain the enables */
+ /* DRAM Limit i Registers
+ * F1:0x44 i = 0
+ * F1:0x4C i = 1
+ * F1:0x54 i = 2
+ * F1:0x5C i = 3
+ * F1:0x64 i = 4
+ * F1:0x6C i = 5
+ * F1:0x74 i = 6
+ * F1:0x7C i = 7
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 7: 3] Reserved
+ * [10: 8] Interleave select
+ * specifies the values of A[14:12] to use with interleave enable.
+ * [15:11] Reserved
+ * [31:16] DRAM Limit Address i Bits 39-24
+ * This field defines the upper address bits of a 40 bit address
+ * that define the end of the DRAM region.
+ */
+ PCM(0, 0x18, 1, 0x44 , 0x0000f8f8, 0x00000000),
+ PCM(0, 0x18, 1, 0x4C , 0x0000f8f8, 0x00000001),
+ PCM(0, 0x18, 1, 0x54 , 0x0000f8f8, 0x00000002),
+ PCM(0, 0x18, 1, 0x5C , 0x0000f8f8, 0x00000003),
+ PCM(0, 0x18, 1, 0x64 , 0x0000f8f8, 0x00000004),
+ PCM(0, 0x18, 1, 0x6C , 0x0000f8f8, 0x00000005),
+ PCM(0, 0x18, 1, 0x74 , 0x0000f8f8, 0x00000006),
+ PCM(0, 0x18, 1, 0x7C , 0x0000f8f8, 0x00000007),
+
+ /* DRAM Base i Registers
+ * F1:0x40 i = 0
+ * F1:0x48 i = 1
+ * F1:0x50 i = 2
+ * F1:0x58 i = 3
+ * F1:0x60 i = 4
+ * F1:0x68 i = 5
+ * F1:0x70 i = 6
+ * F1:0x78 i = 7
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 7: 2] Reserved
+ * [10: 8] Interleave Enable
+ * 000 = No interleave
+ * 001 = Interleave on A[12] (2 nodes)
+ * 010 = reserved
+ * 011 = Interleave on A[12] and A[14] (4 nodes)
+ * 100 = reserved
+ * 101 = reserved
+ * 110 = reserved
+ * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+ * [15:11] Reserved
+ * [13:16] DRAM Base Address i Bits 39-24
+ * This field defines the upper address bits of a 40-bit address
+ * that define the start of the DRAM region.
+ */
+ PCM(0, 0x18, 1, 0x40 , 0x0000f8fc, 0x00000000),
+ PCM(0, 0x18, 1, 0x48 , 0x0000f8fc, 0x00000000),
+ PCM(0, 0x18, 1, 0x50 , 0x0000f8fc, 0x00000000),
+ PCM(0, 0x18, 1, 0x58 , 0x0000f8fc, 0x00000000),
+ PCM(0, 0x18, 1, 0x60 , 0x0000f8fc, 0x00000000),
+ PCM(0, 0x18, 1, 0x68 , 0x0000f8fc, 0x00000000),
+ PCM(0, 0x18, 1, 0x70 , 0x0000f8fc, 0x00000000),
+ PCM(0, 0x18, 1, 0x78 , 0x0000f8fc, 0x00000000),
+
+ /* Memory-Mapped I/O Limit i Registers
+ * F1:0x84 i = 0
+ * F1:0x8C i = 1
+ * F1:0x94 i = 2
+ * F1:0x9C i = 3
+ * F1:0xA4 i = 4
+ * F1:0xAC i = 5
+ * F1:0xB4 i = 6
+ * F1:0xBC i = 7
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 3: 3] Reserved
+ * [ 5: 4] Destination Link ID
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 = Reserved
+ * [ 6: 6] Reserved
+ * [ 7: 7] Non-Posted
+ * 0 = CPU writes may be posted
+ * 1 = CPU writes must be non-posted
+ * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+ * This field defines the upp adddress bits of a 40-bit address that
+ * defines the end of a memory-mapped I/O region n
+ */
+ PCM(0, 0x18, 1, 0x84 , 0x00000048, 0x00000000),
+ PCM(0, 0x18, 1, 0x8C , 0x00000048, 0x00000000),
+ PCM(0, 0x18, 1, 0x94 , 0x00000048, 0x00000000),
+ PCM(0, 0x18, 1, 0x9C , 0x00000048, 0x00000000),
+ PCM(0, 0x18, 1, 0xA4 , 0x00000048, 0x00000000),
+ PCM(0, 0x18, 1, 0xAC , 0x00000048, 0x00000000),
+ PCM(0, 0x18, 1, 0xB4 , 0x00000048, 0x00000000),
+// PCM(0, 0x18, 1, 0xBC , 0x00000048, 0x00ffff00),
+
+ /* Memory-Mapped I/O Base i Registers
+ * F1:0x80 i = 0
+ * F1:0x88 i = 1
+ * F1:0x90 i = 2
+ * F1:0x98 i = 3
+ * F1:0xA0 i = 4
+ * F1:0xA8 i = 5
+ * F1:0xB0 i = 6
+ * F1:0xB8 i = 7
+ * [ 0: 0] Read Enable
+ * 0 = Reads disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes disabled
+ * 1 = Writes Enabled
+ * [ 2: 2] Cpu Disable
+ * 0 = Cpu can use this I/O range
+ * 1 = Cpu requests do not use this I/O range
+ * [ 3: 3] Lock
+ * 0 = base/limit registers i are read/write
+ * 1 = base/limit registers i are read-only
+ * [ 7: 4] Reserved
+ * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+ * This field defines the upper address bits of a 40bit address
+ * that defines the start of memory-mapped I/O region i
+ */
+ PCM(0, 0x18, 1, 0x80 , 0x000000f0, 0x00000000),
+ PCM(0, 0x18, 1, 0x88 , 0x000000f0, 0x00000000),
+ PCM(0, 0x18, 1, 0x90 , 0x000000f0, 0x00000000),
+ PCM(0, 0x18, 1, 0x98 , 0x000000f0, 0x00000000),
+ PCM(0, 0x18, 1, 0xA0 , 0x000000f0, 0x00000000),
+ PCM(0, 0x18, 1, 0xA8 , 0x000000f0, 0x00000000),
+ PCM(0, 0x18, 1, 0xB0 , 0x000000f0, 0x00000000),
+// PCM(0, 0x18, 1, 0xB8 , 0x000000f0, 0x00fc0003),
+
+ /* PCI I/O Limit i Registers
+ * F1:0xC4 i = 0
+ * F1:0xCC i = 1
+ * F1:0xD4 i = 2
+ * F1:0xDC i = 3
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 3: 3] Reserved
+ * [ 5: 4] Destination Link ID
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 = reserved
+ * [11: 6] Reserved
+ * [24:12] PCI I/O Limit Address i
+ * This field defines the end of PCI I/O region n
+ * [31:25] Reserved
+ */
+// PCM(0, 0x18, 1, 0xC4 , 0xFE000FC8, 0x00007000),
+ PCM(0, 0x18, 1, 0xCC , 0xFE000FC8, 0x00000000),
+ PCM(0, 0x18, 1, 0xD4 , 0xFE000FC8, 0x00000000),
+ PCM(0, 0x18, 1, 0xDC , 0xFE000FC8, 0x00000000),
+
+ /* PCI I/O Base i Registers
+ * F1:0xC0 i = 0
+ * F1:0xC8 i = 1
+ * F1:0xD0 i = 2
+ * F1:0xD8 i = 3
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 3: 2] Reserved
+ * [ 4: 4] VGA Enable
+ * 0 = VGA matches Disabled
+ * 1 = matches all address < 64K and where A[9:0] is in the
+ * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+ * [ 5: 5] ISA Enable
+ * 0 = ISA matches Disabled
+ * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+ * from matching agains this base/limit pair
+ * [11: 6] Reserved
+ * [24:12] PCI I/O Base i
+ * This field defines the start of PCI I/O region n
+ * [31:25] Reserved
+ */
+// PCM(0, 0x18, 1, 0xC0 , 0xFE000FCC, 0x00000033),
+ PCM(0, 0x18, 1, 0xC8 , 0xFE000FCC, 0x00000000),
+ PCM(0, 0x18, 1, 0xD0 , 0xFE000FCC, 0x00000000),
+ PCM(0, 0x18, 1, 0xD8 , 0xFE000FCC, 0x00000000),
+
+ /* Config Base and Limit i Registers
+ * F1:0xE0 i = 0
+ * F1:0xE4 i = 1
+ * F1:0xE8 i = 2
+ * F1:0xEC i = 3
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 2: 2] Device Number Compare Enable
+ * 0 = The ranges are based on bus number
+ * 1 = The ranges are ranges of devices on bus 0
+ * [ 3: 3] Reserved
+ * [ 6: 4] Destination Node
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 7: 7] Reserved
+ * [ 9: 8] Destination Link
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 - Reserved
+ * [15:10] Reserved
+ * [23:16] Bus Number Base i
+ * This field defines the lowest bus number in configuration region i
+ * [31:24] Bus Number Limit i
+ * This field defines the highest bus number in configuration region i
+ */
+// PCM(0, 0x18, 1, 0xE0 , 0x0000FC88, 0xff000003), /* link 0 of cpu 0 --> Nvidia MCP55 */
+ PCM(0, 0x18, 1, 0xE4 , 0x0000FC88, 0x00000000),
+ PCM(0, 0x18, 1, 0xE8 , 0x0000FC88, 0x00000000),
+ PCM(0, 0x18, 1, 0xEC , 0x0000FC88, 0x00000000),
+
+ };
+
+
void hardware_stage1(void)
{
+ void it8716f_enable_serial(u8 dev, u8 serial, u16 iobase);
+ void enumerate_ht_chain(void);
+ int max;
+ u8 tmp;
+
+ printk(BIOS_ERR, "Stage1: enable rom ...\n");
+ max = ARRAY_SIZE(register_values);
+ rawpnp_enter_ext_func_mode(SUPERIO_DEV);
+ /* The following line will set CLKIN to 24 MHz, external */
+ rawpnp_write_config(SUPERIO_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
+ tmp = rawpnp_read_config(SUPERIO_DEV, IT8716F_CONFIG_REG_SWSUSP);
+ /* Is serial flash enabled? Then enable writing to serial flash. */
+ if (tmp & 0x0e) {
+ rawpnp_write_config(SUPERIO_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
+ rawpnp_set_logical_device(SUPERIO_DEV, GPIO_DEV);
+ /* Set Serial Flash interface to 0x0820 */
+ rawpnp_write_config(SUPERIO_DEV, 0x64, 0x08);
+ rawpnp_write_config(SUPERIO_DEV, 0x65, 0x20);
+ /* We can get away with not resetting the logical device because
+ * it8716f_enable_serial will do that.
+ */
+ }
+ it8716f_enable_serial(SUPERIO_DEV, SERIAL_DEV, SERIAL_IOBASE);
+ rawpnp_exit_ext_func_mode(SERIAL_DEV);
+
+ setup_resource_map(register_values, max);
+ enumerate_ht_chain();
+ printk(BIOS_ERR, "Done.\n");
post_code(POST_START_OF_MAIN);
}
Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-09-29 17:24:44 UTC (rev 875)
+++ coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-10-01 06:47:51 UTC (rev 876)
@@ -18,7 +18,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
+#include <mainboard.h>
#include <console.h>
#include <lib.h>
#include <io.h>
Modified: coreboot-v3/superio/ite/it8716f/it8716f.h
===================================================================
--- coreboot-v3/superio/ite/it8716f/it8716f.h 2008-09-29 17:24:44 UTC (rev 875)
+++ coreboot-v3/superio/ite/it8716f/it8716f.h 2008-10-01 06:47:51 UTC (rev 876)
@@ -37,4 +37,12 @@
#define IT8716F_GAME 0x09 /* GAME port */
#define IT8716F_IR 0x0a /* Consumer IR */
+/* Global configuration registers. */
+#define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
+#define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+#define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
+#define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
+
+
#endif /* SUPERIO_ITE_IT8716F_IT8716F_H */
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