[coreboot] [PATCH] Fix ITE IT8712F pnp_dev_info[] items

Uwe Hermann uwe at hermann-uwe.de
Fri Oct 3 14:39:27 CEST 2008

On Thu, Oct 02, 2008 at 02:46:35PM -0600, Marc Jones wrote:
> Uwe Hermann wrote:
>> See patch. The pnp_dev_info[] was incomplete and partly wrong, due to
>> me doing blind copy-paste. After checking with the datasheet I _think_
>> the contents are correct now, but it would be nice if someone could
>> double-check that.
>> Various other superios have the same problem I'm afraid, I'll post more
>> patches later...
>> For parallel port there are _two_ base addresses (0x60/0x61 and 0x62/0x63),
>> but most other superios/boards only use the first one (I assume the
>> second set is only needed for some non-standard parallel port modes?)
> Yeah, that is interesting since there is only one IRQ. I have never seen  
> a second lpt port used. I would ignore it.


>> Also, I left IT8712F_GPIO "empty" like this
>>   {&ops, IT8712F_GPIO, },
>> even though it does have 0x60/0x61, 0x62/0x63, and 0x64/0x65 base address
>> registers, but those are "SMI# Normal Run Access Base Address" and
>> "Simple I/O Base Address" and "Panel Button De-bounce Base Address",
>> which I guess we don't need (?)
> You could put it in for completeness but I doubt it will ever get used.

Yep, ok.

> Why did the io_info.mask change from 0x7f8 to 0xfff8/c/f? That just  
> changes the granularity of of the resource? It is not a mask on the  
> address.

This is my biggest concern, I'm really not sure what values to put here.
My assumption was that those values are indeed bitmasks, specifying
which bits of the 0x60/0x61 registers shall be used for the I/O address.

For example: The IT8712F datasheet says for serial port 1:

8.5.2   Serial Port 1 Base Address MSB Register (Index=60h, Default=03h)
    Bit    Description
    7-4    Read only as "0h" for Base Address[15:12].
    3-0    Read/write, mapped as Base Address[11:8].
8.5.3   Serial Port 1 Base Address LSB Register (Index=61h, Default=F8h)
    Bit    Description
    7-3    Read/write, mapped as Base Address[7:3].
    2-0    Read only as "000b."

So bits 11..3 consitute the base address, the rest (15..12 and 2..0 are
zero and unused).

I used this information, the bitmask 0b0000111111111000, as the io_info.mask
values for the serial port (that's 0xff8 if converted to hex).

For the parallel port the datasheet says:

8.7.2  Parallel Port Primary Base Address MSB Register (Index=60h, Default=03h)
     Bit      Description
     7-4      Read only as "0h" for Base Address[15:12]
     3-0      Read/write, mapped as Base Address[11:8]
8.7.3  Parallel Port Primary Base Address LSB Register (Index=61h, Default=78h)
If the bit 2 is set to 1, the EPP mode is disabled automatically.
     Bit      Description
     7-2      Read/write, mapped as Base Address[7:2]
     1-0      Read only as "00b."

So I used the (different) bitmask 0b0000111111111100 here (0xffc).

For the keyboard the mask is 0b0000111111111111, thus 0xfff.

Now, the important question is whether what I'm doing is actually
_correct_ or if I misunderstood the purpose of that bitmask...

> Also, what is io_info.set supposed to do? I didn't find any  
> reference to it in the code. Why is it sometimes set to 0x4? It would be  
> nice if io_info was documented a little.....

This is the big question. It seems nobody knows what it was ever used
for, and to me it definately seems unused nowadays. Ward asked the same
question a while ago, see

Does anybody remember what purpose the ".set" value serves/served?

> The IO/IRQ/DRQ flags for each device look correct.
> Explain the io_info.mask then
> Acked-by: Marc Jones <marc.jones at amd.com>

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