[coreboot] r890 - coreboot-v3/southbridge/nvidia/mcp55

[svn at coreboot.org]

Author: rminnich
Date: 2008-10-06 07:18:22 +0200 (Mon, 06 Oct 2008)
New Revision: 890

Added:
   coreboot-v3/southbridge/nvidia/mcp55/stage1_enable_rom.c
Modified:
   coreboot-v3/southbridge/nvidia/mcp55/stage1.c
   coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c
Log:
Cleanup to get to building a bios. This is as far as I want to take this 
awful chip. But it builds. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/stage1.c	2008-10-05 04:56:29 UTC (rev 889)
+++ coreboot-v3/southbridge/nvidia/mcp55/stage1.c	2008-10-06 05:18:22 UTC (rev 890)
@@ -28,8 +28,10 @@
 #include <amd/k8/k8.h>
 #include "mcp55.h"
 
-#warning fix disgusting define of MCP55_NUM it is mainboard dependent
-#define MCP55_NUM 1
+#ifndef MCP55_NUM
+#error MCP55_NUM should be defined in mainboard.h (in the mainboard directory)
+#endif
+
 int set_ht_link_mcp55(u8 ht_c_num)
 {
 	int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid,  unsigned val);
@@ -441,10 +443,10 @@
 
 }
 
+void set_bios_reset(void);
 void hard_reset(void)
 {
-#warning what is set_bios_reset
-//	set_bios_reset();
+	set_bios_reset();
 
 	/* full reset */
 	outb(0x0a, 0x0cf9);
@@ -460,12 +462,31 @@
 
 void soft_reset(void)
 {
-#warning what is set_bios_reset
-//	set_bios_reset();
-#if 1
+	set_bios_reset();
 	/* link reset */
 	outb(0x02, 0x0cf9);
 	outb(0x06, 0x0cf9);
-#endif
 }
 
+/* this seems to be needed. The mcp55 is a real mess. I won't miss it. */
+void sio_setup(u32 devn)
+{
+
+        unsigned value;
+        u32 dword;
+        u8 byte;
+
+        byte = pci_conf1_read_config8(PCI_BDF(0, devn+1 , 0), 0x7b);
+        byte |= 0x20; 
+        pci_conf1_write_config8(PCI_BDF(0, devn+1 , 0), 0x7b, byte);
+        
+        dword = pci_conf1_read_config32(PCI_BDF(0, devn+1 , 0), 0xa0);
+        dword |= (1<<0);
+        pci_conf1_write_config32(PCI_BDF(0, devn+1 , 0), 0xa0, dword);
+        
+        dword = pci_conf1_read_config32(PCI_BDF(0, devn+1 , 0), 0xa4);
+        dword |= (1<<16);
+        pci_conf1_write_config32(PCI_BDF(0, devn+1 , 0), 0xa4, dword);
+}
+
+

Added: coreboot-v3/southbridge/nvidia/mcp55/stage1_enable_rom.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/stage1_enable_rom.c	                        (rev 0)
+++ coreboot-v3/southbridge/nvidia/mcp55/stage1_enable_rom.c	2008-10-06 05:18:22 UTC (rev 890)
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+#include <mainboard.h>
+#include <types.h>
+#include <lib.h>
+#include <device/device.h>
+#include <device/pci.h>
+void mcp55_enable_rom(void)
+{
+	u8 byte;
+	u16 word;
+	u32 addr;
+
+	/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
+	addr = PCI_BDF(0, (MCP55_DEVN_BASE+1), 0);
+
+	/* Set the 4MB enable bit bit */
+	byte = pci_conf1_read_config8(addr, 0x88);
+	byte |= 0xff; //256K
+	pci_conf1_write_config8(addr, 0x88, byte);
+	byte = pci_conf1_read_config8(addr, 0x8c);
+	byte |= 0xff; //1M
+	pci_conf1_write_config8(addr, 0x8c, byte);
+	word = pci_conf1_read_config16(addr, 0x90);
+	word |= 0x7fff; //15M
+	pci_conf1_write_config16(addr, 0x90, word);
+}

Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c	2008-10-05 04:56:29 UTC (rev 889)
+++ coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c	2008-10-06 05:18:22 UTC (rev 890)
@@ -21,13 +21,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* This should probably be a config variable. */
-#if HT_CHAIN_END_UNITID_BASE != 0x20
-	#define MCP55_DEVN_BASE	HT_CHAIN_END_UNITID_BASE
-#else
-	#define MCP55_DEVN_BASE	HT_CHAIN_UNITID_BASE
-#endif
-
+#include <mainboard.h>
 #define EHCI_BAR_INDEX	0x10
 #define EHCI_BAR	0xFEF00000
 #define EHCI_DEBUG_OFFSET	0x98