[coreboot] v3 updates

[ron minnich]

On Tue, Oct 7, 2008 at 9:44 AM, Myles Watson <mylesgw at gmail.com> wrote:
>
>
>> Here is a proposed change to dts. I've forgotten all I ever knew about
>> the 8111 so I am pretty sure this is incomplete, but it's something
>> like what we want.
>>
>>
>> Index: mainboard/amd/serengeti/dts
>> ===================================================================
>> --- mainboard/amd/serengeti/dts       (revision 904)
>> +++ mainboard/amd/serengeti/dts       (working copy)
>> @@ -28,18 +28,17 @@
>>               /config/("northbridge/amd/k8/domain");
>>               pci at 1,0{
>>               };
>> -             /* guesses; we need a real lspci */
>>               pci0 at 18,0 {
>>                       /config/("northbridge/amd/k8/pci");
>> -                     pci at 0,0 {
>> +                     pci at 0,0 {
>>
> /config/("southbridge/amd/amd8111/amd8111.dts");
>> +                             pci at 1,0 {
>> +
> /config/("southbridge/amd/amd8111/nic.dts");
>> +                             };
>>                       };
>>                       pci at 4,0 {
>>                               /config/("southbridge/amd/amd8111/ide.dts");
>>                       };
>> -                     pci at 5,0 {
>> -                             /config/("southbridge/amd/amd8111/nic.dts");
>> -                     };
>>               };
>>               pci1 at 18,0 {
>>                       /config/("northbridge/amd/k8/pci");
>>
>> It still doesn't seem quite right. Segher?
>
> I've played with it a little more, no luck yet.  Could you help me
> understand the naming convention?
>
> pci at 5,0 = pci at device 5 function 0 ?

yes

>
> I don't see how we say there's a pci bridge at device 0 function 0 on this
> bus, then specify the devices on the pci bus from there.

the bridge is actually implied by the fact that the node has child
nodes (as in v2). But yes, I see your point.
I don't have time to look today but there is some simple thing wrong.
The devices are straight from v2.

>
> Should we be using the amd8111/pci.dts here too?  Maybe that's why you had
> the phase3_scan = 0, since the pci bus should take care of its scan?
>

Hmm, not sure, ref. v2 again.


I think we should take a careful look at v2 again but I think this is
a  simple problem that just needs
close looking at ...

ron