[coreboot] r910 - in coreboot-v3: arch/x86 mainboard/amd/dbm690t mainboard/amd/serengeti southbridge/amd/amd8111

svn at coreboot.org svn at coreboot.org
Thu Oct 9 16:54:29 CEST 2008


Author: rminnich
Date: 2008-10-09 16:54:29 +0200 (Thu, 09 Oct 2008)
New Revision: 910

Removed:
   coreboot-v3/southbridge/amd/amd8111/amd8111.dts
Modified:
   coreboot-v3/arch/x86/Makefile
   coreboot-v3/mainboard/amd/dbm690t/Makefile
   coreboot-v3/mainboard/amd/serengeti/Makefile
   coreboot-v3/mainboard/amd/serengeti/dts
   coreboot-v3/southbridge/amd/amd8111/amd8111.c
   coreboot-v3/southbridge/amd/amd8111/pci.dts
   coreboot-v3/southbridge/amd/amd8111/usb.c
Log:
This gets us to etherboot again, but this time devices are set 
up correctly on bus 1 --- i.e., the scan of the 8111 bridge works. It 
even 
tries to find the vga rom to run it, which we did not get before. 

the pci bus map built by coreboot matches simnow. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Acked-by: Peter Stuge <peter at stuge.se>


Modified: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3/arch/x86/Makefile	2008-10-08 16:12:32 UTC (rev 909)
+++ coreboot-v3/arch/x86/Makefile	2008-10-09 14:54:29 UTC (rev 910)
@@ -103,7 +103,7 @@
 		       vsprintf.c console.c string.c $(DECOMPRESSORS)
 STAGE0_ARCH_X86_SRC  = stage1.c serial.c \
 		       udelay_io.c mc146818rtc.c post_code.c \
-			pci_ops_conf1.c resourcemap.c 
+			pci_ops_conf1.c 
 # speaker.c \
 
 ifeq ($(CONFIG_PAYLOAD_ELF_LOADER),y)

Modified: coreboot-v3/mainboard/amd/dbm690t/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/dbm690t/Makefile	2008-10-08 16:12:32 UTC (rev 909)
+++ coreboot-v3/mainboard/amd/dbm690t/Makefile	2008-10-09 14:54:29 UTC (rev 910)
@@ -34,6 +34,7 @@
 			$(src)/northbridge/amd/k8/reset_test.c \
 			$(src)/northbridge/amd/k8/coherent_ht.c \
 			$(src)/northbridge/amd/k8/incoherent_ht.c \
+			$(src)/northbridge/amd/k8/coherent_ht.c \
 			$(src)/arch/x86/pci_ops_conf1.c \
 			$(src)/arch/x86/stage1_mtrr.c \
 			$(src)/arch/x86/amd/model_fxx/dualcore.c \

Modified: coreboot-v3/mainboard/amd/serengeti/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/Makefile	2008-10-08 16:12:32 UTC (rev 909)
+++ coreboot-v3/mainboard/amd/serengeti/Makefile	2008-10-09 14:54:29 UTC (rev 910)
@@ -26,6 +26,7 @@
 			$(src)/arch/x86/stage1_mtrr.c \
 			$(src)/arch/x86/amd/model_fxx/dualcore_id.c \
 			$(src)/arch/x86/amd/model_fxx/stage1.c \
+			$(src)/arch/x86/resourcemap.c \
 			$(src)/northbridge/amd/k8/get_nodes.c \
 			$(src)/northbridge/amd/k8/libstage1.c \
 			$(src)/southbridge/amd/amd8111/stage1_smbus.c \

Modified: coreboot-v3/mainboard/amd/serengeti/dts
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/dts	2008-10-08 16:12:32 UTC (rev 909)
+++ coreboot-v3/mainboard/amd/serengeti/dts	2008-10-09 14:54:29 UTC (rev 910)
@@ -32,14 +32,38 @@
 		pci0 at 18,0 {
 			/config/("northbridge/amd/k8/pci");
 			pci at 0,0 {
-				/config/("southbridge/amd/amd8111/amd8111.dts");
+				/config/("southbridge/amd/amd8111/pci.dts");
+				pci at 1,0{
+					/config/("southbridge/amd/amd8111/nic.dts");
+				};
+				pci at 0,0{
+					/config/("southbridge/amd/amd8111/usb.dts");
+				};
+				pci at 0,1{
+					/config/("southbridge/amd/amd8111/usb.dts");
+				};
+				pci at 0,2{
+					/config/("southbridge/amd/amd8111/usb2.dts");
+				};
 			};
-			pci at 4,0 {
+			pci at 7,0 {
+				/config/("southbridge/amd/amd8111/lpc.dts");
+			};
+			pci at 7,1 {
 				/config/("southbridge/amd/amd8111/ide.dts");
 			};
-			pci at 5,0 {
-				/config/("southbridge/amd/amd8111/nic.dts");
+			pci at 7,2 {
+				/config/("southbridge/amd/amd8111/smbus.dts");
 			};
+			pci at 7,3 {
+				/config/("southbridge/amd/amd8111/acpi.dts");
+			};
+			pci at 7,5 {
+				/config/("southbridge/amd/amd8111/ac97audio.dts");
+			};
+			pci at 7,6 {
+				/config/("southbridge/amd/amd8111/ac97modem.dts");
+			};
 		};
 		pci1 at 18,0 {
 			/config/("northbridge/amd/k8/pci");

Modified: coreboot-v3/southbridge/amd/amd8111/amd8111.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/amd8111.c	2008-10-08 16:12:32 UTC (rev 909)
+++ coreboot-v3/southbridge/amd/amd8111/amd8111.c	2008-10-09 14:54:29 UTC (rev 910)
@@ -92,15 +92,3 @@
 	}
 }
 
-struct device_operations amd8111 = {
-	.id = {.type = DEVICE_ID_PCI,
-		{.pci = {.vendor = PCI_VENDOR_ID_AMD,
-			 .device = PCI_DEVICE_ID_AMD_8111_PCI}}},
-	.constructor		 = default_device_constructor,
-	.phase3_scan		 = 0,
-	.phase4_enable_disable	 = amd8111_enable,
-	.phase4_read_resources	 = pci_dev_read_resources,
-	.phase4_set_resources	 = pci_dev_set_resources,
-	.phase6_init		 = NULL,
-	.ops_pci		 = &pci_dev_ops_pci,
-};

Deleted: coreboot-v3/southbridge/amd/amd8111/amd8111.dts
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/amd8111.dts	2008-10-08 16:12:32 UTC (rev 909)
+++ coreboot-v3/southbridge/amd/amd8111/amd8111.dts	2008-10-09 14:54:29 UTC (rev 910)
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-{
-	device_operations = "amd8111";
-};

Modified: coreboot-v3/southbridge/amd/amd8111/pci.dts
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/pci.dts	2008-10-08 16:12:32 UTC (rev 909)
+++ coreboot-v3/southbridge/amd/amd8111/pci.dts	2008-10-09 14:54:29 UTC (rev 910)
@@ -20,4 +20,5 @@
 
 {
 	device_operations = "amd8111_pci";
+	bridge;
 };

Modified: coreboot-v3/southbridge/amd/amd8111/usb.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/usb.c	2008-10-08 16:12:32 UTC (rev 909)
+++ coreboot-v3/southbridge/amd/amd8111/usb.c	2008-10-09 14:54:29 UTC (rev 910)
@@ -50,6 +50,7 @@
 			      .device = PCI_DEVICE_ID_AMD_8111_USB}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = scan_static_bus,
+	.phase4_enable_disable           = amd8111_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,





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