[coreboot] v2 and v3 pci differences

ron minnich rminnich at gmail.com
Fri Oct 10 00:54:10 CEST 2008

On Thu, Oct 9, 2008 at 1:58 PM, Myles Watson <mylesgw at gmail.com> wrote:
> Here are the major differences between v2 and v3 initializing serengeti
> cheetah.  The biggest problem is that the memory-mapped I/O ends up in the
> wrong place (see the Display controller's ROM address)

This one is easy:

      if ((dev->on_mainboard) && (dev->rom_address == 0)) {
                // Skip it if rom_address is not set in MB Config.lb.
                // TODO: No more Config.lb in coreboot-v3.

we have not done it yet.

If anybody wants to get to this before I do, the help is appreciated.
I think it needs a dtc fix.

i.e. in a dts for a part,
rom_address = "fff00000";
and the dtc needs to know this is one of the special properties in the
device struct.


More information about the coreboot mailing list