[coreboot] r3645 - trunk/util/superiotool

svn at coreboot.org svn at coreboot.org
Fri Oct 10 01:56:11 CEST 2008


Author: uwe
Date: 2008-10-10 01:56:11 +0200 (Fri, 10 Oct 2008)
New Revision: 3645

Modified:
   trunk/util/superiotool/fintek.c
Log:
Add Fintek F71882FG support (trivial).

Tested on actual hardware, the MSI K9AG Neo2-Digital (MS-7368).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/util/superiotool/fintek.c
===================================================================
--- trunk/util/superiotool/fintek.c	2008-10-09 17:08:32 UTC (rev 3644)
+++ trunk/util/superiotool/fintek.c	2008-10-09 23:56:11 UTC (rev 3645)
@@ -35,6 +35,48 @@
 	{0x4103, "F71872F/FG / F71806F/FG", {	/* Same ID? Datasheet typo? */
 		{EOT}}},
 	{0x4105, "F71882FG/F71883FG", {		/* Same ID? Datasheet typo? */
+		/* We assume reserved bits are read as 0. */
+		{NOLDN, NULL,
+			{0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,
+			 0x2b,0x2c,0x2d,EOT},
+			{0x05,0x41,0x19,0x34,0x00,0x00,0x00,0x00,0x00,0x00,
+			 0x00,0x08,0x08,EOT}},
+		{0x0, "Floppy",
+			{0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT},
+			{0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}},
+		{0x1, "COM1",
+			{0x30,0x60,0x61,0x70,0xf0,EOT},
+			{0x01,0x03,0xf8,0x04,0x00,EOT}},
+		{0x2, "COM2",
+			{0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
+			{0x01,0x02,0xf8,0x03,0x00,0x04,EOT}},
+		{0x3, "Parallel port",
+			{0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
+			{0x01,0x03,0x78,0x07,0x03,0x42,EOT}},
+		{0x4, "Hardware monitor",
+			{0x30,0x60,0x61,0x70,EOT},
+			{0x01,0x02,0x95,0x00,EOT}},
+		{0x5, "Keyboard",
+			{0x30,0x60,0x61,0x70,0x72,0xf0,EOT},
+			{0x01,0x00,0x60,0x00,0x00,0x83,EOT}},
+		{0x6, "GPIO",
+			{0x70,0xe0,0xe1,0xe2,0xe3,0xd0,0xd1,0xd2,0xd3,0xc0,
+			 0xc1,0xc2,0xc3,0xb0,0xb1,0xb2,0xb3,0xf0,0xf1,0xf2,
+			 0xf3,EOT},
+			{0x00,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,
+			 0x0f,NANA,0x00,0x00,0x0f,NANA,0x00,0x00,0xff,NANA,
+			 0x00,EOT}},
+		{0x7, "VID",
+			{0x30,0x60,0x61,EOT},
+			{0x00,0x00,0x00,EOT}},
+		{0x7, "SPI",
+			{0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,
+			 0xfb,0xfc,0xfd,0xfe,0xff,EOT},
+			{0x10,0x04,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+			 0x00,0x00,0x00,0x00,0x00,EOT}},
+		{0xa, "PME, ACPI",
+			{0x30,0xf0,0xf1,0xf4,0xf5,EOT},
+			{0x00,0x00,0x01,0x06,0x1c,EOT}},
 		{EOT}}},
 	{0x0604, "F71805F/FG", {
 		/* We assume reserved bits are read as 0. */





More information about the coreboot mailing list