[coreboot] r934 - coreboot-v3/southbridge/amd/rs690

svn at coreboot.org svn at coreboot.org
Thu Oct 16 18:02:12 CEST 2008


Author: rminnich
Date: 2008-10-16 18:02:12 +0200 (Thu, 16 Oct 2008)
New Revision: 934

Added:
   coreboot-v3/southbridge/amd/rs690/pcie2.dts
   coreboot-v3/southbridge/amd/rs690/pcie3.dts
   coreboot-v3/southbridge/amd/rs690/pcie4.dts
   coreboot-v3/southbridge/amd/rs690/pcie5.dts
   coreboot-v3/southbridge/amd/rs690/pcie6.dts
   coreboot-v3/southbridge/amd/rs690/pcie7.dts
   coreboot-v3/southbridge/amd/rs690/pcie8.dts
Modified:
   coreboot-v3/southbridge/amd/rs690/pcie.c
Log:
Having received no comments on this pro or con, and knowing we have to 
have this code, I'm comitting it.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: coreboot-v3/southbridge/amd/rs690/pcie.c
===================================================================
--- coreboot-v3/southbridge/amd/rs690/pcie.c	2008-10-16 03:03:33 UTC (rev 933)
+++ coreboot-v3/southbridge/amd/rs690/pcie.c	2008-10-16 16:02:12 UTC (rev 934)
@@ -393,6 +393,7 @@
 	.set_subsystem = 0,
 };
 
+
 struct device_operations rs690_pcie = {
 	.id = {.type = DEVICE_ID_PCI,
 		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
@@ -407,16 +408,94 @@
 	.ops_pci		 = &lops_pci,
 };
 
-/* not yet until we figure out how to handle gpp_configuration and port_enable  -- are they per port or per chip? Should they
- * be per port or per chip? 
-static struct pci_driver pcie_driver_dev7 __pci_driver = {
-	.ops = &pcie_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7,
+/* the rest of these have no phase4_enable_disable; it is all managed by the above device. */
+struct device_operations rs690_pcie2 = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
+			      .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV2}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = pci_scan_bridge,
+	.phase4_read_resources	 = pci_bus_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = pci_bus_enable_resources,
+	.phase6_init		 = pcie_init,
+	.ops_pci		 = &lops_pci,
 };
-static struct pci_driver pcie_driver_dev8 __pci_driver = {
-	.ops = &pcie_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8,
+
+struct device_operations rs690_pcie3 = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
+			      .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV3}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = pci_scan_bridge,
+	.phase4_read_resources	 = pci_bus_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = pci_bus_enable_resources,
+	.phase6_init		 = pcie_init,
+	.ops_pci		 = &lops_pci,
 };
-*/
+
+struct device_operations rs690_pcie4 = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
+			      .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV4}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = pci_scan_bridge,
+	.phase4_read_resources	 = pci_bus_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = pci_bus_enable_resources,
+	.phase6_init		 = pcie_init,
+	.ops_pci		 = &lops_pci,
+};
+
+struct device_operations rs690_pcie5 = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
+			      .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV5}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = pci_scan_bridge,
+	.phase4_read_resources	 = pci_bus_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = pci_bus_enable_resources,
+	.phase6_init		 = pcie_init,
+	.ops_pci		 = &lops_pci,
+};
+
+struct device_operations rs690_pcie6 = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
+			      .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV6}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = pci_scan_bridge,
+	.phase4_read_resources	 = pci_bus_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = pci_bus_enable_resources,
+	.phase6_init		 = pcie_init,
+	.ops_pci		 = &lops_pci,
+};
+
+struct device_operations rs690_pcie7 = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
+			      .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = pci_scan_bridge,
+	.phase4_read_resources	 = pci_bus_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = pci_bus_enable_resources,
+	.phase6_init		 = pcie_init,
+	.ops_pci		 = &lops_pci,
+};
+
+struct device_operations rs690_pcie8 = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
+			      .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = pci_scan_bridge,
+	.phase4_read_resources	 = pci_bus_read_resources,
+	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = pci_bus_enable_resources,
+	.phase6_init		 = pcie_init,
+	.ops_pci		 = &lops_pci,
+};

Added: coreboot-v3/southbridge/amd/rs690/pcie2.dts
===================================================================
--- coreboot-v3/southbridge/amd/rs690/pcie2.dts	                        (rev 0)
+++ coreboot-v3/southbridge/amd/rs690/pcie2.dts	2008-10-16 16:02:12 UTC (rev 934)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+/*
+#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
+#Define vga_rom_address = 0xfff0000
+#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
+ */
+{
+	device_operations	= "rs690_pcie2";
+};

Added: coreboot-v3/southbridge/amd/rs690/pcie3.dts
===================================================================
--- coreboot-v3/southbridge/amd/rs690/pcie3.dts	                        (rev 0)
+++ coreboot-v3/southbridge/amd/rs690/pcie3.dts	2008-10-16 16:02:12 UTC (rev 934)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+/*
+#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
+#Define vga_rom_address = 0xfff0000
+#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
+ */
+{
+	device_operations	= "rs690_pcie3";
+};

Added: coreboot-v3/southbridge/amd/rs690/pcie4.dts
===================================================================
--- coreboot-v3/southbridge/amd/rs690/pcie4.dts	                        (rev 0)
+++ coreboot-v3/southbridge/amd/rs690/pcie4.dts	2008-10-16 16:02:12 UTC (rev 934)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+/*
+#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
+#Define vga_rom_address = 0xfff0000
+#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
+ */
+{
+	device_operations	= "rs690_pcie4";
+};

Added: coreboot-v3/southbridge/amd/rs690/pcie5.dts
===================================================================
--- coreboot-v3/southbridge/amd/rs690/pcie5.dts	                        (rev 0)
+++ coreboot-v3/southbridge/amd/rs690/pcie5.dts	2008-10-16 16:02:12 UTC (rev 934)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+/*
+#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
+#Define vga_rom_address = 0xfff0000
+#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
+ */
+{
+	device_operations	= "rs690_pcie5";
+};

Added: coreboot-v3/southbridge/amd/rs690/pcie6.dts
===================================================================
--- coreboot-v3/southbridge/amd/rs690/pcie6.dts	                        (rev 0)
+++ coreboot-v3/southbridge/amd/rs690/pcie6.dts	2008-10-16 16:02:12 UTC (rev 934)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+/*
+#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
+#Define vga_rom_address = 0xfff0000
+#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
+ */
+{
+	device_operations	= "rs690_pcie6";
+};

Added: coreboot-v3/southbridge/amd/rs690/pcie7.dts
===================================================================
--- coreboot-v3/southbridge/amd/rs690/pcie7.dts	                        (rev 0)
+++ coreboot-v3/southbridge/amd/rs690/pcie7.dts	2008-10-16 16:02:12 UTC (rev 934)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+/*
+#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
+#Define vga_rom_address = 0xfff0000
+#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
+ */
+{
+	device_operations	= "rs690_pcie7";
+};

Added: coreboot-v3/southbridge/amd/rs690/pcie8.dts
===================================================================
--- coreboot-v3/southbridge/amd/rs690/pcie8.dts	                        (rev 0)
+++ coreboot-v3/southbridge/amd/rs690/pcie8.dts	2008-10-16 16:02:12 UTC (rev 934)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+/*
+#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
+#Define vga_rom_address = 0xfff0000
+#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
+ */
+{
+	device_operations	= "rs690_pcie8";
+};





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