[coreboot] [PATCH] workaround v2 VIA ROMCC breakage

Rudolf Marek r.marek at assembler.cz
Thu Oct 16 18:36:55 CEST 2008


> +#if 0
>  	/* Set SPI clock to 33MHz. */
>  	spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c);
>  	(*spireg) &= 0xff00;
> +#endif

This is OK because default is 16MHz, mtrr should handle caching for us.

> +#if 0
>  	if (rom == NULL) {
>  		print_err("No config data specified, using default MAC!\n");
>  		n.mac_address[0] = 0x0;
> @@ -443,6 +446,7 @@
>  		n.checksum = 0x0;
>  		rom = &n;
>  	}
> +#endif
The reason why exactly this needs to be handled in rom stage is that the 
shadow registers needs to be filled _before_ PCI reset, because
PCI reset will force the internal microcontroller to reload with this 
configuration. Its not much documented, only in programming guide,
and there is just assembly code and some strange English ;) they really 
mention that the controller should be reloaded when the device enters D0 
via PCIRST#. Dont know if for example some ->D3 and ->D0 transition will 
work or not.


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