[coreboot] [PATCH] workaround v2 VIA ROMCC breakage
c-d.hailfinger.devel.2006 at gmx.net
Thu Oct 16 20:37:36 CEST 2008
On 16.10.2008 19:59, Eric W. Biederman wrote:
> Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> writes:
>> I'm copying you on this mail because we managed to have ROMCC segfault
>> reliably and choke on another piece of code.
>> On 16.10.2008 18:36, Rudolf Marek wrote:
>>>> +#if 0
>>>> /* Set SPI clock to 33MHz. */
>>>> spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c);
>>>> (*spireg) &= 0xff00;
>>> This is OK because default is 16MHz, mtrr should handle caching for us.
>> ROMCC segfaulted on the code above, so a small rewrite may also fix this
>> problem. Or we could fix ROMCC.
> I would need to get the preprocessed output of that chunk of code
> to see how bad that would be to fix.
Sure. Preprocessed output follows. ROMCC will segfault with the
following command line:
romcc -mcpu=c3 -O auto.E -o auto.inc
Thanks for looking into this!
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
More information about the coreboot